Analog Devices ADSP-BF53x Blackfin, Reference

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Events and Interrupts
4-36 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Depending on how interrupt sources map to the general-purpose interrupt
inputs of the core, the interrupt service routine may have to interrogate
multiple interrupt status bits to determine the source of the interrupt.
One of the first instructions executed in an interrupt service routine
should read
SIC_ISR
to determine whether more than one of the peripher-
als sharing the input has asserted its interrupt output. The service routine
should fully process all pending, shared interrupts before executing the
RTI
, which enables further interrupt generation on that interrupt input.
[
When an interrupt’s service routine is finished, the
RTI
instruction
clears the appropriate bit in the
IPEND
register. However, the rele-
vant
SIC_ISR
bit is not cleared unless the service routine clears the
mechanism that generated the interrupt.
Many systems need relatively few interrupt-enabled peripherals, allowing
each peripheral to map to a unique core priority level. In these designs,
SIC_ISR
will seldom, if ever, need to be interrogated.
The
SIC_ISR
register is not affected by the state of the System Interrupt
Mask register (
SIC_IMASK
) and can be read at any time. Writes to the
SIC_ISR
register have no effect on its contents.
SIC_IMASK Register
The System Interrupt Mask register (
SIC_IMASK
, shown in the System
Interrupt Appendix of the Blackfin Processor Hardware Reference for your
part) allows masking of any peripheral interrupt source at the System
Interrupt Controller (SIC), independently of whether it is enabled at the
peripheral itself.
A reset forces the contents of
SIC_IMASK
to all 0s to mask off all peripheral
interrupts. Writing a 1 to a bit location turns off the mask and enables the
interrupt.