Analog Devices ADSP-BF53x Blackfin, Reference

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L1 Data Memory
6-26 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
The
PORT_PREF0
bit selects the data port used to process DAG0
non-cacheable L2 fetches. Cacheable fetches are always processed by the
data port physically associated with the targeted cache memory. Steering
DAG0, DAG1, and cache traffic to different ports optimizes performance
by keeping the queue to L2 memory full.
L
For optimal performance with dual DAG reads, DAG0 and DAG1
should be configured for different ports. For example, if
PORT_PREF0
is configured as 1, then
PORT_PREF1
should be pro-
grammed to 0.
The
DCBS
bit provides some control over which addresses alias into the
same set. This bit can be used to affect which addresses tend to remain res-
ident in cache by avoiding victimization of repetitively used sets. It has no
affect unless both Data Bank A and Data Bank B are serving as cache (bits
DMC[1:0]
in this register are set to
11
).
The
ENDCPLB
bit is used to enable/disable the 16 Cacheability Protection
Lookaside Buffers (CPLBs) used for data (see “L1 Data Cache” on page
6-29 ). Data CPLBs are disabled by default after reset. When disabled,
only minimal address checking is performed by the L1 memory interface.
This minimal checking generates an exception when the processor:
• Addresses nonexistent (reserved) L1 memory space
• Attempts to perform a nonaligned memory access
• Attempts to access MMR space either using DAG1 or when in
User mode
CPLBs must be disabled using this bit prior to updating their descriptors
(registers
DCPLB_DATAx
and
DCPLB_ADDRx
). Note that since load store order-
ing is weak (see “Ordering of Loads and Stores” on page 6-67 ), disabling
CPLBs should be preceded by a
CSYNC
instruction.
L
When enabling or disabling cache or CPLBs, immediately follow
the write to
DMEM_CONTROL
with a
SSYNC
to ensure proper behavior.