Analog Devices ADSP-BF53x Blackfin, Reference

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 6-3
Memory
The L1 memory provides:
• A modified Harvard architecture, allowing up to four core memory
accesses per clock cycle (one 64-bit instruction fetch, two 32-bit
data loads, and one pipelined 32-bit data store)
• Simultaneous system DMA, cache maintenance, and core accesses
• SRAM access at processor clock rate (
CCLK
) for critical DSP algo-
rithms and fast context switching
Figure 6-1. Processor Memory Architecture
NON-DMA PERIPHERALS
EBIU
DMA
CONTROLLER
L1 MEMORY
CORE
PROCESSOR
INSTRUCTION
LOAD DATA
LOAD DATA
EXTERNAL
MEMORY
DEVICES
64
32
32
16
32
STORE DATA
SYSTEM CLOCK
(SCLK) DOMAIN
CORE CLOCK
(CCLK) DOMAIN
DMA ACCESS BUS
(DAB)
EXTERNAL
PORT
BUS (EPB)
EXTERNAL
ACCESS
BUS (EAB)
DMA
EXTERNAL
BUS (DEB)
DMA
CORE
BUS (DCB)
DMA PERIPHERALS
PERIPHERAL
ACCESS
BUS (PAB)
16
ROM
16
16
16
16
16