Analog Devices ADSP-BF53x Blackfin, Reference

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 6-7
Memory
L1 Instruction SRAM
The processor core reads the instruction memory through the 64-bit wide
instruction fetch bus. All addresses from this bus are 64-bit aligned. Each
instruction fetch can return any combination of 16-, 32- or 64-bit instruc-
tions (for example, four 16-bit instructions, two 16-bit instructions and
one 32-bit instruction, or one 64-bit instruction).
The pointer registers and index registers, which are described in Chapter
5, cannot access L1 Instruction Memory directly. A direct access to an
address in instruction memory SRAM space generates an exception.
Figure 6-2. L1 Instruction Memory Control Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
L1 Instruction Memory Control Register (IMEM_CONTROL)
Reset = 0x0000 0001
ENICPLB (Instruction CPLB
Enable)
LRUPRIORST (LRU
Priority Reset)
0 - LRU priority functionality is enabled
1 - All cached LRU priority bits (LRUPRIO)
are cleared
0 - CPLBs disabled, minimal
address checking only
1 - CPLBs enabled
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ILOC[3:0] (Cache Way Lock)
0000 - All Ways not locked
0001 - Way0 locked, Way1, Way2, and
Way3 not locked
...
1111 - All Ways locked
IMC (L1 Instruction Memory
Configuration)
0 - Upper 16K byte of LI
instruction memory
configured as SRAM,
also invalidates all cache
lines if previously
configured as cache
1 - Upper 16K byte of L1
instruction memory
configured as cache
0xFFE0 1004