Analog Devices ADSP-BF53x Blackfin, Reference

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 15-61
Arithmetic Operations
See “Rounding and Truncating” on page 1-19 for a description of round-
ing behavior.
Options
The Multiply and Multiply-Accumulate to Half-Register instruction sup-
ports operand and Accumulator copy options.
The options are listed in Table 15-4 .
Table 15-4. Multiply and Multiply-Accumulate to Half-Register
Options
Option Description
Default Signed fraction format. Multiply 1.15 * 1.15 formats to produce 1.31 results after
shift correction. The special case of 0x8000 * 0x8000 is saturated to 0x7FFF FFFF
to fit the 1.31 result.
Sign extend 1.31 result to 9.31 format before copying or accumulating to Accumu-
lator. Then, saturate Accumulator to maintain 9.31 precision; Accumulator result
is between minimum 0x80 0000 0000 and maximum 0x7F FFFF FFFF.
To extract to half-register, round Accumulator 9.31 format value at bit 16.
(RND_MOD bit in the ASTAT register controls the rounding.) Saturate the result
to 1.15 precision and copy it to the destination register half. Result is between
minimum -1 and maximum 1-2
-15
(or, expressed in hex, between minimum
0x8000 and maximum 0x7FFF).
(FU) Unsigned fraction format. Multiply 0.16* 0.16 formats to produce 0.32 results.
No shift correction. The special case of 0x8000 * 0x8000 yields 0x4000 0000. No
saturation is necessary since no shift correction occurs.
Zero extend 0.32 result to 8.32 format before copying or accumulating to Accu-
mulator. Then, saturate Accumulator to maintain 8.32 precision; Accumulator
result is between minimum 0x00 0000 0000 and maximum 0xFF FFFF FFFF.
To extract to half-register, round Accumulator 8.32 format value at bit 16.
(RND_MOD bit in the ASTAT register controls the rounding.) Saturate the result
to 0.16 precision and copy it to the destination register half. Result is between
minimum 0 and maximum 1-2
-16
(or, expressed in hex, between minimum 0x0000
and maximum 0xFFFF).