Analog Devices ADSP-BF53x Blackfin, Reference

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Hardware Loops
4-28 ADSP-BF53x/BF56x Blackfin Processor Programming Reference
To avoid unnecessary penalty cycles, the loop hardware follows these
rules:
• Restoring
LC0
and
LC1
registers always re-initializes the loop hard-
ware and causes a ten-cycle “replay” penalty.
• Restoring
LT0
,
LT1
,
LB0
, and
LB1
performs in a single cycle if the
respective loop counter register is zero.
• If
LCx
is non-zero, every write to the
LTx
and
LBx
registers also
attempts to re-initialize the loop hardware and causes a ten-cycle
penalty.
In terms of performance, there is a difference depending on the order that
the loop registers are popped. For best performance, restore the
LCx
regis-
ters last. Furthermore, it is recommended that interrupt service routines
and global subroutines that contain hardware loops terminate their local
loops cleanly, that is, do not artificially break the loops and do not execute
return instructions within their loops. This guarantees that the
LCx
regis-
ters are 0 when
LTx
and
LBx
registers are popped.
Example Code for Using Hardware Loops in an ISR
The following code shows the optimal method of saving and restoring
when using hardware loops in an interrupt service routine.
Listing 4-2. Saving and Restoring With Hardware Loops
lhandler
:
<Save other registers here>
[--SP] = LC0; /* save loop 0 */
[--SP] = LB0;
[--SP] = LT0;
<Handler code here>