Analog Devices ADSP-BF53x Blackfin, Reference

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ADSP-BF53x/BF56x Blackfin Processor Programming Reference 18-9
Video Pixel Operations
as bytes on half-word boundaries in one 32-bit destination register. Some
syntax options load the upper byte in the half-word and others load the
lower byte, as shown in
Table 18-2 , Table 18-4 , and Table 18-4 .
In either case, the unused bytes in the destination register are filled with
0x00.
The 8-bit and 16-bit addition is performed as a signed operation. The
16-bit operand is sign-extended to 32 bits before adding.
The only valid input source register pairs are
R1:0
and
R3:2
.
Table 18-2. Assuming the source registers contain:
31................24 23................16 15..................8 7....................0
aligned_src_reg_0: y1 y0
aligned_src_reg_1: z3 z2 z1 z0
Table 18-3. The versions that load the result into the lower byte–“(LO)”–
produce:
31................24 23................16 15..................8 7....................0
dest_reg: 0 . . . . . 0 y1 + z3 clipped
to 8 bits
0 . . . . . 0 y0 + z1 clipped
to 8 bits
Table 18-4. And the versions that load the result into the higher byte–
“(HI)”–produce:
31................24 23................16 15..................8 7....................0
dest_reg: y1 + z2 clipped
to 8 bits
0 . . . . .0 y0 + z0 clipped
to 8 bits
0 . . . . .0