Altigen ACC 6.7, Administration Manual

Page: 138 / 462

Chapter 11: Board Configuration
124 MAXCS ACC 6.7 Administration Manual
Note: For ideally synchronized systems, Transmit and Receive Frame Slips
counters should be ‘0.’ Continuous update of the frame slips counters means
that transmit and receive frequencies are not equal. In this case, you should
check the system and CT-Bus clock setup.
Setting the Configurable Options
These are the options you can set:
T1/E1 Clocking
Depending on the configuration of the T1/E1 boards and span for your MAXCS
system(s), the
System Clock Master setup should be set according to the follow
conditions:
• If all of the T1/E1 boards are connected to a carrier’s switch, the System Clock
Master check box must not be checked for any of the T1/E1 boards.
Option Notes
Frame Type • For T1, you can set the Frame Type to either SF or ESF .
SF (Superframe Format) consists of 12 consecutive
frames. ESF (Extended Superframe Format) consists of
24 consecutive frames.
• For E1 , you can set the Frame Type to either No CRC or
CRC4 . CRC4 is embedded into 16 consecutive frames.
Line Code
•
For T1, you can set the Line Code to either AMI or
B8ZS . AMI (Alternate Mark Inversion) is the line coding
format in T1 transmission systems whereby successive
ones (marks) are alternately inverted and sent with
opposite polarity of the preceding mark.
B8ZS (Binary 8
Zero Substitution) sends two violations of the bipolar line
encoding technique, rather than inserting a one for every
seven consecutive zeros.
•
For E1 , you can set the Line Code to either AMI or
HDB3 . HDB3 (High Density Bipolar Order) is based on
AMI, but extends this by inserting violation codes
whenever there is a run of four or more zeros.
Zero Code Suppression You can set the Zero Code Suppression to None (default
setting), Jam Bit 8 , GTE or Bell .
Zero Code Suppression inserts a “one” bit to prevent the
transmission of eight or more consecutive “zero” bits; Jam
Bit 8 forces every bit 8 to a one; GTE Zero Code
Suppression replaces bit 8 of an all zero channel byte to a
one, except in signaling frames where bit 7 is forced to a
one.
Bell Zero Code Suppression replaces bit 7 of an all zero
channel byte with a one.
CD Bits Handling CD Bits Handling is not editable.
System Clock Master You can set the System Clock Master if you have a back-
to-back configuration and you want this span to be the
master clock to the system. (Only one clock master should
be selected in a back-to-back system.) See the following
section on T1/E1 clocking.