have been transmitted. The transmit FIFO threshold level (
TXFTLR
) can be used to early interrupt (Transmit
FIFO Empty Interrupt) the processor indicating that the transmit FIFO buffer is nearly empty. †
When the DMA is used in conjunction with the SPI master, the transmit data level (DMATDLR) can be
used to early request the DMA Controller, indicating that the transmit FIFO buffer is nearly empty. The
FIFO buffer can then be refilled with data to continue the serial transfer. The user may also write a block of
data (at least two FIFO buffer entries) into the transmit FIFO buffer before enabling a serial slave. This
ensures that serial transmission does not begin until the number of data frames that make up the continuous
transfer are present in the transmit FIFO buffer. †
When the transfer mode is “receive only” (TMOD = 2), a serial transfer is started by writing one “dummy”
data word into the transmit FIFO buffer when a serial slave is selected. The
txd
output from the SPI controller
is held at a constant logic level for the duration of the serial transfer. The transmit FIFO buffer is popped
only once at the beginning and may remain empty for the duration of the serial transfer. The end of the
serial transfer is controlled by the “number of data frames” (
NDF
) field in control register 1 (
CTRLR1
). †
If, for example, you want to receive 24 data frames from a serial-slave peripheral, you should program the
NDF field with the value 23; the receive logic terminates the serial transfer when the number of frames
received is equal to the NDF value plus one. This transfer mode increases the bandwidth of the system bus
as the transmit FIFO buffer never needs to be serviced during the transfer. The receive FIFO buffer should
be read each time the receive FIFO buffer generates a FIFO full interrupt request to prevent an overflow. †
When the transfer mode is “eeprom_read” (TMOD = 3), a serial transfer is started by writing the opcode
and/or address into the transmit FIFO buffer when a serial slave (EEPROM) is selected. The opcode and
address are transmitted to the EEPROM device, after which read data is received from the EEPROM device
and stored in the receive FIFO buffer. The end of the serial transfer is controlled by the NDF field in the
control register 1 (
CTRLR1
). †
EEPROM read mode is not supported when the SPI controller is configured to be in the SSP mode.
†
Note:
The receive FIFO threshold level (
RXF TLR
) can be used to give early indication that the receive FIFO buffer
is nearly full. When a DMA is used, the receive data level (DMARDLR) can be used to early request the
DMA Controller, indicating that the receive FIFO buffer is nearly full. †
Related Information
•
on page 19-12
•
Texas Instruments Synchronous Serial Protocol (SSP)
on page 19-13
Master Microwire Serial Transfers
“National Semiconductor Microwire Protocol” describes the Microwire serial protocol in detail. †
Microwire serial transfers from the SPI serial master are controlled by the Microwire Control Register
(
MWCR
). The MHS bit field enables and disables the Microwire handshaking interface. The MDD bit field
controls the direction of the data frame (the control frame is always transmitted by the master and received
by the slave). The MWMOD bit field defines whether the transfer is sequential or nonsequential. †
All Microwire transfers are started by the SPI serial master when there is at least one control word in the
transmit FIFO buffer and a slave is enabled. When the SPI master transmits the data frame (MDD =1), the
transfer is terminated by the shift logic when the transmit FIFO buffer is empty. When the SPI master receives
the data frame (MDD = 1), the termination of the transfer depends on the setting of the MWMOD bit field.
If the transfer is nonsequential (MWMOD = 0), it is terminated when the transmit FIFO buffer is empty
after shifting in the data frame from the slave. When the transfer is sequential (MWMOD = 1), it is terminated
Altera Corporation
SPI Controller
19-9
Master Microwire Serial Transfers
cv_54019
2013.12.30
