Altera Cyclone V, Device Handbook

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FPGA-CTI
The FPGA-CTI allows FPGA to send and receive triggers from debug system.
Table 7-6: FPGA-CTI
The following table shows the signal description between FPGA-CTI and FPGA.
Description Signal
Trigger input from FPGA h2f_cti_trig_in[8]
ACK signal to FPGA h2f_cti_trig_in_ack[8]
Trigger output to FGPA h2f_cti_trig_out[8]
ACK signal from FPGA h2f_cti_trig_out_ack[8]
Clock input from FPGA h2f_cti_clk
Clock enable driven by FPGA h2f_cti_fpga_clk_en
Signal from FPGA h2f_cti_asicctl[8]
Related Information
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CTI-NoC
CTI-NoC has all of its triggers available to the NoC interconnect.
TPIU
Signal descriptions between TPIU and FPGA.
Table 7-7: TPIU
Description Signal
Selects whether trace data is captured using the
internal TPIU clock or an external clock provided as
an input to the TPIU from the FPGA.
0 - use h2f_tpiu_clock_in
1 - use internal clock
Note: When the FPGA is powered down or not
configured the TPIU uses the internal clock.
h2f_tpiu_clk_ctl
32 bit trace data bus to the FPGA. Trace data changes
on both edges of h2f_tpiu_clock.
Note: When the FPGA is powered down or not
configured, the TPIU sends the lower 8-bits trace data
to I/Os.
h2f_tpiu_data[32]
Clock from the FPGA used to capture trace data. h2f_tpiu_clock_in
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FPGA-CTI
cv_54007
2013.12.30