• Transmit FIFO Empty Interrupt – Set when the transmit FIFO buffer is equal to or below its threshold
value and requires service to prevent an underrun. The threshold value, set through a software-
programmable register, determines the level of transmit FIFO buffer entries at which an interrupt is
generated. This interrupt is cleared by hardware when data are written into the transmit FIFO buffer,
bringing it over the threshold level. †
• Transmit FIFO Overflow Interrupt – Set when a master attempts to write data into the transmit FIFO
buffer after it has been completely filled. When set, new data writes are discarded. This interrupt remains
set until you read the transmit FIFO overflow interrupt clear register (
TXOICR
). †
• Receive FIFO Full Interrupt – Set when the receive FIFO buffer is equal to or above its threshold value
plus 1 and requires service to prevent an overflow. The threshold value, set through a software-
programmable register, determines the level of receive FIFO buffer entries at which an interrupt is
generated. This interrupt is cleared by hardware when data are read from the receive FIFO buffer, bringing
it below the threshold level. †
• Receive FIFO Overflow Interrupt – Set when the receive logic attempts to place data into the receive
FIFO buffer after it has been completely filled. When set, newly received data are discarded. This interrupt
remains set until you read the receive FIFO overflow interrupt clear register (
RXOICR
). †
• Receive FIFO Underflow Interrupt – Set when a system bus access attempts to read from the receive
FIFO buffer when it is empty. When set, zeros are read back from the receive FIFO buffer. This interrupt
remains set until you read the receive FIFO underflow interrupt clear register (
RXUICR
). †
• Combined Interrupt Request – ORed result of all the above interrupt requests after masking. To mask
this interrupt signal, you must mask all other SPI interrupt requests. †
Transmit FIFO Overflow, Transmit FIFO Empty, Receive FIFO Full, Receive FIFO Underflow, and Receive
FIFO Overflow interrupts can all be masked independently, using the Interrupt Mask Register (
IMR
). †
Transfer Modes
When transferring data on the serial bus, the SPI controller operates one of several modes. The transfer
mode (TMOD) is set by writing to control register 0 (
CTRLR0
).
The transfer mode setting does not affect the duplex of the serial transfer. TMOD is ignored for
Microwire transfers, which are controlled by the MWCR register. †
Note:
Transmit and Receive
When TMOD = 0, both transmit and receive logic are valid. The data transfer occurs as normal according
to the selected frame format (serial protocol). Transmit data are popped from the transmit FIFO buffer and
sent through the
txd
line to the target device, which replies with data on the
rxd
line. The receive data
from the target device is moved from the receive shift register into the receive FIFO buffer at the end of each
data frame. †
Transmit Only
When TMOD = 1, any receive data are ignored. The data transfer occurs as normal, according to the selected
frame format (serial protocol). Transmit data are popped from the transmit FIFO buffer and sent through
the
txd
line to the target device, which replies with data on the
rxd
line. At the end of the data frame, the
receive shift register does not load its newly received data into the receive FIFO buffer. The data in the receive
shift register is overwritten by the next transfer. You should mask interrupts originating from the receive
logic when this mode is entered. †
Receive Only
When TMOD = 2, the transmit data are invalid. In the case of the SPI slave, the transmit FIFO buffer is
never popped in Receive Only mode. The
txd
output remains at a constant logic level during the
SPI Controller
Altera Corporation
cv_54019
Transfer Modes
19-6
2013.12.30
