When ports carry traffic of the same absolute priority, relative priority is determined based on port weighting.
Port weighting is a five-bit value (0-31), and is determined by a deficit-weighted round robin (DWRR)
algorithm, which corrects for past over-servicing or under-servicing of a port. Each port has an associated
weight which is updated every cycle, with a user-configured weight added to it and the amount of traffic
served subtracted from it. The port with the highest weighting is considered the most eligible.
To ensure that high-priority traffic is served quickly and that long and short bursts are effectively interleaved
between ports, incoming transactions longer than a single SDRAM burst are scheduled as a series of SDRAM
bursts, with each burst arbitrated separately.
To ensure that lower priority ports do not build up large running weights while higher priority ports
monopolize bandwidth, the controller's DWRR weights are updated only when a port matches the scheduled
priority. Therefore, if three ports are being accessed, two being priority seven and one being priority four,
the weights for both ports at priority seven are updated but the port with priority four remains unchanged.
Multiport scheduling is performed between all of the ports connected to the FPGA fabric and internally in
the HPS to determine which transaction is serviced next. Arbitration is performed on a SDRAM burst basis
to ensure that a long transaction does not lock other transactions or cause latency to significantly increase
for high-priority ports.
Arbitration supports both absolute and relative priority. Absolute priority is intended for applications where
one master should always get priority above or below others. Relative priority is supported through a
programmable weight field which controls scheduling between ports at the same priority.
The scheduler is work-conserving. Write operations can only be scheduled when enough data for the SDRAM
burst has been received. Read operations can only be scheduled when sufficient internal memory is free and
the port is not occupying too much of the read buffer.
The multiport scheduling configuration can be updated while traffic is flowing. Both priority and weight
for a port can be updated without interrupting traffic on a port. Updates are used in scheduling decisions
within 10 memory clock cycles of being updated, so priority can be updated frequently if needed.
Read Data Handling
The MPFE contains a read buffer shared by all ports. If a port is capable of receiving returned data then the
read buffer is bypassed. If the size of a read transaction is smaller than twice the memory interface width,
the buffer RAM cannot be bypassed.
MPFE SDRAM Burst Scheduling
SDRAM burst scheduling recognizes addresses that access the same row/bank combination, known as open
page accesses. Operations to a page are served in the order in which they are received by the single-port
controller. Selection of SDRAM operations is a two-stage process. First, each pending transaction must wait
for its timers to be eligible for execution. Next, the transaction arbitrates against other transactions that are
also eligible for execution.
The following rules govern transaction arbitration:
• High-priority operations take precedence over lower-priority operations
• If multiple operations are in arbitration, read operations have precedence over write operations
• If multiple operations still exist, the oldest is served first
A high-priority transaction in the SDRAM burst scheduler wins arbitration for that bank immediately if the
bank is idle and the high-priority transaction's chip select, row, or column fields of the address do not match
an address already in the single-port controller. If the bank is not idle, other operations to that bank yield
until the high-priority operation is finished. If the chip select, row, and column fields match an earlier
transaction, the high-priority transaction yields until the earlier transaction is completed.
SDRAM Controller Subsystem
Altera Corporation
cv_54008
MPFE SDRAM Burst Scheduling
8-8
2013.12.30
