For LVDS receivers, the Quartus II software provides an RSKM report showing the SW, TUI, and RSKM
values for non-DPA LVDS mode:
• You can generate the RSKM report by executing the
report_RSKM
command in the TimeQuest Timing
Analyzer. You can find the RSKM report in the Quartus II compilation report in the TimeQuest Timing
Analyzer section.
• To obtain the RSKM value, assign the input delay to the LVDS receiver through the constraints menu of
the TimeQuest Timing Analyzer. The input delay is determined according to the data arrival time at the
LVDS receiver port, with respect to the reference clock.
• If you set the input delay in the settings parameters for the Set Input Delay option, set the clock name
to the clock that reference the source synchronous clock that feeds the LVDS receiver.
• If you do not set any input delay in the TimeQuest Timing Analyzer, the receiver channel-to-channel
skew defaults to zero.
• You can also directly set the input delay in a Synopsys Design Constraint file (.sdc) using the
set_input_delay
command.
Related Information
•
LVDS SERDES Transmitter/Receiver (ALTLVDS_TX and ALTLVDS_RX) Megafunction User Guide
Provides more information about the RSKM equation and calculation.
•
Quartus II TimeQuest Timing Analyzer chapter, Quartus II Development Software Handbook
Provides more information about .sdc commands and the TimeQuest Timing Analyzer.
Document Revision History
Changes
Version
Date
• Added 3.3 V V
CCIO
input for 3.0 V LVTTL/3.0 V LVCMOS and 2.5 V
LVCMOS I/O standards.
2014.01.10
January 2014
• Added 3.3 V input signal for 2.5 V V
CCIO
in the table listing the
MultiVolt I/O support.
• Updated the statement about setting the phase of the clock in relation
to data in the topic about transmitter clocking.
• Updated statements in several topics to clarify that each modular I/O
bank can support multiple I/O standards that use the same voltage.
• Updated the guideline topic about using the same V
CCPD
for I/O banks
in the same V
CCPD
group to improve clarity.
• Added the optional PCI clamp diode to the figure showing the IOE
structure.
• Changed all "SoC FPGA" to "SoC".
• Removed SSTL-125 from the list of supported I/O standards for the
HPS I/O.
• Added SSTL-15, SSTL-135, SSTL-125, HSUL-12, Differential SSTL-15,
Differential SSTL-135, Differential SSTL-125, and Differential HSUL-12
to the list of output termination settings for uncalibrated R
S
OCT.
Altera Corporation
I/O Features in Cyclone V Devices
5-73
Document Revision History
CV-52005
2014.01.10