Altera Cyclone V, Device Handbook

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Rate Match FIFO Behaviors in Custom Double-Width Mode
The different operations available in custom double-width mode for the rate match FIFO are symbol insertion,
symbol deletion, full condition, and empty condition.
Table 5-3: Rate Match FIFO Behaviors in Custom Double-Width Mode (20-bit PMA–PCS Interface Width)
Behavior Operation
Inserts as many pairs (10-bit skip patterns at the
LSByte and MSByte of the 20-bit word at the same
clock cycle) of skip patterns as needed. Symbol Insertion
Deletes as many pairs (10-bit skip patterns at the
LSByte and MSByte of the 20-bit word at the same
clock cycle) of skip patterns as needed. Symbol Deletion
Deletes the pair (20-bit word) of data bytes that causes
the FIFO to go full. Full Condition
Inserts a pair of /K30.7/ ({9'h1FE, 9'h1FE}) after the
data byte that causes the FIFO to go empty. Empty Condition
Standard PCS in Low Latency Configuration
In this configuration, you can customize the transceiver channel to include a PMA and PCS that bypasses
most of the PCS logical functionality for a low latency datapath.
To provide a low latency datapath, the PCS includes only the phase compensation FIFO in phase
compensation mode, and optionally, the byte serializer and byte deserializer blocks, as shown in the following
figure. The transceiver channel interfaces with the FPGA fabric through the PCS.
Transceiver Custom Configurations in Cyclone V Devices
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Rate Match FIFO Behaviors in Custom Double-Width Mode
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2013.05.06