Altera Cyclone V, Device Handbook

Page: 480 / 1077

Table 2-2: Main PLL Output Assignments
Phase Shift Control Frequency Clock Name Output Counter PLL
No
osc1_clk
to varies
(1)
mpu_base_clk
C0
Main
No
osc1_clk
to varies
(1)
main_base_clk
C1
No
osc1_clk
/4 to
mpu_base_clk
/2
dbg_base_clk
C2
No Up to 432 MHz
main_qspi_
base_clk
C3
No Up to 250 MHz for
the NAND flash
controller and up to
200 MHz for the SD/
MMC controller
main_nand_
sdmmc_base_
clk
C4
No
osc1_clk
to
125 MHz for driving
configuration and
100 MHz for the user
clock
cfg_h2f_
user0_base_
clk
C5
The maximum frequency depends on the speed grade of the
device. Note:
The counter outputs from the main PLL can have their frequency further divided by programmable dividers
external to the PLL. Transitions to a different divide value occur on the fastest output clock, one clock cycle
prior to the slowest clock’s rising edge. For example, cycle 15 of the divide-by-16 divider for the main C2
output and cycle 3 of the divide-by-4 divider for the main C0 output.
The following figure shows how each counter output from the main PLL can have its frequency further
divided by programmable post-PLL dividers. Green-colored clock gating logic is directly controlled by
software writing to a register. Orange-colored clock gating logic is controlled by hardware. Orange-colored
clock gating logic allows hardware to seamlessly transition a synchronous set of clocks, for example, all the
MPU subsystem clocks.
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2013.12.30