Figure 6-9: PHYCLK Networks in Cyclone V GX C3 Devices
Left
PLL
Right
PLL
Right
PLL
Sub-Bank
Sub-Bank
I/O Bank 7
Sub-Bank
Sub-Bank
I/O Bank 8
PHYCLK Networks
Sub-Bank
Sub-Bank
I/O Bank 4
Sub-Bank
Sub-Bank
I/O Bank 3
PHYCLK Networks
Sub-Bank
I/O
Bank
6
Sub-Bank
Sub-Bank
I/O
Bank
5
PHYCLK
Networks
Transceiver
Banks
FPGA Device
Sub-Bank
Figure 6-10: PHYCLK Networks in Cyclone V E A7, A5, and A9 Devices, Cyclone V GX C4, C5, C7, and C9
Devices, and Cyclone V GT D5, D7, and D9 Devices
Left
PLL
Right
PLL
Sub-Bank
Sub-Bank
I/O Bank 7
Sub-Bank
Sub-Bank
I/O Bank 8
PHYCLK Networks
Sub-Bank
Sub-Bank
I/O Bank 4
Sub-Bank
Sub-Bank
I/O Bank 3
PHYCLK Networks
Sub-Bank
I/O
Bank
6
Sub-Bank
Sub-Bank
I/O
Bank
5
PHYCLK
Networks
Transceiver
Banks
FPGA Device
Sub-Bank
Left
PLL
Right
PLL
External Memory Interfaces in Cyclone V Devices
Altera Corporation
CV-52006
PHY Clock (PHYCLK) Networks
6-22
2014.01.10