Receive FIFO Buffer Underflow
Setting the source transaction burst length greater than the watermark level can cause underflow where there
is not enough data to service the source burst request. Therefore, the following equation must be adhered
to avoid underflow: †
DMA burst length =
DMATDLR
+ 1
If the number of data items in the receive FIFO buffer is equal to the source burst length at the time of the
burst request is made, the receive FIFO buffer may be emptied, but not underflowed, at the completion of
the burst transaction. For optimal operation, DMA burst length should be set at the watermark level,
DMATDLR
+ 1. †
Adhering to this equation reduces the number of DMA bursts in a block transfer, which in turn can improve
bus utilization. †
The receive FIFO buffer will not be empty at the end of the source burst transaction if the SPI controller
has successfully received one data item or more on the serial receive line during the burst. †
Note:
Figure 19-16: Receive FIFO Buffer
D 1
DMA
Controller
Transmit FIFO
Watermark Level
Data In
Data Out
Empty
Full
Receive
FIFO Buffer
SPI Controller Address Map and Register Definitions
The address map and register definitions reside in hps.html file that accompanies this handbook volume.
Click the link to open the file.
To view the module description and base address, scroll to and click the link for any of the following module
instances:
• spis0
• spis1
• spim0
• spim1
To then view the register and field descriptions, scroll to and click the register names. The register addresses
are offsets relative to the base address of each module instance.
Related Information
•
Introduction to Cyclone V Hard Processor System (HPS)
on page 1-1
The base addresses of all modules are also listed in the
Introduction to the Hard Processor System
chapter.
•
For more information, refer to
hps.html
.
Altera Corporation
SPI Controller
19-27
Receive FIFO Buffer Underflow
cv_54019
2013.12.30
