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Altera Cyclone V, Device Handbook

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DQS Delay Chain

DQS delay chains consist of a set of variable delay elements to allow the input DQS signals to be shifted by
the amount specified by the DQS phase-shift circuitry or the logic array.

There are two delay elements in the DQS delay chain that have the same characteristics:

• Delay elements in the DQS logic block
• Delay elements in the DLL

The DQS pin is shifted by the DQS delay settings.

The number of delay chains required is transparent because the UniPHY IP automatically sets it when you
choose the operating frequency.

In the Cyclone V SE, SX, and ST devices, the DQS delay chain is controlled by the DQS phase-shift circuitry
only.

Related Information

•

ALTDQ_DQS2 Megafunction User Guide

Provides more information about programming the delay chains.

•

Delay Chains

on page 6-28

DQS Postamble Circuitry

There are preamble and postamble specifications for both read and write operations in DDR3 and DDR2
SDRAM. The DQS postamble circuitry ensures that data is not lost if there is noise on the DQS line during
the end of a read operation that occurs while DQS is in a postamble state.

The Cyclone V devices contain dedicated postamble registers that you can control to ground the shifted
DQS signal that is used to clock the DQ input registers at the end of a read operation. This function ensures
that any glitches on the DQS input signal during the end of a read operation and occurring while DQS is in
a postamble state do not affect the DQ IOE registers.

• For preamble state, the DQS is low, just after a high-impedance state.
• For postamble state, the DQS is low, just before it returns to a high-impedance state.

For external memory interfaces that use a bidirectional read strobe (DDR3 and DDR2 SDRAM), the DQS
signal is low before going to or coming from a high-impedance state.

Half Data Rate Block

The Cyclone V devices contain a half data rate (HDR) block in the postamble enable circuitry.

The HDR block is clocked by the half-rate resynchronization clock, which is the output of the I/O clock
divider circuit. There is an AND gate after the postamble register outputs to avoid postamble glitches from
a previous read burst on a non-consecutive read burst. This scheme allows half-a-clock cycle latency for

dqsenable

assertion and zero latency for

dqsenable

deassertion.

Using the HDR block as the first stage capture register in the postamble enable circuitry block is optional.
Altera recommends using these registers if the controller is running at half the frequency of the I/Os.

Altera Corporation

External Memory Interfaces in Cyclone V Devices

Send Feedback

6-25

DQS Delay Chain

CV-52006
2014.01.10

Summary of Contents for Cyclone V

Page 1: ...Cyclone V Device Handbook Volume 1 Device Interfaces and Integration 101 Innovation Drive San Jose CA 95134 www altera com CV 5V2 2014 01 10 Subscribe Send Feedback ...

Page 2: ...sider the Memory Block Selection 2 2 Guideline Implement External Conflict Resolution 2 3 Guideline Customize Read During Write Behavior 2 3 Guideline Consider Power Up State and Memory Initialization 2 6 Guideline Control Clocking to Reduce Power Consumption 2 7 Embedded Memory Features 2 7 Embedded Memory Configurations 2 8 Mixed Width Port Configurations 2 9 Embedded Memory Modes 2 10 Embedded ...

Page 3: ...ut Adder 3 4 Block Architecture 3 5 Input Register Bank 3 6 Pre Adder 3 8 Internal Coefficient 3 8 Multipliers 3 8 Adder 3 9 Accumulator and Chainout Adder 3 9 Systolic Registers 3 10 Double Accumulation Register 3 10 Output Register Bank 3 10 Operational Mode Descriptions 3 10 Independent Multiplier Mode 3 11 Independent Complex Multiplier Mode 3 13 Multiplier Adder Sum Mode 3 15 18 x 18 Multipli...

Page 4: ...Phase Shift 4 37 Document Revision History 4 38 I O Features in Cyclone V Devices 5 1 I O Resources Per Package for Cyclone V Devices 5 1 I O Vertical Migration for Cyclone V Devices 5 4 Verifying Pin Migration Compatibility 5 5 I O Standards Support in Cyclone V Devices 5 5 I O Standards Support for FPGA I O in Cyclone V Devices 5 5 I O Standards Support for HPS I O in Cyclone V Devices 5 7 I O S...

Page 5: ...s 5 29 Programmable Current Strength 5 30 Programmable Output Slew Rate Control 5 31 Programmable IOE Delay 5 31 Programmable Output Buffer Delay 5 31 Programmable Pre Emphasis 5 32 Programmable Differential Output Voltage 5 32 I O Pins Features for Cyclone V Devices 5 33 Open Drain Output 5 33 Bus Hold Circuitry 5 33 Pull up Resistor 5 34 On Chip I O Termination in Cyclone V Devices 5 34 RS OCT w...

Page 6: ...ument Revision History 5 73 External Memory Interfaces in Cyclone V Devices 6 1 External Memory Performance 6 2 HPS External Memory Performance 6 2 Memory Interface Pin Support in Cyclone V Devices 6 2 Guideline Using DQ DQS Pins 6 3 DQ DQS Bus Mode Pins for Cyclone V Devices 6 3 DQ DQS Groups in Cyclone V E 6 5 DQ DQS Groups in Cyclone V GX 6 7 DQ DQS Groups in Cyclone V GT 6 9 DQ DQS Groups in C...

Page 7: ... 7 1 MSEL Pin Settings 7 2 Configuration Sequence 7 3 Power Up 7 4 Reset 7 5 Configuration 7 5 Configuration Error Handling 7 5 Initialization 7 6 User Mode 7 6 Device Configuration Pins 7 6 Configuration Pin Options in the Quartus II Software 7 8 Fast Passive Parallel Configuration 7 9 Fast Passive Parallel Single Device Configuration 7 9 Fast Passive Parallel Multi Device Configuration 7 10 Acti...

Page 8: ...equence in the Remote Update Mode 7 30 Remote System Upgrade Circuitry 7 31 Enabling Remote System Upgrade Circuitry 7 31 Remote System Upgrade Registers 7 32 Remote System Upgrade State Machine 7 34 User Watchdog Timer 7 34 Design Security 7 34 ALTCHIP_ID Megafunction 7 35 JTAG Secure Mode 7 35 Security Key Types 7 36 Security Modes 7 37 Design Security Implementation Steps 7 37 Document Revision...

Page 9: ...1 BST Circuitry 9 8 Guidelines for IEEE Std 1149 1 Boundary Scan Testing 9 9 IEEE Std 1149 1 Boundary Scan Register 9 9 Boundary Scan Cells of a Cyclone V Device I O Pin 9 10 Document Revision History 9 12 Power Management in Cyclone V Devices 10 1 Power Consumption 10 1 Dynamic Power Equation 10 1 Hot Socketing Feature 10 2 Hot Socketing Implementation 10 2 Power Up Sequence 10 4 Power On Reset C...

Page 10: ... logic resources Each LAB contains dedicated logic for driving control signals to its ALMs MLAB is a superset of the LAB and includes all the LAB features ISO 9001 2008 Registered 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office a...

Page 11: ... C12 R14 R3 R6 Direct Link Interconnect from Adjacent Block Direct Link Interconnect to Adjacent Block Direct Link Interconnect to Adjacent Block Direct Link Interconnect from Adjacent Block Connects to adjacent LABs memory blocks digital signal processing DSP blocks or I O element IOE outputs MLAB Each MLAB supports a maximum of 640 bits of simple dual port SRAM You can configure each ALM in an M...

Page 12: ...ALM as a regular LAB ALM or configure it as a dual port SRAM Local and Direct Link Interconnects Each LAB can drive 30 ALMs through fast local and direct link interconnects Ten ALMs are in any given LAB and ten ALMs are in each of the adjacent LABs The local interconnect can drive ALMs in the same LAB using column and row interconnects and ALM outputs in the same LAB Neighboring LABs MLABs M10K bl...

Page 13: ...B Control Signals Each LAB contains dedicated logic for driving the control signals to its ALMs and has two unique clock sources and three clock enable signals The LAB control block generates up to three clocks using the two clock sources and three clock enable signals Each clock and the clock enable signals are linked De asserting the clock enable signal turns off the corresponding LAB wide clock...

Page 14: ...Each register has the following ports Data Clock Synchronous and asynchronous clear Synchronous load Global signals general purpose I O GPIO pins or any internal logic can drive the clock and clear control signals of an ALM register GPIO pins or internal logic drives the clock enable signal For combinational functions the registers are bypassed and the output of the look up table LUT drives direct...

Page 15: ...tputs can also drive local interconnect resources The LUT adder or register output can drive the ALM outputs The LUT or adder can drive one output while the register drives another output Register packing improves device utilization by allowing unrelated register and combinational logic to be packed into a single ALM Another mechanism to improve fitting is to allow the register output to feed back...

Page 16: ...ut LUT 3 Input LUT 3 Input LUT 3 Input LUT dataf0 datae0 dataa datab datac1 datae1 dataf1 datac0 Row Column Direct Link Routing Row Column Direct Link Routing Row Column Direct Link Routing ALM Operating Modes The Cyclone V ALM operates in any of the following modes Normal mode Extended LUT mode Arithmetic mode Shared arithmetic mode Altera Corporation Logic Array Blocks and Adaptive Logic Modules...

Page 17: ...t Functions in Extended LUT Mode for Cyclone V Devices datae0 combout0 5 Input LUT 5 Input LUT datac dataa datab datad dataf0 datae1 dataf1 D Q reg0 This input is available for register packing To General or Local Routing Arithmetic Mode The ALM in arithmetic mode uses two sets of two 4 input LUTs along with two dedicated full adders The dedicated adders allow the LUTs to perform pre adder logic t...

Page 18: ...tions in normal mode Carry chains that use the top five ALMs in the first LAB carry into the top half of the ALMs in the next LAB in the column Carry chains that use the bottom five ALMs in the first LAB carry into the bottom half of the ALMs in the next LAB within the column You can bypass the top half of the LAB columns and bottom half of the MLAB columns The Quartus II Compiler creates carry ch...

Page 19: ...rithmetic chains in alternate LAB columns can be bypassed This capability allows the shared arithmetic chain to cascade through half of the ALMs in an LAB while leaving the other half available for narrower fan in functionality In every LAB the column is top half bypassable while in MLAB columns are bottom half bypassable The Quartus II Compiler creates shared arithmetic chains longer than 20 ALMs...

Page 20: ...ument issues in the Knowledge Base Removed register chain outputs information in ALM output section Removed reg_chain_in and reg_chain_out ports in ALM high level block diagram and ALM connection details diagram 2013 05 06 May 2013 Reorganized content and updated template 2012 12 28 December 2012 Updated for the Quartus II software v12 0 release Restructured chapter Updated Figure 1 6 2 0 June 201...

Page 21: ...e V Devices Table 2 1 Embedded Memory Capacity and Distribution in Cyclone V Devices Total RAM Bit Kb MLAB M10K Member Code Variant RAM Bit Kb Block RAM Bit Kb Block 1 956 196 314 1 760 176 A2 Cyclone V E 3 383 303 485 3 080 308 A4 4 884 424 679 4 460 446 A5 7 696 836 1338 6 860 686 A7 13 917 1 717 2748 12 200 1 220 A9 ISO 9001 2008 Registered 2014 Altera Corporation All rights reserved ALTERA ARR...

Page 22: ...ariants of this device family Guideline Consider the Memory Block Selection The Quartus II software automatically partitions the user defined memory into the memory blocks based on your design s speed and size constraints For example the Quartus II software may spread out the memory across multiple available memory blocks to increase the performance of the design To assign the memory to a specific...

Page 23: ...n Port B data in Port A data out Port B data out Mixed port data flow Same port data flow FPGA Device Same Port Read During Write Mode The same port read during write mode applies to a single port RAM or the same port of a true dual port RAM Table 2 2 Output Modes for Embedded Memory Blocks in Same Port Read During Write Mode This table lists the available output modes if you select the embedded m...

Page 24: ... the new data on the next rising edge after the data is written to the MLAB memory This mode is available only if the output is registered MLAB new data A read during write operation to different ports causes the RAM output to reflect the old data value at the particular address For MLAB this mode is available only if the output is registered M10K MLAB old data The RAM outputs don t care or unknow...

Page 25: ...a wren_a byteena_a rden_b data_a q_b registered address_b AAAA BBBB CCCC DDDD EEEE FFFF A0 A1 A0 A1 AAAA BBBB CCCC DDDD EEEE FFFF Figure 2 4 Mixed Port Read During Write Old Data Mode This figure shows a sample functional waveform of mixed port read during write behavior for the old data mode clk_a b address_a wren_a byteena_a rden_b data_a q_b asynch address_b A0 A1 AAAA BBBB CCCC DDDD EEEE FFFF ...

Page 26: ...on Consider the power up state of the different types of memory blocks if you are designing logic that evaluates the initial power up values as listed in the following table Table 2 4 Initial Power Up Values of Embedded Memory Blocks Power Up Value Output Registers Memory Type Zero cleared Used MLAB Read memory contents Bypassed Zero cleared Used M10K Zero cleared Bypassed By default the Quartus I...

Page 27: ...power mode to reduce static power Embedded Memory Features Table 2 5 Memory Features in Cyclone V Devices This table summarizes the features supported by the embedded memory blocks MLAB M10K Features 420 MHz 315 MHz Maximum operating frequency 640 10 240 Total RAM bits including parity bits Supported Supported Parity bits Supported Supported Byte enable Supported Packed mode Supported Supported Ad...

Page 28: ...d port read during write Soft IP support using the Quartus II software Soft IP support using the Quartus II software ECC support Related Information Internal Memory RAM and ROM User Guide Provides more information about the embedded memory features Embedded Memory Configurations Table 2 6 Supported Embedded Memory Block Configurations for Cyclone V Devices This table lists the maximum configuratio...

Page 29: ...Yes Yes Yes Yes Yes Yes 8K x 1 Yes Yes Yes Yes Yes Yes 4K x 2 Yes Yes Yes Yes Yes Yes 2K x 4 Yes Yes Yes Yes 2K x 5 Yes Yes Yes Yes Yes Yes 1K x 8 Yes Yes Yes Yes 1K x 10 Yes Yes Yes Yes Yes Yes 512 x 16 Yes Yes Yes Yes 512 x 20 Yes Yes Yes Yes Yes Yes 256 x 32 Yes Yes Yes Yes 256 x 40 Table 2 8 M10K Block Mixed Width Configurations in True Dual Port Mode Port A Port B 512 x 20 512 x 16 1K x 10 1K...

Page 30: ...t the same address location do not create a read enable signal or activate the read enable during a write operation Yes Yes Single port RAM You can simultaneously perform one read and one write operations to different locations where the write operation happens on port A and the read operation happens on port B Yes Yes Simple dual port RAM You can perform any combination of two port operations two...

Page 31: ...ed Information Internal Memory RAM and ROM User Guide Provides more information memory modes RAM Based Shift Register ALTSHIFT_TAPS Megafunction User Guide Provides more information about implementing the shift register mode SCFIFO and DCFIFO Megafunctions User Guide Provides more information about implementing FIFO buffers Embedded Memory Clocking Modes This section describes the clocking modes f...

Page 32: ...ndependent Clock Mode In the independent clock mode a separate clock is available for each port A and B Clock A controls all registers on the port A side clock B controls all registers on the port B side You can create independent clock enable for different input and output registers to control the shut down of a particular register for power saving purposes From the parameter editor click More Op...

Page 33: ...e operations Parity function is not performed on the parity bit Byte Enable in Embedded Memory Blocks The embedded memory blocks support byte enable controls The byte enable controls mask the input data so that only specific bytes of data are written The unwritten bytes retain the values written previously The write enable wren signal together with the byte enable byteena signal control the write ...

Page 34: ...g masked data byte output appears as a don t care value In MLABs when you de assert a byte enable bit during a write cycle the corresponding data byte output appears as either a don t care value or the current data at that location You can control the output value for the masked byte in the MLABs by using the Quartus II software Embedded Memory Blocks in Cyclone V Devices Altera Corporation Send F...

Page 35: ...d Mode Support The M10K memory blocks support packed mode The packed mode feature packs two independent single port RAM blocks into one memory block The Quartus II software automatically implements packed mode where appropriate by placing the physical RAM block in true dual port mode and using the MSB of the address to distinguish between the two logical RAM blocks The size of each independent sin...

Page 36: ... 0 Figure 2 8 Address Clock Enable During Read Cycle Waveform This figure shows the address clock enable waveform during the read cycle inclock rden rdaddress q synch a0 a1 a2 a3 a4 a5 a6 q asynch an a0 a4 a5 latched address inside memory dout0 dout1 dout4 dout4 dout5 addressstall a1 doutn 1 doutn doutn dout0 dout1 Embedded Memory Blocks in Cyclone V Devices Altera Corporation Send Feedback CV 520...

Page 37: ...dge Base Updated the maximum operating frequency of the MLAB Corrected the description about the don t care output mode for RAM in mixed port read during write Reorganized the structure of the supported memory configurations topics single port and mixed width dual port to improve clarity about maximum data widths supported for each configuration Addedadescriptiontothetablelistingthemaximumembedded...

Page 38: ...cked mode support Added topic about the address clock enable support 2012 12 28 December 2012 Restructured the chapter Updated the Memory Modes Clocking Modes and Design Considerations sections Updated Table 2 1 Added the Parity Bit and Byte Enable sections Moved the memory capacity information to the Cyclone V Device Overview 2 0 June 2012 Initial release 1 0 October 2011 Embedded Memory Blocks i...

Page 39: ... and 27 bit systolic finite impulse response FIR filters with distributed output adder Related Information Cyclone V Device Overview Provides more information about the number of multipliers in each Cyclone V device ISO 9001 2008 Registered 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corpor...

Page 40: ...Independent 18 x 19 multiplication Yes Yes Yes Yes 1 Independent 18 x 25 multiplication Yes Yes Yes Yes 1 Independent 20 x 24 multiplication Yes Yes Yes Yes 1 Independent 27 x 27 multiplication Yes Yes Yes Yes 1 Two 18 x 19 multiplier adder mode Yes No No Yes 1 18 x 18 multiplier adder summed with 36 bit input No Yes No No 1 Complex 18 x 19 multiplication 2 variable precision DSP blocks 1 When you...

Page 41: ...156 156 312 468 156 A7 342 342 342 684 1 026 342 A9 51 51 51 102 153 51 C3 Cyclone V GX 70 70 70 140 210 70 C4 150 150 150 300 450 150 C5 156 156 156 312 468 156 C7 342 342 342 684 1 026 342 C9 150 150 150 300 450 150 D5 Cyclone V GT 156 156 156 312 468 156 D7 342 342 342 684 1 026 342 D9 36 36 36 72 108 36 A2 Cyclone V SE 84 84 84 168 252 84 A4 87 87 87 174 261 87 A5 112 112 112 224 336 112 A6 36...

Page 42: ...COMPLEX Related Information Introduction to Megafunction User Guide Integer Arithmetic Megafunctions User Guide Floating Point Megafunctions User Guide Quartus II Software Help Internal Coefficient and Pre Adder To use the pre adder feature all input data and multipliers must have the same clock setting The input cascade support is not available when you enable the pre adder feature In both 18 bit...

Page 43: ...in scanout LOADCONST ACCUMULATE NEGATE dataa_y0 18 0 dataa_z0 17 0 dataa_x0 17 0 COEFSELA 2 0 datab_y1 18 0 datab_z1 17 0 datab_x1 17 0 COEFSELB 2 0 SUB_COMPLEX Pre Adder Pre Adder Internal Coefficient Internal Coefficient Multiplier Adder Systolic Registers 1 Systolic Register 1 Chainout adder accumulator Output Register Bank Constant Double Accumulation Register chainin 63 0 chainout 63 0 Result...

Page 44: ...ls control the input registers within the variable precision DSP block CLK 2 0 ENA 2 0 ACLR 0 In 18 x 19 mode you can use the delay registers to balance the latency requirements when you use both the input cascade and chainout features The tap delay line feature allows you to drive the top leg of the multiplier input dataa_y0 and datab_y1 in 18 x 19 mode and dataa_y0 only in 27 x 27 mode from the ...

Page 45: ... Registers for the control signals are not shown dataa_y0 18 0 dataa_z0 17 0 dataa_x0 17 0 datab_y1 18 0 Delay registers datab_z1 17 0 datab_x1 17 0 Delay registers scanin 18 0 scanout 18 0 CLK 2 0 ENA 2 0 ACLR 0 Altera Corporation Variable Precision DSP Blocks in Cyclone V Devices Send Feedback 3 7 Input Register Bank CV 52003 2014 01 10 ...

Page 46: ...action for 18 x 19 mode 17 bit unsigned addition or subtraction for 18 x 19 mode 26 bit addition or subtraction for 27 x 27 mode Internal Coefficient The Cyclone V variable precision DSP block has the flexibility of selecting the multiplicand from either the dynamic input or the internal coefficient The internal coefficient can support up to eight constant coefficients for the multiplicands in 18 ...

Page 47: ... 64 bit adder The following signals can dynamically control the function of the accumulator NEGATE LOADCONST ACCUMULATE The accumulator supports double accumulation by enabling the 64 bit double accumulation registers located between the output register bank and the accumulator The double accumulation registers are set statically in the programming file The accumulator and chainout adder features ...

Page 48: ...ccumulation Register The double accumulation register is an extra register in the feedback path of the accumulator Enabling the double accumulation register will cause an extra clock cycle delay in the feedback path of the accumulator This register has the same CLK ENA and ACLR settings as the output register bank By enabling this register you can have two accumulator channels using the same numbe...

Page 49: ... 3 9 x 9 2 18 signed x 18 unsigned 18 unsigned x 18 unsigned 18 signed x 19 signed 18 unsigned x 19 signed 1 18 x 25 1 20 x 24 1 27 x 27 9 x 9 Independent Multiplier Figure 3 4 Three 9 x 9 Independent Multiplier Mode per Variable Precision DSP Block for Cyclone V Devices Three pairs of data are packed into the ax and ay ports result contains three 18 bit products Input Register Bank Multiplier x R...

Page 50: ...lock data_b0 n 1 0 data_a0 17 0 n 18 m m 1 0 m Output Register Bank 18 x 25 Independent Multiplier Figure 3 6 One 18 x 25 Independent Multiplier Mode per Variable Precision DSP Block for Cyclone V Devices In this mode the result can be up to 52 bits when combined with a chainout adder or accumulator Input Register Bank Multiplier Result 42 0 dataa_b0 17 0 dataa_a0 24 0 18 25 43 Variable Precision ...

Page 51: ...sult can be up to 64 bits when combined with a chainout adder or accumulator Input Register Bank Multiplier x Result 53 0 dataa_b0 26 0 dataa_a0 26 0 27 27 54 Variable Precision DSP Block Output Register Bank Independent Complex Multiplier Mode The Cyclone V devices support the 18 x 19 complex multiplier mode using two Cyclone V variable precision DSP blocks Figure 3 9 Sample of Complex Multiplica...

Page 52: ... Register Bank Imaginary Part ad bc Multiplier c 18 0 b 17 0 19 18 Multiplier d 18 0 a 17 0 19 18 38 Adder x x Output Register Bank Input Register Bank Real Part ac bd d 18 0 b 17 0 19 18 c 18 0 a 17 0 19 18 38 Output Register Bank Multiplier Multiplier Adder x x Variable Precision DSP Blocks in Cyclone V Devices Altera Corporation Send Feedback CV 52003 18 x 19 Complex Multiplier 3 14 2014 01 10 ...

Page 53: ... to provide the input for an 18 x 18 multiplication while the bottom multiplier is bypassed The datab_y1 17 0 and datab_y1 35 18 signals are concatenated to produce a 36 bit input Figure 3 12 One 18 x 18 Multiplication Summed with 36 Bit Input Mode for Cyclone V Devices Input Register Bank Result 36 0 dataa_y0 17 0 dataa_x0 17 0 18 18 Variable Precision DSP Block datab_y1 35 18 datab_y1 17 0 18 18...

Page 54: ...locks support the following systolic FIR structures 18 bit 27 bit In systolic FIR mode the input of the multiplier can come from four different sets of sources Two dynamic inputs One dynamic input and one coefficient input One coefficient input and one pre adder output One dynamic input and one pre adder output 18 Bit Systolic FIR Mode In 18 bit systolic FIR mode the adders are configured as dual ...

Page 55: ... bit Systolic FIR x x Note 1 The systolic registers have the same clock source as the output register bank 18 18 18 18 18 18 3 3 44 44 44 27 Bit Systolic FIR Mode In 27 bit systolic FIR mode the chainout adder or accumulator is configured for a 64 bit operation providing 10 bits of overhead when using a 27 bit data 54 bit products This allows a total of 1 024 multiplier products The 27 bit systoli...

Page 56: ...one V SE A4 from 116 to 168 Corrected 9 x 9 multiplier for Cyclone V SE A4 from 174 to 252 2014 01 10 January 2014 Added link to the known document issues in the Knowledge Base Moved all links to the Related Information section of respective topics for easy reference Updated the variable DSP blocks and multipliers counts for the Cyclone V SX device variants 2013 05 06 May 2013 Added resources for ...

Page 57: ...tion Register sections Updated Figure 3 1 and Figure 3 13 Added Table 3 3 Updated Systolic Registers and Systolic FIR Mode sections Added Equation 3 2 Added Figure 3 12 2 0 June 2012 Initial release 1 0 May 2011 Altera Corporation Variable Precision DSP Blocks in Cyclone V Devices Send Feedback 3 19 Document Revision History CV 52003 2014 01 10 ...

Page 58: ...UARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in ac...

Page 59: ... single ended or 6 differential Cyclone V SE A2 and A4 Cyclone V SX C2 and C4 CLK 0 11 p n pins PLL clock outputs and logic array GCLK networks 16 RCLK networks 88 Cyclone V E A5 A7 and A9 Cyclone V GX C4 C5 C7 and C9 Cyclone V GT D5 D7 and D9 GCLK and RCLK networks CLK 0 3 p n CLK 6 p n CLK 8 11 p n pins PLL clock outputs and logic array Cyclone V E A2 and A4 Cyclone V GX C3 CLK 0 3 p n and CLK 6...

Page 60: ...r to the pin connection guidelines Related Information Cyclone V Device Family Pin Connection Guidelines Types of Clock Networks Global Clock Networks Cyclone V devices provide GCLKs that can drive throughout the device The GCLKs serve as low skew clock sources for functional blocks such as adaptive logic modules ALMs digital signal processing DSP embedded memory and PLLs Cyclone V I O elements IO...

Page 61: ... silicon die that corresponds to a reverse view of the device package GCLK 12 15 GCLK 8 11 GCLK 4 7 GCLK 0 3 Q1 Q4 Q2 Q3 CLK 0 3 p n CLK 6 7 p n CLK 4 5 p n GCLK network is not available in quadrant 2 for Cyclone V SE A5 and A6 devices Cyclone V ST D5 and D6 devices and Cyclone V SX C5 and C6 devices Regional Clock Networks RCLK networks are only applicable to the quadrant they drive into RCLK net...

Page 62: ...RCLK Networks in Cyclone V SE SX and ST Devices This figure represents the top view of the silicon die that corresponds to a reverse view of the device package RCLK 64 69 RCLK 70 75 RCLK 82 87 RCLK 76 81 RCLK 58 63 RCLK 52 57 RCLK 40 45 RCLK 0 9 RCLK 30 39 RCLK 20 29 CLK 6 7 p n CLK 0 3 p n CLK 4 5 p n Q1 Q2 Q3 Q4 RCLK network is not available in quadrant 2 for Cyclone V SE A5 and A6 devices and C...

Page 63: ... represents the top view of the silicon die that corresponds to a reverse view of the device package Q1 Q2 Q4 Q3 Horizontal PCLK Horizontal PCLK Horizontal PCLK Horizontal PCLK CLK 0 3 p n CLK 8 11 p n CLK 4 7 p n For Cyclone V E A2 and A4 devices and Cyclone V GX C3 device only CLK 6 p n pins are available Clock Networks and PLLs in Cyclone V Devices Altera Corporation Send Feedback CV 52004 Peri...

Page 64: ... O interfaces of the device A spine clock is another layer of routing between the GCLK RCLK and PCLK networks before each clock is connected to the clock routing for each LAB row The settings for spine clocks are transparent The Quartus II software automatically routes the spine clock based on the GCLK RCLK and PCLK networks The following figure shows SCLKs driven by the GCLK RCLK PCLK or the PLL ...

Page 65: ... entire device The source is not necessarily a clock signal This clock region has the maximum insertion delay when compared with other clock regions but allows the signal to reach every destination in the device It is a good option for routing global reset and clear signals or routing clocks throughout the device Regional Clock Region To form a regional clock region a source drives a signal in a R...

Page 66: ...ly the CLK p pins have dedicated connections to the PLL The CLK n pins drive the PLLs over global or regional clock networks and do not have dedicated routing paths to the PLLs Driving a PLL over a global or regional clock can lead to higher jitter at the PLL input and the PLL will not be able to fully compensate for the global or regional clock Altera recommends using the CLK p pins for optimal p...

Page 67: ...ated Clock Input Pin Connectivity to the RCLK Networks for Cyclone V E GX and GT Devices A given clock input pin can drive two adjacent RCLK networks to create a dual regional clock network CLK p n Pins Clock Resources CLK 0 RCLK 20 24 28 30 34 38 58 59 60 61 62 63 64 68 82 86 CLK 1 RCLK 21 25 29 31 35 39 58 59 60 61 62 63 65 69 83 87 CLK 2 RCLK 22 26 32 36 52 53 54 55 56 57 58 59 60 61 62 63 66 8...

Page 68: ... 58 59 60 61 62 63 66 84 CLK 3 RCLK 23 27 33 37 52 53 54 55 56 57 58 59 60 61 62 63 67 85 CLK 4 3 RCLK 52 53 54 55 56 57 78 CLK 5 3 RCLK 52 53 54 55 56 57 79 CLK 6 RCLK 0 4 8 40 41 42 43 44 45 64 68 82 86 CLK 7 RCLK 1 5 9 40 41 42 43 44 45 65 69 83 87 Clock Output Connections For Cyclone V PLL connectivity to GCLK and RCLK networks refer to the PLL connectivity to GCLK and RCLK networks spreadshee...

Page 69: ...amically you can select up to two PLL counter outputs and up to two clock pins Figure 4 9 GCLK Control Block for Cyclone V Devices CLKp Pins PLL Counter Outputs CLKSELECT 1 0 2 2 2 GCLK Enable Disable This multiplexer supports user controllable dynamic switching Internal Logic Internal Logic Static Clock Select PLL Counter Outputs CLKn Pin When the device is in user mode you can dynamically contro...

Page 70: ... dynamically using the ALTCLKCTRL megafunction choose the inputs using the CLKSELECT 0 1 signal The inputs from the clock pins feed the inclk 0 1 ports of the multiplexer and the PLL outputs feed the inclk 2 3 ports Note Related Information Clock Control Block ALTCLKCTRL Megafunction User Guide Provides more information about ALTCLKCTRL megafunction PCLK Control Block To drive the HSSI horizontal ...

Page 71: ...ng both static and dynamic approaches When a clock network is powered down all the logic fed by the clock network is in off state reducing the overall power consumption of the device The unused GCLK RCLK and PCLK networks are automatically powered down through configuration bit settings in the configuration file sof or pof generated by the Quartus II software The dynamic clock enable or disable fe...

Page 72: ...hronous to the falling edge of the clock output clkena AND Gate Output with R2 Bypassed ena Port Registered as Falling Edge of Input Clock Clock Select Multiplexer Output AND Gate Output with R2 Not Bypassed ena Port Registered as Double Register with Input Clock Use the clkena signals to enable or disable the GCLK and RCLK networks or the FPLL_ _CLKOUT pins Cyclone V devices have an additional me...

Page 73: ...nput clock tracking Yes Source synchronous compensation Yes Direct compensation Yes Normal compensation Yes Zero delay buffer compensation Yes External feedback compensation Yes LVDS compensation 78 125 ps 6 Phase shift resolution Yes Programmable duty cycle Yes Power down mode PLL Physical Counters in Cyclone V Devices The physical counters for the fractional PLLs are arranged in the following se...

Page 74: ...rement of HSSI applications The total number of PLLs in the Cyclone V devices includes the PLLs in the PLL strip However the transceivers can only use the PLLs located in the strip The following figures show the physical locations of the fractional PLLs Every index represents one fractional PLL in the device The physical locations of the fractional PLLs correspond to the coordinates in the Quartus...

Page 75: ...vice Cyclone V GX C4 and C5 Devices and Cyclone V GT D5 Device This figure represents the top view of the silicon die that corresponds to a reverse view of the device package Pins Logical Clocks CLK 4 5 p n FRACTIONALPLL_X0_Y54 4 4 4 4 2 Pins Logical Clocks Logical Clocks Pins 4 Logical Clocks CLK 8 11 p n CLK 0 3 p n CLK 2 3 CLK 10 11 PLL Strip Pins CLK 6 7 p n 4 2 Logical Clocks FRACTIONALPLL_X0...

Page 76: ... 2 Logical Clocks Pins 4 Logical Clocks CLK 8 11 p n CLK 0 3 p n Pins Pins Logical Clocks 2 4 CLK 4 5 p n CLK 6 7 p n FRACTIONALPLL_X0_Y56 FRACTIONALPLL_X0_Y32 FRACTIONALPLL_X0_Y74 FRACTIONALPLL_X0_Y15 FRACTIONALPLL_X89_Y74 FRACTIONALPLL_X89_Y1 2 4 4 4 FRACTIONALPLL_X0_Y1 CLK 2 3 CLK 10 11 PLL Strip Logical Clocks 2 4 Altera Corporation Clock Networks and PLLs in Cyclone V Devices Send Feedback 4 ...

Page 77: ...s 2 Logical Clocks Pins CLK 8 11 p n CLK 0 3 p n CLK 2 3 CLK 10 11 2 4 Logical Clocks 4 Logical Clocks FRACTIONALPLL_X0_Y81 FRACTIONALPLL_X0_Y64 FRACTIONALPLL_X0_Y39 FRACTIONALPLL_X0_Y22 FRACTIONALPLL_X0_Y1 FRACTIONALPLL_X121_Y1 4 4 4 4 PLL Strip 4 4 Pins CLK 6 7 p n FRACTIONALPLL_X0_Y108 FRACTIONALPLL_X121_Y108 2 Logical Clocks 4 Clock Networks and PLLs in Cyclone V Devices Altera Corporation Sen...

Page 78: ...L Locations for Cyclone V SE A5 and A6 Devices Cyclone V SX C5 and C6 Devices and Cyclone V ST D5 and D6 Devices This figure represents the top view of the silicon die that corresponds to a reverse view of the device package 2 2 4 Pins Logical Clocks 2 Logical Clocks Pins 2 Logical Clocks CLK 6 7 p n CLK 0 3 p n Pins CLK 4 5 p n FRACTIONALPLL_X0_Y56 FRACTIONALPLL_X0_Y32 FRACTIONALPLL_X0_Y74 FRACTI...

Page 79: ... N CP LF VCO 2 GCLK RCLK 8 4 FBIN DIFFIOCLK Network GCLK RCLK Network Direct Compensation Mode ZDB External Feedback Modes LVDS Compensation Mode Source Synchronous Normal Modes C0 C1 C2 C3 C8 M PLL Output Multiplexer Casade Output to Adjacent PLL GCLKs RCLKs External Clock Outputs TX Serial Clock TX Load Enable FBOUT External Memory Interface DLL 8 PMA Clocks Delta Sigma Modulator Dedicated refcl...

Page 80: ...e range of C counters PLL External Clock I O Pins All Cyclone V external clock outputs for corner fractional PLLs that are not from the PLL strips are dual purpose clock I O pins Two external clock output pins associated with each corner fractional PLL are organized as one of the following combinations Two single ended clock outputs One differential clock output Two single ended clock outputs and ...

Page 81: ... places a NOT gate in the design into the IOE The clock output pin pairs support the following I O standards Same I O standard for the pin pairs LVDS Differential high speed transceiver logic HSTL Differential SSTL Cyclone V PLLs can drive out to any regular I O pin through the GCLK or RCLK network You can also use the external clock output pins as user I O pins if you do not require external PLL ...

Page 82: ...gaWizard Plug In Manager The lock detection circuit provides a signal to the core logic The signal indicates when the feedback clock has locked onto the reference clock both in phase and frequency Clock Feedback Modes This section describes the following clock feedback modes Source synchronous LVDS compensation Direct Normal compensation ZDB EFB Each mode allows clock multiplication and division p...

Page 83: ... pin to the IOE register input Clock input pin to the PLL phase frequency detector PFD input The Cyclone V PLL can compensate multiple pad to input register paths such as a data bus when it is set to use source synchronous compensation mode LVDS Compensation Mode The purpose of LVDS compensation mode is to maintain the same data and clock timing relationship seen at the pins of the internal serial...

Page 84: ...e PLL Clocks in Direct Mode PLL Reference Clock at the Input Pin PLL Clock at the Register Clock Port External PLL Clock Outputs Phase Aligned The PLL clock outputs lag the PLL input clocks depending on routing delays Normal Compensation Mode An internal clock in normal compensation mode is phase aligned to the input clock pin The external clock output pin has a phase delay relative to the clock i...

Page 85: ... output pins You cannot use differential I O standards on the PLL clock input or output pins To ensure phase alignment between the clk pin and the external clock output CLKOUT pin in ZDB mode instantiate a bidirectional I O pin in the design The bidirectional I O pin serves as the feedback path connecting the fbout and fbin ports of the PLL The bidirectional I O pin must always be assigned a singl...

Page 86: ...Reference Clock at the Input Pin The internal PLL clock output can lead or lag the external PLL clock outputs Related Information PLL External Clock I O Pins on page 4 23 Provides more information about PLL clock outputs External Feedback Mode In EFB mode the output of the M counter fbout feeds back to the PLL fbin input using a trace on the board and becomes part of the feedback loop Altera Corpo...

Page 87: ...L_ _FBn N PFD VCO 0 CP LF Multiplexer External board connection for one single ended clock output and one single ended feedback input for single ended EFB support For single ended EFB mode FPLL_ _CLKOUT1 is the fbout output pin while the FPLL_ _FB is the fbin input pin External board connection for one differential clock output and one differential feedback input for differential EFB support For d...

Page 88: ... VCO to 660 MHz the least common multiple of 33 and 66 MHz within the VCO range Then the post scale counters C scale down the VCO frequency for each output port Pre Scale Counter N and Multiply Counter M Each PLL has one pre scale counter N and one multiply counter M with a range of 1 to 512 for both M and N The N counter does not use duty cycle control because the only purpose of this counter is ...

Page 89: ... counter driving the fbin pin to 50 Combining the programmable duty cycle with programmable phase shift allows the generation of precise non overlapping clocks Clock Switchover The clock switchover feature allows the PLL to switch between two reference input clocks Use this feature for clock redundancy or for a dual clock domain application where a system turns on the redundant clock if the previo...

Page 90: ...ce clock to the PLL When the frequency difference between the two clock inputs is more than 20 the activeclock signal is the only valid status signal Glitches in the input clock may cause the frequency difference between the input clocks to be more than 20 Note Use the switchover circuitry to automatically switch between inclk0 and inclk1 when the current reference clock to the PLL stops toggling ...

Page 91: ... this figure switchover is enabled on the falling edge of inclk1 Automatic Switchover with Manual Override In automatic switchover with manual override mode you can use the clkswitch signal for user or system controlled switch conditions You can use this mode for same frequency switchover or to switch between inputs of different frequencies For example if inclk0 is 66 MHz and inclk1 is 200 MHz you...

Page 92: ...switch signal goes high again the process repeats The clkswitch signal and automatic switch work only if the clock being switched to is available If the clock is not available the state machine waits until the clock is available Related Information Altera Phase Locked Loop ALTERA_PLL Megafunction User Guide Provides more information about PLL software support in the Quartus II software Manual Cloc...

Page 93: ...een the input and output clocks Both inclk0 and inclk1 must be running when the clkswitch signal goes high to initiate the manual clock switchover event Failing to meet this requirement causes the clock switchover to not function properly Applications that require a clock switchover feature and a small frequency drift must use a low bandwidth PLL When referencing input clock changes the low bandwi...

Page 94: ...Shift For more information about PLL reconfiguration and dynamic phase shifting refer to AN661 Related Information AN661 Implementing Fractional PLL Reconfiguration with ALTERA_PLL and ALTERA_PLL_RECONFIG Megafunctions Altera Corporation Clock Networks and PLLs in Cyclone V Devices Send Feedback 4 37 PLL Reconfiguration and Dynamic Phase Shift CV 52004 2014 01 10 ...

Page 95: ...X C3 device Cyclone V E A7 device Cyclone V GX C7 device and Cyclone V GT D7 device Added the following PLL locations diagrams Cyclone V SE A2 and A4 devices and Cyclone V SX C2 and C4 devices Cyclone V SE A5 and A6 devices Cyclone V SX C5 and C6 devices and Cyclone V ST D5 and D6 devices Added information on PLL migration guidelines Updated VCO post scale counter K to VCO post divider Added infor...

Page 96: ... view of the silicon die Removed DPA support Updated clock resources table Updated diagrams for GCLK RCLK and PCLK networks Updated diagram for clock sources per quadrant Updated dual regional clock region for Cyclone V SoC devices support Restructured and updated tables for clock input pin connectivity to the GCLK and RCLK networks Added tables for clock input pin connectivity to the GCLK and RCL...

Page 97: ...s Clock Network Sources Clock Output Connections Clock Enable Signals PLL Control Signals Clock Multiplication and Division Programmable Duty Cycle Clock Switchover and PLL Reconfiguration and Dynamic Phase Shift sections 2 0 June 2012 Updated Table 4 2 1 1 February 2012 Initial release 1 0 October 2011 Clock Networks and PLLs in Cyclone V Devices Altera Corporation Send Feedback CV 52004 Document...

Page 98: ...e Cyclone V Device Handbook chapters I O Resources Per Package for Cyclone V Devices The following package plan tables for the different Cyclone V variants list the maximum I O resources available for each package ISO 9001 2008 Registered 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporat...

Page 99: ...an for Cyclone V GT Devices F1152 F896 F672 F484 U484 M484 M383 M301 Member Code XCVR GPIO XCVR GPIO XCVR GPIO XCVR GPIO XCVR GPIO XCVR GPIO XCVR GPIO XCVR GPIO 6 336 6 240 6 224 6 175 4 129 D5 9 480 9 336 6 240 6 240 3 240 D7 12 560 12 480 9 336 6 224 5 240 D9 Table 5 4 Package Plan for Cyclone V SE Devices The HPS I O counts are the number of I Os in the HPS and does not correlate with the numbe...

Page 100: ... 145 C6 Table 5 6 Package Plan for Cyclone V ST Devices The HPS I O counts are the number of I Os in the HPS and does not correlate with the number of HPS specific I O pins in the FPGA Each HPS specific pin in the FPGA may be mapped to several HPS I Os F896 Member Code XCVR HPS I O FPGA GPIO 9 181 288 D5 9 181 288 D6 For more information about each device variant refer to the device overview Relat...

Page 101: ...e V GT D5 D7 D9 Cyclone V SE A2 A4 A5 A6 Cyclone V SX C2 C4 C5 C6 Cyclone V ST D5 D6 You can achieve the vertical migration shaded in red if you use only up to 175 GPIOs This migration path is not shown in the Quartus II software Pin Migration View To verify the pin migration compatibility use the Pin Migration View window in the Quartus II software Pin Planner Note Related Information Verifying P...

Page 102: ... in at least one migration device that have a different feature than the corresponding pin in the migration result turn on Show migration differences 7 Click Pin Finder to open the Pin Finder dialog box and find and highlight pins with specific functionality If you want to view only the pins found and highlighted by the most recent query in the Pin Finder dialog box turn on Show only highlighted p...

Page 103: ...Class I JESD8 9B Differential SSTL 2 Class II JESD8 15 Differential SSTL 18 Class I JESD8 15 Differential SSTL 18 Class II Differential SSTL 15 Class I Differential SSTL 15 Class II JESD8 6 Differential 1 8 V HSTL Class I JESD8 6 Differential 1 8 V HSTL Class II JESD8 6 Differential 1 5 V HSTL Class I JESD8 6 Differential 1 5 V HSTL Class II JESD8 16A Differential 1 2 V HSTL Class I JESD8 16A Diff...

Page 104: ...TL 3 0 V LVCMOS Yes JESD8 5 2 5 V LVCMOS Yes Yes JESD8 7 1 8 V LVCMOS Yes JESD8 11 1 5 V LVCMOS Yes JESD8 15 SSTL 18 Class I Yes JESD8 15 SSTL 18 Class II Yes SSTL 15 Class I Yes SSTL 15 Class II Yes JESD8 6 1 5 V HSTL Class I Yes JESD8 6 1 5 V HSTL Class II 9 The Cyclone V devices support true RSDS output standard with data rates of up to 230 Mbps using true LVDS output buffer types on all I O ba...

Page 105: ... 1 5 V LVCMOS 2 5 1 2 1 2 1 2 V LVCMOS 1 25 1 25 2 5 2 5 VCCPD SSTL 2 Class I 1 25 1 25 2 5 2 5 VCCPD SSTL 2 Class II 0 9 0 9 2 5 1 8 VCCPD SSTL 18 Class I 0 9 0 9 2 5 1 8 VCCPD SSTL 18 Class II 0 75 0 75 2 5 1 5 VCCPD SSTL 15 Class I 0 75 0 75 2 5 1 5 VCCPD SSTL 15 Class II 0 9 0 9 2 5 1 8 VCCPD 1 8 V HSTL Class I 0 9 0 9 2 5 1 8 VCCPD 1 8 V HSTL Class II 0 75 0 75 2 5 1 5 VCCPD 1 5 V HSTL Class ...

Page 106: ...HSTL Class II 0 75 2 5 1 5 VCCPD Differential 1 5 V HSTL Class I 0 75 2 5 1 5 VCCPD Differential 1 5 V HSTL Class II 0 6 2 5 1 2 VCCPD Differential 1 2 V HSTL Class I 0 6 2 5 1 2 VCCPD Differential 1 2 V HSTL Class II 2 5 2 5 VCCPD LVDS 2 5 2 5 VCCPD RSDS 2 5 2 5 VCCPD Mini LVDS 2 5 VCCPD LVPECL Differential clock input only 2 5 VCCPD SLVS Input only 2 5 VCCPD Sub LVDS input only 2 5 VCCPD HiSpi i...

Page 107: ...ws Cyclone V devices in all packages to interface with systems of different supply voltages Table 5 10 MultiVolt I O Support in Cyclone V Devices Output Signal V Input Signal V VCCPD V VCCIO V 1 2 1 2 2 5 1 2 1 25 1 25 2 5 1 25 1 35 1 35 2 5 1 35 1 5 1 5 1 8 2 5 1 5 1 8 1 5 1 8 2 5 1 8 2 5 2 5 3 0 3 3 2 5 2 5 3 0 2 5 3 0 3 3 3 0 3 0 3 3 2 5 3 0 3 3 3 3 3 3 The pin current may be slightly higher th...

Page 108: ...se an I O bank can only have one VCCIO value it can only drive out the value for non voltage referenced signals For example an I O bank with a 2 5 V VCCIO setting can support 2 5 V standard inputs and outputs and 3 0 V LVCMOS inputs only Related Information I O Standards Voltage Levels in Cyclone V Devices on page 5 8 Voltage Referenced I O Standards To accommodate voltage referenced I O standards...

Page 109: ...egions For example the top left corner fractional PLL cannot cross over to drive the LVDS receiver and driver channels on the top right I O bank The Quartus II compiler automatically checks the design and issues an error message if the guidelines are not followed Related Information High Speed Differential I O Locations on page 5 52 PLL locations that are available for each device Guideline Use PL...

Page 110: ...els If you use LVDS channels adhere to the following guidelines LVDS Channel Driving Distance Each PLL can drive all the LVDS channels in the entire quadrant Using Both Corner PLLs You can use both corner PLLs to drive LVDS channels simultaneously You can use a corner PLL to drive all the transmitter channels and the other corner PLL to drive all the receiver channels in the same I O bank Both cor...

Page 111: ...CLK Corner PLL Corner PLL Reference CLK Reference CLK Corner PLL Diff I O Diff I O Diff I O Diff I O Diff I O Diff I O Diff I O Diff I O Diff I O Channels Driven by Corner PLL No Separation Buffer Needed Figure 5 3 Invalid Placement of Differential I Os Due to Interleaving of Channels Driven by the Corner PLLs Diff I O Diff I O Diff I O Diff I O Reference CLK Corner PLL Corner PLL Reference CLK Di...

Page 112: ...TLVDS transmitter and receiver As an example the table lists the serial clock output load enable output and parallel clock output generated on ports outclk0 outclk1 and outclk2 along with the locked signal of the Altera_PLL instance You can choose any of the PLL output clock ports to generate the interface clocks To the ALTLVDS Receiver To the ALTLVDS Transmitter From the Altera_PLL Megafunction r...

Page 113: ... and then connect the appropriate output to the ALTLVDS_RX and ALTLVDS_TX megafunctions Table 5 13 Example Generating Output Clocks Using an Altera_PLL Megafunction This table lists the parameter values that you can set in the Altera_PLL parameter editor to generate three output clocks using an Altera_PLL megafunction if you are not using DPA and soft CDR mode outclk2 Used as the core clock for th...

Page 114: ...S Receiver ALTLVDS rx_inclock Receiver Core Logic rx_coreclk rx_enable pll_areset rx_out tx_inclock tx_enable tx_in Altera_PLL inclk0 pll_areset outclk0 outclk2 outclk1 locked FPGA Fabric When generating the Altera_PLL megafunction the Left Right PLL option is configured to set up the PLL in LVDS mode Instantiation of pll_areset is optional Guideline Use the Same VCCPD for All I O Banks in a Group...

Page 115: ...2 5 V VCCPD3B is connected to 3 0 V VCCIO pins for banks 3B and 4A must be connected to 3 0 V Guideline VREF Pin Restrictions For the Cyclone V devices consider the following VREF pins guidelines You cannot assign shared VREF pins as LVDS or external memory interface pins SSTL HSTL and HSUL I O standards do not support shared VREF pins For example if a particular B1p or B1n pin is a shared VREF pi...

Page 116: ...e at the I O pins Related Information Cyclone V Device Datasheet Guideline Adhere to the LVDS I O Restrictions and Differential Pad Placement Rules For Cyclone V LVDS applications adhere to these guidelines to avoid adverse impact on LVDS performance I O restrictions guideline to avoid excessive jitter on the LVDS transmitter output pins Differential pad placement rule for each device to avoid cro...

Page 117: ...GX and GT Devices Bank 7A Bank 6A Transceiver Block Bank 8A Bank 5B Bank 5A Bank 4A Bank 3B Bank 3A Figure 5 8 I 0 Banks for Cyclone V SE Devices Bank 8A HPS Column I O HPS Row I O Bank 5B Bank 5A Bank 4A Bank 3B Bank 3A HPS Core I O Features in Cyclone V Devices Altera Corporation Send Feedback CV 52005 I O Banks Locations in Cyclone V Devices 5 20 2014 01 10 ...

Page 118: ...es on page 5 25 Modular I O Banks for Cyclone V SX Devices on page 5 26 Modular I O Banks for Cyclone V ST Devices on page 5 27 I O Banks Groups in Cyclone V Devices The I O pins in Cyclone V devices are arranged in groups called modular I O banks Modular I O banks have independent power supplies that allow each bank to support different I O standards Each modular I O bank can support multiple I O...

Page 119: ... A9 A7 A5 Member Code F896 F672 F484 U484 F896 F672 F484 U484 M484 F484 U484 M383 Package 32 16 16 16 32 16 16 16 16 16 16 16 3A I O Bank 48 32 32 32 48 32 32 32 32 32 32 21 3B 80 80 48 48 80 80 48 48 48 48 48 38 4A 32 16 16 16 32 16 16 16 16 16 16 16 5A 48 32 16 48 48 64 16 48 16 16 32 14 5B 80 48 80 16 32 6A 80 80 64 48 80 80 80 48 48 80 48 39 7A 80 32 32 32 80 32 32 32 32 32 32 31 8A 480 336 22...

Page 120: ...ble 5 17 Modular I O Banks for Cyclone V GX C7 and C9 Devices C9 C7 Member Code F1152 F896 F672 F484 U484 F896 F672 F484 U484 M484 Package 48 32 16 16 16 32 16 16 16 16 3A I O Bank 48 48 32 32 32 48 32 32 32 32 3B 96 80 80 48 48 80 80 48 48 48 4A 48 32 16 16 16 32 16 16 16 16 5A 48 48 32 16 48 48 64 16 48 16 5B 80 80 48 80 16 32 6A 96 80 80 64 48 80 80 80 48 48 7A 96 80 32 32 32 80 32 32 32 32 8A ...

Page 121: ...40 240 240 336 240 224 175 129 Total Table 5 19 Modular I O Banks for Cyclone V GT D9 Devices D9 Member Code F1152 F896 F672 F484 U484 Package 48 32 16 16 16 3A I O Bank 48 48 32 32 32 3B 96 80 80 48 48 4A 48 32 16 16 16 5A 48 48 32 16 48 5B 80 80 48 6A 96 80 80 64 48 7A 96 80 32 32 32 8A 560 480 336 224 240 Total Related Information I O Banks Locations in Cyclone V Devices on page 5 19 Guideline ...

Page 122: ...16 5A 16 16 5B 56 56 52 56 56 52 56 52 56 52 6A HPS RowI O Bank 44 44 23 44 44 23 44 23 44 23 6B 19 19 19 19 19 19 19 19 19 19 7A HPS Column I O Bank 22 22 21 22 22 21 22 21 22 21 7B 12 12 8 12 12 8 12 8 12 8 7C 14 14 14 14 14 14 14 14 14 14 7D 80 13 6 80 13 6 13 6 13 6 8A FPGA I O Bank 455 312 203 455 312 203 312 203 312 203 Total Related Information I O Banks Locations in Cyclone V Devices on pa...

Page 123: ... 16 32 16 16 16 5A 16 16 5B 56 56 56 56 56 56 6A HPS Row I O Bank 44 44 44 44 44 44 6B 19 19 19 19 19 19 7A HPS Column I O Bank 22 22 22 22 22 22 7B 12 12 12 12 12 12 7C 14 14 14 14 14 14 7D 80 13 80 13 13 13 8A FPGA I O Bank 455 312 455 312 312 312 Total Related Information I O Banks Locations in Cyclone V Devices on page 5 19 Guideline Use the Same VCCPD for All I O Banks in a Group on page 5 17...

Page 124: ...tructure in Cyclone V Devices The I O elements IOEs in Cyclone V devices contain a bidirectional I O buffer and I O registers to support a complete embedded bidirectional single data rate SDR or double data rate DDR transfer The IOEs are located in I O blocks around the periphery of the Cyclone V device The Cyclone V SE SX and ST devices also have I O elements for the HPS I O Buffer and Registers ...

Page 125: ...hip termination OCT control is available for each DQ DQS group 4 Open Drain On Chip Termination Bus Hold Circuit Programmable Current Strength and Slew Rate Control VCCIO VCCIO Programmable Pull Up Resistor Half Data Rate Block Write Data from Core 4 PRN D Q PRN D Q PRN D Q PRN D Q PRN D Q OE Register OE Register Output Register Output Register clkout To Core To Core D5 Delay Input Register PRN D ...

Page 126: ...l HSTL and SSTL I O standards 0 disabled and 1 enabled Pre Emphasis 00 low 01 medium 10 high Differential Output Voltage Yes Recommended to turn on for 3 3 V I O standards On Off On Chip Clamp Diode The on chip clamp diode is available on all general purpose I O GPIO pins in all Cyclone V device variants Note Related Information Cyclone V Device Datasheet Programmable Current Strength on page 5 30...

Page 127: ... 12 8 4 3 0 V LVCMOS Yes 16 12 8 4 2 5 V LVCMOS Yes 12 10 8 6 4 2 1 8 V LVCMOS Yes 12 10 8 6 4 2 1 5 V LVCMOS 8 6 4 2 1 2 V LVCMOS 12 10 8 SSTL 2 Class I 16 SSTL 2 Class II Yes 12 10 8 6 4 SSTL 18 Class I Yes 16 SSTL 18 Class II Yes 12 10 8 6 4 SSTL 15 Class I Yes 16 SSTL 15 Class II 12 10 8 6 4 1 8 V HSTL Class I 16 1 8 V HSTL Class II Yes 12 10 8 6 4 1 5 V HSTL Class I Yes 16 1 5 V HSTL Class II...

Page 128: ...r or a delay from output register to output pin values to ensure that the signals within a bus have the same delay going into or out of the device For more information about the programmable IOE delay specifications refer to the device datasheet Related Information Cyclone V Device Datasheet Programmable IOE Features in Cyclone V Devices on page 5 29 Programmable Output Buffer Delay The delay chai...

Page 129: ...grammable Pre Emphasis This figure shows the LVDS output with pre emphasis OUT OUT VOD VP VP Voltage boost from pre emphasis Differential output voltage peak peak Table 5 26 Quartus II Software Assignment Editor Programmable Pre Emphasis This table lists the assignment name for programmable pre emphasis and its possible values in the Quartus II software Assignment Editor Assignment Default setting...

Page 130: ... IOE Features in Cyclone V Devices on page 5 29 I O Pins Features for Cyclone V Devices Open Drain Output on page 5 33 Bus Hold Circuitry on page 5 33 Pull up Resistor on page 5 34 Open Drain Output The optional open drain output for each I O pin is equivalent to an open collector output If it is configured as an open drain the logic value of the output is either high Z or logic low Use an externa...

Page 131: ... level The Cyclone V device supports programmable weak pull up resistors only on user I O pins but not on dedicated configuration pins dedicated clock pins or JTAG pins If you enable this option you cannot use the bus hold feature On Chip I O Termination in Cyclone V Devices Dynamic RS and RT OCT provides I O impedance matching and termination capabilities OCT maintains signal quality saves board ...

Page 132: ...0 1 5 V LVCMOS 25 50 1 2 V LVCMOS 50 SSTL 2 Class I 25 SSTL 2 Class II 50 SSTL 18 Class I 25 SSTL 18 Class II 50 SSTL 15 Class I 25 SSTL 15 Class II 50 1 8 V HSTL Class I 25 1 8 V HSTL Class II 50 1 5 V HSTL Class I 25 1 5 V HSTL Class II 50 1 2 V HSTL Class I 25 1 2 V HSTL Class II 50 Differential SSTL 2 Class I 25 Differential SSTL 2 Class II 50 Differential SSTL 18 Class I 25 Differential SSTL ...

Page 133: ...ransmission line As a result you can significantly reduce signal reflections on PCB traces If you select matching impedance current strength is no longer selectable Figure 5 13 RS OCT Without Calibration This figure shows the RS as the intrinsic impedance of the output transistors VCCIO RS RS GND Z0 50 Ω Driver Series Termination Receiving Device Related Information On Chip I O Termination in Cycl...

Page 134: ... V HSTL Class I 100 25 1 5 V HSTL Class II 100 50 1 2 V HSTL Class I 100 25 1 2 V HSTL Class II 100 50 Differential SSTL 2 Class I 100 25 Differential SSTL 2 Class II 100 50 Differential SSTL 18 Class I 100 25 Differential SSTL 18 Class II 100 50 Differential SSTL 15 Class I 100 25 Differential SSTL 15 Class II 100 50 Differential 1 8 V HSTL Class I 100 25 Differential 1 8 V HSTL Class II 100 50 D...

Page 135: ...haracteristics of the drivers Figure 5 14 RS OCT with Calibration This figure shows the RS as the intrinsic impedance of the output transistors VCCIO RS RS GND Z0 50 Ω Driver Series Termination Receiving Device Related Information On Chip I O Termination in Cyclone V Devices on page 5 34 RT OCT with Calibration in Cyclone V Devices The Cyclone V devices support RT OCT with calibration in all banks...

Page 136: ...l SSTL 2 Class II 100 50 Differential SSTL 18 Class I 100 50 Differential SSTL 18 Class II 100 50 Differential SSTL 15 Class I 100 50 Differential SSTL 15 Class II 100 50 Differential 1 8 V HSTL Class I 100 50 Differential 1 8 V HSTL Class II 100 50 Differential 1 5 V HSTL Class I 100 50 Differential 1 5 V HSTL Class II 100 50 Differential 1 2 V HSTL Class I 100 50 Differential 1 2 V HSTL Class II...

Page 137: ...ctional path by optimizing the signal integrity depending on the direction of the data Dynamic OCT also helps save power because device termination is internal termination switches on only during input operation and thus draw less static power If you use the SSTL 15 SSTL 135 and SSTL 125 I O standards with the DDR3 memory interface Altera recommends that you use dynamic OCT with these I O standard...

Page 138: ...lone V Devices The Cyclone V devices support RD OCT in all I O banks You can only use RD OCT if you set the VCCPD to 2 5 V Figure 5 17 Differential Input OCT The Cyclone V devices support OCT for differential LVDS and SLVS input buffers with a nominal resistance value of 100 Ω as shown in this figure 100 Ω Receiver Transmitter Z0 50 Ω Z0 50 Ω Related Information On Chip I O Termination in Cyclone ...

Page 139: ...y voltage with the I O bank where the pin is located Cyclone V devices support calibrated RS and calibrated RT OCT on all I O pins except for dedicated configuration pins Calibration Block Locations in Cyclone V Devices Figure 5 18 OCT Calibration Block and RZQ Pin Location This figure shows the location of I O banks with OCT calibration blocks and RZQ pins in the Cyclone V device Calibration bloc...

Page 140: ...Block Sharing Example Figure 5 19 Example of Calibrating Multiple I O Banks with One Shared OCT Calibration Block As an example this figure shows a group of I O banks that has the same VCCIO voltage The figure does not show transceiver calibration blocks CB3 Bank 8A Transceiver Block Bank 7A Bank 6A Bank 5B Bank 5A Bank 4A Bank 3B Bank 3A I O bank with different VCCIO I O bank with the same VCCIO ...

Page 141: ... Ended SSTL I O Standard Termination SSTL 2 Class I SSTL 2 Class II SSTL 18 Class I SSTL 18 Class II SSTL 15 Class I SSTL 15 Class II Single Ended HSTL I O Standard Termination 1 8 V HSTL Class I 1 8 V HSTL Class II 1 5 V HSTL Class I 1 5 V HSTL Class II 1 2 V HSTL Class I 1 2 V HSTL Class II Differential SSTL I O Standard Termination Differential SSTL 2 Class I Differential SSTL 2 Class II Differ...

Page 142: ...ge referenced I O standards require an input VREF and a termination voltage VTT The reference voltage of the receiving device tracks the termination voltage of the transmitting device The supported I O standards such as SSTL 125 SSTL 135 and SSTL 15 typically do not require external board termination Altera recommends that you use dynamic OCT with these I O standards to save board space and cost D...

Page 143: ...Ω 100 Ω GND Transmitter Receiver 50 Ω Series OCT 50 Ω Transmitter Receiver 50 Ω 50 Ω 25 Ω FPGA Parallel OCT 100 Ω 100 Ω GND 50 Ω Transmitter Receiver 50 Ω Series OCT 25 Ω 50 Ω 50 Ω Transmitter Receiver 50 Ω VREF VREF VREF VREF VREF VREF 50 Ω VTT VTT VTT VTT VTT VTT VTT Transmitter Receiver 50 Ω 50 Ω 50 Ω 25 Ω VREF VREF VREF VREF SSTL Class I Termination OCT Transmit OCT Receive SSTL Class II Exter...

Page 144: ...ation Dynamic OCT in Cyclone V Devices on page 5 40 Differential I O Termination The I O pins are organized in pairs to support differential I O standards Each I O pin pair can support differential input and output buffers The supported I O standards such as Differential SSTL 15 Differential SSTL 125 and Differential SSTL 135 typically do not require external board termination Altera recommends th...

Page 145: ...igure shows the details of Differential HSTL I O standard termination on Cyclone V devices Transmitter Receiver Transmitter Receiver Series OCT 25 Ω Transmitter Receiver Series OCT 50 Ω Transmitter Receiver 50 Ω 50 Ω VTT 50 Ω 50 Ω VTT 50 Ω 50 Ω VTT 50 Ω 50 Ω VTT 50 Ω VTT 50 Ω VTT 50 Ω VTT 100 Ω 100 Ω GND VCCIO 100 Ω 100 Ω GND VCCIO 50 Ω VTT 100 Ω 100 Ω GND VCCIO 100 Ω 100 Ω GND VCCIO Differential ...

Page 146: ...ination External On Board Termination OCT Receiver True LVDS or SLVS Output Receiver OCT Emulated LVDS RSDS and Mini LVDS Termination The I O banks also support emulated LVDS RSDS and mini LVDS I O standards Emulated LVDS RSDS and mini LVDS output buffers use two single ended output buffers with an external single resistor or three resistor network and can be tri stated Altera Corporation I O Feat...

Page 147: ... Inputs Transmitter 50 Ω 50 Ω 100 Ω External Resistor RP Receiver OCT Single Ended Outputs Differential Inputs Transmitter 50 Ω 50 Ω 100 Ω 1 inch External Resistor RS RS RP Receiver OCT RSDS_E_3R External On Board Termination RSDS_E_3R OCT Receive Single Ended Output with Single Resistor LVDS_E_1R OCT Receive Single Ended Output with Three Resistor Network LVDS_E_3R To meet the RSDS or mini LVDS s...

Page 148: ...e RSDS Specification on the National Semiconductor web site LVPECL Termination The Cyclone V devices support the LVPECL I O standard on input clock pins only LVPECL input operation is supported using LVDS input buffers LVPECL output operation is not supported Use AC coupling if the LVPECL common mode voltage of the output buffer does not match the LVPECL input common mode voltage Altera recommends...

Page 149: ...ferential buffer Up to 10 bit deserializer Up to 10 bit serializer SERDES Generates different phases of a clock for data synchronizer Clocks the load and shift registers Fractional PLL Statically assignable Programmable VOD Boosts output current Programmablepre emphasis Inserts bit latencies into serial data Data realignment block Bit slip Manual Skew adjustment 100 Ω in LVDS and SLVS standards On...

Page 150: ...mbedded Memory Clock Networks Fractional PLL Transceiver Block General Purpose I O and High Speed LVDS I O with SERDES Figure 5 31 High Speed Differential I O Locations in Cyclone V GX C4 C5 C7 and C9 Devices and Cyclone V GT D5 D7 and D9 Devices Fractional PLL Transceiver Block FPGA Fabric Logic Elements DSP Embedded Memory Clock Networks General Purpose I O and High Speed LVDS I O with SERDES Al...

Page 151: ...PS I O HPS Core General Purpose I O and High Speed LVDS I O with SERDES FPGA Fabric Logic Elements DSP Embedded Memory Clock Networks Related Information PLLs and Clocking on page 5 12 I O design guidelines related to PLLs and clocking Guideline Use PLLs in Integer PLL Mode for LVDS on page 5 12 LVDS SERDES Circuitry The following figure shows a transmitter and receiver block diagram for the LVDS ...

Page 152: ... by the Cyclone V devices refer to the device overview Note Related Information Cyclone V Device Overview LVDSSERDESTransmitter Receiver ALTLVDS_TXandALTLVDS_RX MegafunctionUserGuide Provides a list of the LVDS transmitter and receiver ports and settings using ALTLVDS Guideline Use PLLs in Integer PLL Mode for LVDS on page 5 12 True LVDS Buffers in Cyclone V Devices The Cyclone V device family sup...

Page 153: ...12 Top 324 pin Ultra FineLine BGA 8 8 Left 8 8 Right 16 16 Bottom 19 15 Top 383 pin Micro FineLine BGA 12 12 Left 8 7 Right 20 16 Bottom 20 20 Top 484 pin Ultra FineLine BGA 4 4 Left 8 8 Right 24 24 Bottom 20 20 Top 484 pin FineLine BGA 4 4 Left 8 8 Right 24 24 Bottom 19 15 Top 383 pin Micro FineLine BGA A5 8 7 Right 21 16 Bottom 20 20 Top 484 pin Ultra FineLine BGA 12 12 Right 24 24 Bottom 28 28 ...

Page 154: ... 24 24 Right 32 32 Bottom 40 40 Top 896 pin FineLine BGA 40 40 Right 40 40 Bottom 20 20 Top 484 pin Ultra FineLine BGA A9 16 16 Right 24 24 Bottom 24 24 Top 484 pin FineLine BGA 8 8 Right 24 24 Bottom 28 28 Top 672 pin FineLine BGA 24 24 Right 32 32 Bottom 40 40 Top 896 pin FineLine BGA 40 40 Right 40 40 Bottom Altera Corporation I O Features in Cyclone V Devices Send Feedback 5 57 True LVDS Buffe...

Page 155: ...8 8 Right 24 24 Bottom 15 6 Top 301 pin Micro FineLine BGA C4 8 7 Right 20 8 Bottom 19 15 Top 383 pin Micro FineLine BGA 8 7 Right 21 16 Bottom 20 20 Top 484 pin Ultra FineLine BGA 12 12 Right 24 24 Bottom 28 28 Top 484 pin FineLine BGA 8 8 Right 24 24 Bottom 28 28 Top 672 pin FineLine BGA 24 24 Right 32 32 Bottom I O Features in Cyclone V Devices Altera Corporation Send Feedback CV 52005 True LVD...

Page 156: ... Top 672 pin FineLine BGA 24 24 Right 32 32 Bottom 20 20 Top 484 pin Micro FineLine BGA C7 16 16 Right 24 24 Bottom 20 20 Top 484 pin Ultra FineLine BGA 16 16 Right 24 24 Bottom 28 28 Top 484 pin FineLine BGA 8 8 Right 24 24 Bottom 28 28 Top 672 pin FineLine BGA 24 24 Right 32 32 Bottom 40 40 Top 896 pin FineLine BGA 40 40 Right 40 40 Bottom Altera Corporation I O Features in Cyclone V Devices Sen...

Page 157: ...tom Table 5 37 LVDS Channels Supported in Cyclone V GT Devices RX TX Side Package Member Code 15 6 Top 301 pin Micro FineLine BGA D5 8 7 Right 20 8 Bottom 19 15 Top 383 pin Micro FineLine BGA 8 7 Right 21 16 Bottom 20 20 Top 484 pin Ultra FineLine BGA 12 12 Right 24 24 Bottom 28 28 Top 484 pin FineLine BGA 8 8 Right 24 24 Bottom 28 28 Top 672 pin FineLine BGA 24 24 Right 32 32 Bottom I O Features ...

Page 158: ... 40 Top 896 pin FineLine BGA 40 40 Right 40 40 Bottom 20 20 Top 484 pin Ultra FineLine BGA D9 16 16 Right 24 24 Bottom 24 24 Top 484 pin FineLine BGA 8 8 Right 24 24 Bottom 28 28 Top 672 pin FineLine BGA 24 24 Right 32 32 Bottom 40 40 Top 896 pin FineLine BGA 40 40 Right 40 40 Bottom 48 48 Top 1152 pin FineLine BGA 44 44 Right 48 48 Bottom Altera Corporation I O Features in Cyclone V Devices Send ...

Page 159: ...ht 40 40 Bottom Table 5 39 LVDS Channels Supported in Cyclone V SX Devices RX TX Side Package Member Code 2 1 Top 672 pin Ultra FineLine BGA C2 and C4 6 5 Right 29 26 Bottom 2 1 Top 672 pin Ultra FineLine BGA C5 and C6 6 5 Right 29 26 Bottom 20 20 Top 896 pin FineLine BGA 12 12 Right 40 40 Bottom Table 5 40 LVDS Channels Supported in Cyclone V ST Devices RX TX Side Package Member Code 20 20 Top 89...

Page 160: ...l buffer a serializer and fractional PLLs that you can share between the transmitter and receiver The serializer takes up to 10 bits wide parallel data from the FPGA fabric clocks it into the load registers and serializes it using shift registers that are clocked by the fractional PLL before sending the data to the differential buffer The MSB of the parallel data is transmitted first To drive the ...

Page 161: ...with a maximum output clock frequency that each speed grade of the device supports You can divide the output clock by a factor of 1 2 4 6 8 or 10 depending on the serialization factor You can set the phase of the clock in relation to the data using internal PLL option of the ALTLVDS megafunction The fractional PLLs provide additional support for other phase shifts in 45 increments The following fi...

Page 162: ... buffer can receive LVDS mini LVDS and RSDS signal levels You can statically set the I O standard of the receiver pins to LVDS SLVS mini LVDS or RSDS in the Quartus II software Assignment Editor To drive the LVDS channels you must use the PLLs in integer PLL mode Note Related Information Guideline Use PLLs in Integer PLL Mode for LVDS on page 5 12 Receiver Blocks in Cyclone V Devices The Cyclone V...

Page 163: ...pulse width is one period of the parallel clock in the logic array The minimum low time between pulses is one period of the parallel clock The signal is an edge triggered signal The valid data is available two parallel clock cycles after the rising edge of RX_CHANNEL_DATA_ALIGN Figure 5 39 Data Realignment Timing This figure shows receiver output RX_OUT after one bit slip pulse with the deserializ...

Page 164: ...iver FPGA Fabric rx_out Bit Slip Deserializer rx_inclock tx_inclock DOUT DOUT DIN Fractional PLL LOAD_EN diffioclk 2 10 3 LVDS_LOAD_EN LVDS_diffioclk rx_outclock diffioclk rx_outclock DIN IOE 10 2 Note Disabled blocks and signals are grayed out The IOE contains two data input registers that can operate in DDR or SDR mode In DDR mode rx_inclock clocks the IOE register In SDR mode data is directly p...

Page 165: ...l medium connecting the transmitter and receiver LVDS channels may introduce skew between the serial data and the source synchronous clock The instantaneous skew between each LVDS channel and the clock also varies with the jitter on the data and clock signals as seen by the receiver LVDS mode allows you to statically select the optimal phase between the source synchronous clock and the received se...

Page 166: ...ynchronous timing analysis techniques The basis of the source synchronous timing analysis is the skew between the data and the clock signals instead of the clock to output setup times High speed differential data transmission requires the use of timing parameters provided by IC vendors and is strongly influenced by board skew cable skew and clock jitter This section defines the source synchronous ...

Page 167: ...X X X X X X X X X X X X X 7 6 5 4 3 2 1 0 X X X X Previous Cycle Next Cycle tx_out tx_outclock rx_inclock rx_outclock Transmitter Channel Operation x8 Mode Receiver Channel Operation x8 Mode Note These waveforms are only functional waveforms and do not convey timing information For other serialization factors use the Quartus II software tools to find the bit position within the word Differential B...

Page 168: ...alyzer provides the TCCS value in the TCCS report report_TCCS in the Quartus II compilation report which shows TCCS values for serial output ports You can also get the TCCS value from the device datasheet Related Information Cyclone V Device Datasheet LVDSSERDESTransmitter Receiver ALTLVDS_TXandALTLVDS_RX MegafunctionUserGuide Provides more information about the LVDS Transmitter Receiver Package S...

Page 169: ...ceiver can sample the data properly or not given the data rate and device A positive RSKM value indicates that the LVDS receiver can sample the data properly whereas a negative RSKM indicates that it cannot sample the data properly The following figure shows the relationship between the RSKM TCCS and the SW of the receiver Figure 5 47 Differential High Speed Timing Diagram and Timing Budget for LV...

Page 170: ...s more information about the RSKM equation and calculation Quartus II TimeQuest Timing Analyzer chapter Quartus II Development Software Handbook Provides more information about sdc commands and the TimeQuest Timing Analyzer Document Revision History Changes Version Date Added 3 3 V VCCIO input for 3 0 V LVTTL 3 0 V LVCMOS and 2 5 V LVCMOS I O standards 2014 01 10 January 2014 Added 3 3 V input sig...

Page 171: ...n after a bit slip 2013 06 21 June 2013 Removed 3 3 V input signal for 2 5 V VCCIO in the table listing the MultiVolt I O support 2013 06 17 June 2013 Added a topic about LVDS I O restrictions and differential pad placement rule Updated the preliminary I O counts per bank for the following packages M301 packages of Cyclone V GX C5 and GT D5 devices U324 package of Cyclone V GX C3 device M383 packa...

Page 172: ...4 devices Added the M383 and M484 packages to the modular I O banks tables for Cyclone V E devices and added the U484 package for the Cyclone V E A9 device Added the U324 M301 M383 and M484 to the modular I O banks tables for the Cyclone V GX devices and added the U484 package for the Cyclone V GX C9 device Added the M301 M383 and M484 to the modular I O banks tables for the Cyclone V GT devices a...

Page 173: ...rganized content and updated template 2012 12 28 December 2012 Added the I O resources per package and I O vertical migration sections for easy reference Added the steps to verify pin migration compatibility using the Quartus II software Updated the I O standards support table with HPS I O information Added topic about the reference clock pin restriction for LVDS application Updated the pin placem...

Page 174: ...ck sections Added Figure 5 3 Figure 5 4 Figure 5 5 Figure 5 6 and Figure 5 27 Updated Table 5 1 Table 5 8 and Table 5 10 Updated Figure 5 22 with emulated LVDS with external single resistor Updated Table 5 1 Table 5 2 Table 5 8 and Table 5 10 1 2 February 2012 Updated I O Banks on page 5 8 Minor text edits Updated Table 5 2 1 1 November2011 Updated Figure 5 3 Figure 5 4 Updated Sharing an OCT Cali...

Page 175: ...ging information Cyclone V Device Handbook Known Issues Lists the planned updates to the Cyclone V Device Handbook chapters ISO 9001 2008 Registered 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other...

Page 176: ...le 6 3 HPS External Memory Interface Performance The hard processor system HPS is available in Cyclone V SoC devices only HPS Hard Controller MHz Voltage V Interface 400 1 5 DDR3 SDRAM 400 1 35 400 1 8 DDR2 SDRAM 333 1 2 LPDDR2 SDRAM Related Information External Memory Interface Spec Estimator For the latest information and to estimate the external memory system performance specification use Alter...

Page 177: ...Sn pins denote the differential data strobe clock pin pairs The DQS and DQSn pins are listed respectively in the Cyclone V pin tables as DQSXY and DQSnXY X indicates the DQ DQS grouping number and Y indicates whether the group is located on the top T bottom B left L or right R side of the device The F484 package of the Cyclone V E A9 GX C9 and GT D9 devices can only support a 24 bit hard memory co...

Page 178: ...uire one DQSn pin and one DM pin This further reduces the total number of data pins available Table 6 4 DQ DQS Bus Mode Pins for Cyclone V Devices Maximum Data Pins per Group Data Mask Optional DQSn Support Mode 11 Yes Yes x8 23 Yes Yes x16 External Memory Interfaces in Cyclone V Devices Altera Corporation Send Feedback CV 52006 DQ DQS Bus Mode Pins for Cyclone V Devices 6 4 2014 01 10 ...

Page 179: ...A2 A4 0 1 Left 0 2 Right 0 3 Bottom 0 3 Top 324 pin Ultra FineLine BGA 0 2 Left 0 2 Right 0 4 Bottom 0 4 Top 383 pin Micro FineLine BGA 0 2 Left 0 1 Right 0 4 Bottom 1 5 Top 484 pin Ultra FineLine BGA 0 1 Left 0 2 Right 1 6 Bottom 1 5 Top 484 pin FineLine BGA 0 1 Left 0 2 Right 1 6 Bottom 0 4 Top 383 pin Micro FineLine BGA A5 0 1 Right 0 4 Bottom 1 5 Top 484 pin Ultra FineLine BGA 0 3 Right 1 6 Bo...

Page 180: ...BGA 3 10 Right 3 10 Bottom 1 5 Top 484 pin Ultra FineLine BGA A9 0 4 Right 1 6 Bottom 1 5 Top 484 pin FineLine BGA 0 2 Right 1 6 Bottom 2 7 Top 672 pin FineLine BGA 0 6 Right 2 8 Bottom 3 10 Top 896 pin FineLine BGA 3 10 Right 3 10 Bottom Related Information Cyclone V Device Pin Out Files Download the relevant pin tables from this web page External Memory Interfaces in Cyclone V Devices Altera Cor...

Page 181: ...ra FineLine BGA C3 0 2 Right 0 4 Bottom 1 5 Top 484 pin Ultra FineLine BGA 0 2 Right 1 6 Bottom 1 5 Top 484 pin FineLine BGA 0 2 Right 1 6 Bottom TBD TBD Top 301 pin Micro FineLine BGA C4 C5 TBD TBD Left TBD TBD Right TBD TBD Bottom 0 4 Top 383 pin Micro FineLine BGA 0 1 Right 0 4 Bottom 1 5 Top 484 pin Ultra FineLine BGA 0 3 Right 1 6 Bottom 2 7 Top 484 pin FineLine BGA 0 2 Right 1 6 Bottom 2 7 T...

Page 182: ... 5 Top 484 pin Ultra FineLine BGA C9 0 4 Right 1 6 Bottom 1 5 Top 484 pin FineLine BGA 0 2 Right 1 6 Bottom 2 7 Top 672 pin FineLine BGA 0 6 Right 2 8 Bottom 3 10 Top 896 pin FineLine BGA 3 10 Right 3 10 Bottom 4 12 Top 1152 pin FineLine BGA 4 11 Right 4 12 Bottom Related Information Cyclone V Device Pin Out Files Download the relevant pin tables from this web page External Memory Interfaces in Cy...

Page 183: ...before the devices are available x16 x8 Side Package Member Code TBD TBD Top 301 pin Micro FineLine BGA D5 TBD TBD Left TBD TBD Right TBD TBD Bottom 0 4 Top 383 pin Micro FineLine BGA 0 1 Right 0 4 Bottom 1 5 Top 484 pin Ultra FineLine BGA 0 3 Right 1 6 Bottom 2 7 Top 484 pin FineLine BGA 0 2 Right 1 6 Bottom 2 7 Top 672 pin FineLine BGA 2 6 Right 2 8 Bottom Altera Corporation External Memory Inte...

Page 184: ... 5 Top 484 pin Ultra FineLine BGA D9 0 4 Right 1 6 Bottom 1 5 Top 484 pin FineLine BGA 0 2 Right 1 6 Bottom 2 7 Top 672 pin FineLine BGA 0 6 Right 2 8 Bottom 3 10 Top 896 pin FineLine BGA 3 10 Right 3 10 Bottom 4 12 Top 1152 pin FineLine BGA 4 11 Right 4 12 Bottom Related Information Cyclone V Device Pin Out Files Download the relevant pin tables from this web page External Memory Interfaces in Cy...

Page 185: ...ine BGA 0 3 Right 3 10 Bottom DQ DQS Groups in Cyclone V SX Table 6 9 Number of DQ DQS Groups Per Side in Cyclone V SX Devices This table lists the DQ DQS groups for the soft memory controller For the hard memory controller you can get the DQ DQS groups from the pin table of the specific device The numbers are preliminary before the devices are available x16 x8 Side Package Member Code 0 1 Right 6...

Page 186: ...s the self calibrating UniPHY IP that is optimized to take advantage of the Cyclone V I O structure and the Quartus II software TimeQuest Timing Analyzer The UniPHY IP helps set up the physical interface PHY best suited for your system This provides the total solution for the highest reliable frequency of operation across process voltage and temperature PVT variations The UniPHY IP instantiates a ...

Page 187: ...s for different memory interface standards The shaded blocks are part of the I O elements Clock Management and Reset DQS Delay Chain DQS Enable Circuit DQS Enable Control Circuit DQS Postamble Circuitry DDR Input Registers DDR Output and Output Enable Registers DDR Output and Output Enable Registers Half Data Rate Output Registers Half Data Rate Output Registers DQS Phase Shift Circuitry The Cyclo...

Page 188: ...Δt Δt Δt DQS Logic Blocks DLL Reference Clock DLL to IOE to IOE to IOE to IOE DLL DQS Pin DQS Pin DQS Pin DQS Pin Δt Δt Δt Δt DQS Logic Blocks to IOE to IOE to IOE to IOE DQS Pin DQS Pin DQS Pin DQS Pin Δt Δt Δt Δt DQS Logic Blocks to IOE to IOE to IOE to IOE DQS Pin DQS Pin DQS Pin DQS Pin External Memory Interfaces in Cyclone V Devices Altera Corporation Send Feedback CV 52006 DQS Phase Shift Ci...

Page 189: ... Logic Blocks DLL Reference Clock DLL to IOE to IOE to IOE to IOE DLL DQS Pin DQS Pin DQS Pin DQS Pin DLL Reference Clock DLL Δt Δt Δt Δt DQS Logic Blocks to IOE to IOE to IOE to IOE DQS Pin DQS Pin DQS Pin DQS Pin Transceiver Blocks Altera Corporation External Memory Interfaces in Cyclone V Devices Send Feedback 6 15 DQS Phase Shift Circuitry CV 52006 2014 01 10 ...

Page 190: ...QS Pin DQS Pin DQS Pin DQS Pin Transceiver Blocks DLL Reference Clock DLL Reference Clock DLL DLL Δt Δt Δt Δt DQS Logic Blocks to IOE to IOE to IOE to IOE DQS Pin DQS Pin DQS Pin DQS Pin Δt Δt Δt Δt DQS Logic Blocks to IOE to IOE to IOE to IOE DQS Pin DQS Pin DQS Pin DQS Pin External Memory Interfaces in Cyclone V Devices Altera Corporation Send Feedback CV 52006 DQS Phase Shift Circuitry 6 16 201...

Page 191: ...ference Clock DLL Reference Clock DLL DLL Δt Δt Δt Δt DQS Logic Blocks to IOE to IOE to IOE to IOE DQS Pin DQS Pin DQS Pin DQS Pin DQS Pin DQS Pin HPS I O Δt Δt Δt Δt DQS Logic Blocks to IOE to IOE Δt Δt to IOE to IOE HPS Block HPS PLL Altera Corporation External Memory Interfaces in Cyclone V Devices Send Feedback 6 17 DQS Phase Shift Circuitry CV 52006 2014 01 10 ...

Page 192: ... DLL uses a frequency reference to dynamically generate control signals for the delay chains in each of the DQS pins allowing the delay to compensate for process voltage and temperature PVT variations The DQS delay settings are gray coded to reduce jitter if the DLL updates the settings There are a maximum of four DLLs located in each corner of the Cyclone V devices You can clock each DLL using di...

Page 193: ...ference Clock Input for Cyclone V Devices Table 6 11 DLL Reference Clock Input from PLLs for Cyclone V E A2 A4 A5 A7 and A9 GX C4 C5 C7 and C9 and GT D5 D7 and D9 Devices Preliminary PLL DLL Bottom Right Bottom Left Top Right Top Left pllout DLL_TL pllout DLL_TR pllout DLL_BL pllout DLL_BR Table 6 12 DLL Reference Clock Input from PLLs for Cyclone V GX C3 Device Preliminary PLL DLL Bottom Right Bo...

Page 194: ...Figure 6 7 Simplified Diagram of the DQS Phase Shift Circuitry This figure shows a simple block diagram of the DLL All features of the DQS phase shift circuitry are accessible from the UniPHY megafunction in the Quartus II software 7 7 7 delayctrlout 6 0 dqsupdate aload clk upndnin upndninclkena DLL This clock can come from a PLL output clock or an input clock pin DQS delay settings can go to the ...

Page 195: ...ated adjacent to the I O bank The following figures show the PHYCLK networks available in the Cyclone V devices Figure 6 8 PHYCLK Networks in Cyclone V E A2 and A4 Devices Left PLL Right PLL Sub Bank Sub Bank I O Bank 7 Sub Bank Sub Bank I O Bank 8 PHYCLK Networks Sub Bank Sub Bank I O Bank 4 Sub Bank Sub Bank I O Bank 3 PHYCLK Networks Sub Bank I O Bank 6 Sub Bank Sub Bank I O Bank 5 PHYCLK Netwo...

Page 196: ...PHYCLK Networks in Cyclone V E A7 A5 and A9 Devices Cyclone V GX C4 C5 C7 and C9 Devices and Cyclone V GT D5 D7 and D9 Devices Left PLL Right PLL Sub Bank Sub Bank I O Bank 7 Sub Bank Sub Bank I O Bank 8 PHYCLK Networks Sub Bank Sub Bank I O Bank 4 Sub Bank Sub Bank I O Bank 3 PHYCLK Networks Sub Bank I O Bank 6 Sub Bank Sub Bank I O Bank 5 PHYCLK Networks Transceiver Banks FPGA Device Sub Bank Le...

Page 197: ...Networks Figure 6 12 PHYCLK Networks in Cyclone V SX C2 C4 C5 and C6 Devices and Cyclone V ST D5 and D6 Devices Left PLL Sub Bank Sub Bank I O Bank 7 Sub Bank Sub Bank I O Bank 8 PHYCLK Networks HPS PHYCLK Networks Left PLL Right PLL Sub Bank Sub Bank I O Bank 4 Sub Bank Sub Bank I O Bank 3 PHYCLK Networks Transceiver Banks HPS I O FPGA Device HPS PLL HPS Block Sub Bank Sub Bank I O Bank 5 PHYCLK ...

Page 198: ...an also come from the FPGA fabric Update Enable Circuitry The update enable circuitry enables the registers to allow enough time for the DQS delay settings to travel from the DQS phase shift circuitry or core logic to all the DQS logic blocks before the next change Both the DQS delay settings and the phase offset settings pass through a register before going into the DQS delay chains The registers...

Page 199: ...nal that is used to clock the DQ input registers at the end of a read operation This function ensures that any glitches on the DQS input signal during the end of a read operation and occurring while DQS is in a postamble state do not affect the DQ IOE registers For preamble state the DQS is low just after a high impedance state For postamble state the DQS is low just before it returns to a high im...

Page 200: ...Devices DFF D Q D Q DFF OCT Control OCT Control OCT Half Rate Clock 0 1 D Q DFF D Q DFF 1 0 Write Clock OCT Enable OCT Control Path The full rate write clock comes from the PLL The DQ write clock and DQS write clock have a 90 offset between them Related Information Dynamic OCT in Cyclone V Devices on page 5 40 Provides more information about dynamic OCT control IOE Registers The IOE registers are ...

Page 201: ...ut Registers Read FIFO datain 1 wrclk rdclk datain 0 dataout 3 0 To core Half rate or full rate clock DQS CQ DQ D DFF Q D DFF Q D DFF Q The input clock can be from the DQS logic block or from a global clock line This half rate or full rate read clock comes from a PLL through the clock network Output Registers The Cyclone V output and output enable path is divided into the HDR block and output and ...

Page 202: ...ing from the FPGA core are at half the frequency of the memory interface clock frequency in half rate mode The full rate write clock can come from the PLL The DQ write clock have a 90 offset to the DQS write clock OR2 TRI Delay Chains The Cyclone V devices contain run time adjustable delay chains in the I O blocks and the DQS logic blocks You can control the delay chain setting through the I O or ...

Page 203: ...Enable Control DQS delay chain D4 delay chain dqsbusout DQS T11 delay chain Related Information ALTDQ_DQS2 Megafunction User Guide Provides more information about programming the delay chains DQS Delay Chain on page 6 25 I O and DQS Configuration Blocks The I O and DQS configuration blocks are shift registers that you can use to dynamically change the settings of various device configuration bits ...

Page 204: ...y interface frequencies with shorter latency cycles The hard memory controllers use dedicated I O pins as data address command control clock and ground pins for the SDRAM interface If you do not use the hard memory controllers you can use these dedicated pins as regular I O pins Related Information Functional Description HPC II Controller chapter External Memory Interface Handbook The hard memory ...

Page 205: ...ial addresses every clock cycle if the bank is open This function allows for very high efficiencies with large amounts of data Streaming Reads and Writes The controller can issue reads or writes continuously to random addresses Bank Interleaving The controller can issue bank management commands early so that the correct row is open when the read or write occurs This increases efficiency Predictive...

Page 206: ...nitialization of the memory controller under the control of user logic for example through the software control in the user system if a processor is present User Control of Memory Controller Initialization You can bond two controllers to achieve wider data width for higher bandwidth applications Controller Bonding Support Multi Port Front End The multi port front end MPFE and its associated fabric...

Page 207: ...t wider data widths If you bond two hard memory controllers the data going out of the controllers to the user logic is synchro nized However the data going out of the controllers to the memory is not synchronized The bonding controllers are not synchronized and remain independent with two separate address buses and two independent command buses These buses are calibrated separately If you require ...

Page 208: ...D5 D7 and D9 Devices This figure shows the bonding of two opposite hard memory controllers through the core fabric Bank 8A Bank 7A Bank 4A Bank 3B Bank 3A Hard Memory Controller Hard Memory Controller Bonding Core Routing External Memory Interfaces in Cyclone V Devices Altera Corporation Send Feedback CV 52006 Bonding Support 6 34 2014 01 10 ...

Page 209: ... Not Work for Multiple MPFE Ports in Hard Memory Controller Cyclone V Device Family Pin Connection Guidelines Provides more information about the dedicated pins Hard Memory Controller Width for Cyclone V E Table 6 16 Hard Memory Controller Width Per Side in Cyclone V E Devices Preliminary Member Code Package A9 A7 A5 A4 A2 Bottom Top Bottom Top Bottom Top Bottom Top Bottom Top 0 24 0 24 0 24 M383 ...

Page 210: ...Width Per Side in Cyclone V GX Devices Preliminary Member Code Package C9 C7 C5 C4 C3 Bottom Top Bottom Top Bottom Top Bottom Top Bottom Top 0 0 0 0 M301 0 24 0 24 M383 24 24 M484 0 0 U324 24 24 24 24 24 24 24 24 0 24 U484 24 24 24 40 24 40 24 40 0 24 F484 40 40 40 40 40 40 40 40 F672 40 40 40 40 F896 40 40 F1152 Related Information Guideline Using DQ DQS Pins on page 6 3 Important information abo...

Page 211: ...the hard memory controller in the F484 package of this device Hard Memory Controller Width for Cyclone V SE Table 6 19 Hard Memory Controller Width Per Side in Cyclone V SE Devices Preliminary Member Code Package A6 A5 A4 A2 Bottom Top Bottom Top Bottom Top Bottom Top 0 0 0 0 0 0 0 0 U484 40 0 40 0 40 0 40 0 U672 40 0 40 0 F896 Table 6 20 HPS Hard Memory Controller Width in Cyclone V SE Devices Pr...

Page 212: ...ry Member Code Package C6 C5 C4 C2 40 40 40 40 U672 40 40 F896 Hard Memory Controller Width for Cyclone V ST Table 6 23 Hard Memory Controller Width Per Side in Cyclone V ST Devices Preliminary Member Code Package D6 D5 Bottom Top Bottom Top 40 0 40 0 F896 Table 6 24 HPS Hard Memory Controller Width in Cyclone V ST Devices Preliminary Member Code Package D6 D5 40 40 F896 External Memory Interfaces...

Page 213: ...nk to ALTDQ_DQS2MegafunctionUser Guide for more information about using the delay chains Changed all SoC FPGA to SoC Added links to Altera s External Memory Spec Estimator tool to the topics listing the external memory interface performance Updated the topic about using DQ DQS pins to specify that only some specific DQ pins can also be used as RZQ pins Updated the topic about DQS delay chain to re...

Page 214: ...igures show all possible connections and the device pin out files have per package information 2013 05 06 May 2013 Reorganized content and updated template 2012 11 28 December 2012 Added a list of supported external memory interface standards using the hard memory controller and soft memory controller Added performance information for external memory interfaces and the HPS external memory interfac...

Page 215: ...ctions Added SoC devices information Added Figure 6 5 Figure 6 10 and Figure 6 21 2 0 June 2012 Updated Figure 6 20 Minor text edits 1 2 February 2012 Updated Table 6 2 Added Figure 6 2 1 1 November2011 Initial release 1 0 October 2011 Altera Corporation External Memory Interfaces in Cyclone V Devices Send Feedback 6 41 Document Revision History CV 52006 2014 01 10 ...

Page 216: ...figuration and Configuration via Protocol Cyclone V devices support 1 8 V 2 5 V 3 0 V and 3 3 V programming voltages and several configuration modes ISO 9001 2008 Registered 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in ...

Page 217: ...ion rate and flexibility with the easy to use PCIe hard IP block interface The Cyclone V CvP implementation conforms to the PCIe 100 ms power up to active time requirement Related Information Configuration via Protocol CvP Implementation in Altera FPGAs User Guide Provides more information about the CvP configuration scheme MSEL Pin Settings To select a configuration scheme hardwire the MSEL pins ...

Page 218: ...ny valid MSEL pin settings above Disabled Disabled JTAG based configuration You must also select the configuration scheme in the Configuration page of the Device and Pin Options dialog box in the Quartus II software Based on your selection the option bit in the programming file is set accordingly Note Related Information FPGA Manager Provides more information about the MSEL pin settings for config...

Page 219: ...figuration data to FPGA You can initiate reconfiguration by pulling the nCONFIG pin low to at least the minimum tCFG low pulse width except for configuration using the partial reconfiguration operation When this pin is pulled low the nSTATUS and CONF_DONE pins are pulled low and all I O pins are tied to an internal weak pull up Power Up Power up all the power supplies that are monitored by the POR...

Page 220: ...onfiguration pins I O Standards Voltage Levels in Cyclone V Devices on page 5 8 Provides more information about typical power supplies for each supported I O standards in Cyclone V devices Reset POR delay is the time frame between the time when all the power supplies monitored by the POR circuitry reach the recommended operating voltage and when nSTATUS is released high and the Cyclone V device is...

Page 221: ...guration After the CONF_DONE pin goes high the CLKUSR or DCLK pin is enabled after the time specified by tCD2CU When this time period elapses Cyclone V devices require a minimum number of clock cycles as specified by Tinit to initialize properly and enter user mode as specified by the tCD2UMC parameter Related Information Cyclone V Device Datasheet Provides more information about tCD2CU tinit and ...

Page 222: ...M VCCIO 17 I O Input Optional all schemes DEV_CLRn Pull up I O Output Optional all schemes INIT_DONE VCCPGM Input All schemes MSEL 4 0 VCCPGM Pull up Bidirectional All schemes nSTATUS VCCPGM Input All schemes nCE Pull up I O Output All schemes nCEO VCCPGM Input All schemes nCONFIG VCCPGM VCCIO 17 I O Input FPP x8 and x16 DATA 15 5 VCCPGM Output AS nCSO DATA4 VCCPGM Input FPP VCCPGM Bidirectional A...

Page 223: ...ble 7 4 Configuration Pin Options Option Category Page Configuration Pin Enable user supplied start up clock CLKUSR General CLKUSR Enable device wide reset DEV_CLRn General DEV_CLRn Enable device wide output enable DEV_OE General DEV_OE Enable INIT_DONE output General INIT_DONE Enable nCEO pin General nCEO Enable Error Detection CRC_ERROR pin Error Detection CRC CRC_ERROR Enable open drain on CRC_...

Page 224: ... for both uncompressed and compressed configuration data in an FPP configuration Note Related Information Parallel Flash Loader Megafunction User Guide Cyclone V Device Datasheet Provides more information about the FPP configuration timing Fast Passive Parallel Single Device Configuration To configure a Cyclone V device connect the device to an external host as shown in the following figure Figure...

Page 225: ...irst device in the chain flags an error on the nSTATUS pin it resets the chain by pulling its nSTATUS pin low Ensure that DCLK and DATA are buffered for every fourth device to prevent signal integrity and clock skew problems All devices in the chain must use the same data width If you are configuring the devices in the chain using the same configuration data the devices must be of the same package...

Page 226: ... every fourth device Connect the resistor to a supply that provides an acceptable input signal for the FPGA device VCCPGM must be high enough to meet the VIH specification of the I O on the device and the external host Altera recommends powering up all configuration system I Os with VCCPGM N C 10 kΩ VCCPGM When a device completes configuration its nCEO pin is released low to activate the nCE pin o...

Page 227: ...bit data width and AS x4 4 bit data width modes The AS x4 mode provides four times faster configuration time than the AS x1 mode In the AS configuration scheme the Cyclone V device controls the configuration interface Related Information Cyclone V Device Datasheet Provides more information about the AS configuration timing DATA Clock DCLK Cyclone V devices generate the serial clock DCLK that provi...

Page 228: ...t 3 0 or 3 3 V power supply For more information refer to the MSEL pin settings Use the CLKUSR pin to supply the external clock source to drive DCLK during configuration Figure 7 6 Single Device AS x4 Mode Configuration AS_DATA0 ASDO AS_DATA1 AS_DATA2 AS_DATA3 DCLK nCSO EPCQ Device FPGA Device 10 kΩ 10 kΩ 10 kΩ VCCPGM GND nCEO nCE nSTATUS nCONFIG CONF_DONE N C MSEL 4 0 CLKUSR VCCPGM VCCPGM DATA0 D...

Page 229: ... all devices in the chain together nCONFIG nSTATUS DCLK DATA CONF_DONE By tying the CONF_DONE nSTATUS and nCONFIG pins together the devices initialize and enter user mode at the same time If any device in the chain detects an error configuration stops for the entire chain and you must reconfigure all the devices For example if the first device in the chain flags an error on the nSTATUS pin it rese...

Page 230: ...rce to drive DCLK during configuration 10 kΩ VCCPGM When a device completes configuration its nCEO pin is released low to activate the nCE pin of the next device in the chain Configuration automatically begins for the second device in one clock cycle Estimating the Active Serial Configuration Time The AS configuration time is mostly the time it takes to transfer the configuration data from an EPCS...

Page 231: ...aximum Board Load pF Maximum Board Trace Length Inches Cyclone V Device AS Pins 100 MHz 12 5 25 50 MHz 5 6 10 DCLK 10 6 10 DATA 3 0 10 6 10 nCSO Programming EPCS and EPCQ Devices YoucanprogramEPCSandEPCQdevicesin systemusingaUSB Blaster EthernetBlaster EthernetBlasterII or ByteBlaster II download cable Alternatively you can program the EPCS or EPCQ using a microprocessor with the SRunner software ...

Page 232: ...resistors to VCCPGM at a 3 0 or 3 3 V power supply The resistor value can vary from 1 kΩ to 10 kΩ Perform signal integrity analysis to select the resistor value for your setup For more information refer to the MSEL pin settings Instantiate SFL in your design to form a bridge between the EPCS and the 10 pin header Use the CLKUSR pin to supply the external clock source to drive DCLK during configura...

Page 233: ...tor value can vary from 1 kΩ to 10 kΩ Perform signal integrity analysis to select the resistor value for your setup For more information refer to the MSEL pin settings Instantiate SFL in your design to form a bridge between the EPCQ and the 10 pin header Use the CLKUSR pin to supply the external clock source to drive DCLK during configuration Programming EPCS Using the Active Serial Interface To p...

Page 234: ...ly Power up the USB Blaster ByteBlaster II EthernetBlaster or EthernetBlaster II cable s VCC TRGT to VCCPGM For more information refer to the MSEL pin settings Use the CLKUSR pin to supply the external clock source to drive DCLK during configuration Programming EPCQ Using the Active Serial Interface To program an EPCQ device using the AS interface connect the device as shown in the following figur...

Page 235: ...lone V device in the reset stage After programming completes the download cable releases nCE and nCONFIG allowing the pull down and pull up resistors to drive the pin to GND and VCCPGM respectively During the EPCQ programming using the download cable DATA0 transfers the programming data operation command and address information from the download cable into the EPCQ During the EPCQ verification usi...

Page 236: ...V device connect the device to an external host as shown in the following figure Figure 7 12 Single Device PS Configuration Using an External Host External Host MAX II Device MAX V Device or Microprocessor CONF_DONE nSTATUS nCE DATA0 nCONFIG FPGA Device Memory ADDR GND 10 kΩ DCLK nCEO N C MSEL 4 0 DATA0 10 kΩ VCCPGM VCCPGM Connect the resistor to a power supply that provides an acceptable input si...

Page 237: ...ulti Device Configuration You can configure multiple Cyclone V devices that are connected in a chain Pin Connections and Guidelines Observe the following pin connections and guidelines for this configuration setup Tie the following pins of all devices in the chain together nCONFIG nSTATUS DCLK DATA0 CONF_DONE By tying the CONF_DONE and nSTATUS pins together the devices initialize and enter user mo...

Page 238: ...ically begins for the second device in one clock cycle Using One Configuration Data To configure multiple Cyclone V devices in a chain using one configuration data connect the devices to an external host as shown in the following figure Figure 7 15 Multiple Device PS Configuration When Both Devices Receive the Same Set of Configuration Data External Host MAX II Device MAX V Device or Microprocesso...

Page 239: ... pull up resistors on DATA0 and DCLK In the USB Blaster and ByteBlaster II cables this pin is connected to nCE when you use it for AS programming Otherwise this pin is a no connect For more information refer to the MSEL pin settings When a device completes configuration its nCEO pin is released low to activate the nCE pin of the next device Configuration automatically begins for the second device ...

Page 240: ...e programming data from the TDI pin to the TDO pin through a single bypass register The configuration data is available on the TDO pin one clock cycle later The Quartus II software can use the CONF_DONE pin to verify the completion of the configuration process through the JTAG port CONF_DONE pin is low indicates that configuration has failed CONF_DONE pin is high indicates that configuration was s...

Page 241: ...ner as your software driver Figure 7 18 JTAG Configuration of a Single Device Using a Microprocessor Microprocessor CONF_DONE nSTATUS nCE nCONFIG FPGA Device Memory ADDR GND DCLK TDI TCK TMS nCEO N C MSEL 4 0 DATA TDO 10 kΩ 10 kΩ VCCPGM Connect the pull up resistor to a supply that provides an acceptable input signal for all FPGA devices in the chain VCCPGM must be high enough to meet the VIH spec...

Page 242: ... VIO FPGA Device FPGA Device FPGA Device 1 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ 10 kΩ DCLK TMS TCK TDI TDO nSTATUS nCONFIG MSEL 4 0 nCE CONF_DONE DCLK TMS TCK TDI TDO nSTATUS nCONFIG MSEL 4 0 nCE CONF_DONE DCLK Connect the pull up resistor VCCPD If you only use the JTAG configuration connect nCONFIG to VCCPGM and MSEL 4 0 to GND Pull DCLK either high or low whichever is convenient on your board If you...

Page 243: ...t Menu click Device 2 Select your Cyclone V device and then click Device and Pin Options 3 In the Device and Pin Options window select Configuration under the Category list and turn on Generate compressed bitstreams Enabling Compression After Design Compilation To enable compression after design compilation follow these steps 1 On the File menu click Convert Programming Files 2 Select the programm...

Page 244: ...ade Circuitry Data Data Data Configuration Memory 2 3 4 1 You can design your system to manage remote upgrades of the application configuration images in the configuration device The following list is the sequence of the remote system upgrade 1 The logic embedded processor or user logic in the Cyclone V device receives a configuration image from a remote location You can connect the device to the ...

Page 245: ...images at the following locations in the EPCS or EPCQ devices Factory configuration image PGM 23 0 24 h000000 start address on the EPCS or EPCQ device Application configuration image any sector boundary Altera recommends that you store only one image at one sector boundary Configuration Sequence in the Remote Update Mode Figure 7 22 Transitions Between Factory and Application Configurations in Rem...

Page 246: ...lated Information Cyclone V Device Datasheet Provides more information about remote system upgrade circuitry timing specifications Enabling Remote System Upgrade Circuitry To enable the remote system upgrade feature follow these steps 1 Select Active Serial x1 x4 or Configuration Device from the Configuration scheme list in the Configu ration page of the Device and Pin Options dialog box in the Qu...

Page 247: ...riggered this register is updated with the contents of the update register Control This register is clocked by RU_CLK The factory configuration updates this register by shifting data into the shift register and issuing an update When reconfigura tion is triggered the contents of the update register are written to the control register Update After each reconfiguration the remote system upgrade circ...

Page 248: ...e 12 b000000000000 Wd_timer 11 0 26 37 Status Register Table 7 8 Status Register Bits Description Reset Value 19 Name Bit When set to 1 indicates CRC error during application configuration 1 b0 CRC 0 When set to 1 indicates that nSTATUS is asserted by an external device due to error 1 b0 nSTATUS 1 When set to 1 indicates that reconfiguration has been triggered by the logic array of the device 1 b0...

Page 249: ...y configuration user mode operation You cannot disable this feature in the application configuration Note The counter is 29 bits wide and has a maximum count value of 229 When specifying the user watchdog timer value specify only the most significant 12 bits The granularity of the timer setting is 217 cycles The cycle time is based on the frequency of the user watchdog timer internal oscillator Th...

Page 250: ...ty with Cyclone V devices in an FPP configuration scheme it requires a different DCLK to DATA ratio ALTCHIP_ID Megafunction The ALTCHIP_ID megafunction provides the following features Acquiring the chip ID of an FPGA device Allowing you to identify your device in your design as part of a security feature to protect your design from an unauthorized device Related Information ALTCHIP_ID Megafunction...

Page 251: ...sure that the nSTATUS pin is released high before any key programming attempts To clear the volatile key issue the KEY_CLR_VREG JTAG instruction To verify the volatile key has been cleared issue the KEY_VERIFY JTAG instruction Note Related Information Supported JTAG Instruction on page 9 3 Provides more information about the KEY_CLR_VREG and KEY_VERIFY instructions JTAG Boundary Scan Testing in Cy...

Page 252: ...t accept the encrypted configuration file if the volatile key is erased If the volatile key is erased and you want to reprogram the key you must use the volatile key security mode Note Enabling the tamper protection bit disables the test mode in Cyclone V devices and disables programming through the JTAG interface This process is irreversible and prevents Altera from carrying out failure analysis ...

Page 253: ...13 Removed support for active serial multi device configuration using the same configuration data 2013 05 10 May 2013 Added link to the known document issues in the Knowledge Base Added the ALTCHIP_ID megafunction section Updated Connection Setup for Programming the EPCS Using the JTAG Interface and Connection Setup for Programming the EPCQ Using the JTAG Interface figures Added links for AS PS FP...

Page 254: ...CRC values do not match the nSTATUS pin is set to low to indicate a configuration error You can test the capability of this feature by modifying the configuration bitstream or intentionally corrupting the bitstream during configuration User Mode Error Detection In user mode the contents of the configured CRAM bits may be affected by soft errors These soft errors which are caused by an ionizing par...

Page 255: ...termines the error type for single bit and double adjacent errors The probability of other error patterns is very low and the reporting of bit location is not guaranteed The probability of more than five CRAM bits being flipped by soft errors is very low In general the probability of detection for all error patterns is 99 9999 The process of error detection continues until the device is reset by s...

Page 256: ...nal Oscillator Frequency 2n Table 8 2 Error Detection Frequency Range for Cyclone V Devices The following table lists the frequencies and valid values of n Divisor Range n Error Detection Frequency Internal Oscillator Frequency Minimum Maximum 1 256 0 1 2 3 4 5 6 7 8 390 kHz 100 MHz 100 MHz CRC Calculation Time The time taken by the error detection circuitry to calculate the CRC for each frame is ...

Page 257: ...40 15 C9 3 54 7 D5 Cyclone V GT 3 62 7 D7 7 40 15 D9 3 59 7 A2 Cyclone V SE 3 59 7 A4 6 30 13 A5 6 30 13 A6 3 59 7 C4 Cyclone V SX 6 30 13 C5 6 30 13 C6 6 30 13 D5 Cyclone V ST 6 30 13 D6 Using Error Detection Features in User Mode This section describes the pin registers process flow and procedures for error detection in user mode Enabling Error Detection To enable user mode error detection in th...

Page 258: ... atom to the dedicated CRC_ERROR pin or any user I O pin To route the crcerror port to a user I O pin insert a D type flipflop between them I O or output output open drain CRC_ERROR Error Detection Registers This section describes the registers used in user mode Figure 8 2 Block Diagram for Error Detection in User Mode The block diagram shows the registers and data flow in user mode Error Injectio...

Page 259: ...register via the JTAG interface using the SHIFT_ EDERROR_REG JTAG instruction 67 JTAG shift register This register is automatically updated with the contents of the EMR one clock cycle after the contents of this register are validated The user update register includes a clock enable which must be asserted before its contents are written to the user shift register This requirement ensures that the ...

Page 260: ...43 Bit 44 Bit 45 No error 0 0 0 0 Single bit error 1 0 0 0 Double adjacent error 0 1 0 0 Error Detection Process When enabled the user mode error detection process activates automatically when the FPGA enters user mode The process continues to run until the device is reset even when an error is detected in the current frame Figure 8 4 Error Detection Process Flow in User Mode Yes No Receive Data F...

Page 261: ...ust control device reconfiguration To recover from a CRC error drive the nCONFIG signal low The system waits for a safe time before reconfiguring the device When reconfiguration completes successfully the FPGA operates as intended Related Information Error Detection Frequency on page 8 3 Provides more information about the minimum and maximum error detection frequencies Minimum EMR Update Interval...

Page 262: ...r detection block Document Revision History Changes Version Date Updated the CRC Calculation Time section to include a formula to calculate the minimum and maximum time Removed preliminary for the Minimum EMR Update Interval and CRC Calculation Time Removed related information for the Internal Scrubbing feature 2013 11 12 November2013 Added link to the known document issues in the Knowledge Base U...

Page 263: ...QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in a...

Page 264: ...000 C3 Cyclone V GX 1 000 0110 1110 001010110001 0010 0000 C4 1 000 0110 1110 001010110000 0010 0000 C5 1 000 0110 1110 001010110000 0011 0000 C7 1 000 0110 1110 001010110000 0100 0000 C9 1 000 0110 1110 001010110000 0010 0000 D5 Cyclone V GT 1 000 0110 1110 001010110000 0011 0000 D7 1 000 0110 1110 001010110000 0100 0000 D9 1 000 0110 1110 001011010001 0001 0000 A2 Cyclone V SE 1 000 0110 1110 00...

Page 265: ...uction Table 9 2 JTAG Instructions Supported by Cyclone V Devices Description Instruction Code JTAG Instruction Allows you to capture and examine a snapshot of signals at the device pins during normal device operation and permits an initial data pattern to be an output at the device pins Use this instruction to preload the test data into the update registers before loading the EXTEST instruc tion ...

Page 266: ...ic signature UES within the devices along a JTAG chain Selects the 32 bit USERCODE register and places it between the TDI and TDO pins to allow serial shifting of USERCODE out of TDO The UES value is set to default value before configuration and is only user defined after the device is configured 00 0000 0111 USERCODE Identifies the devices in a JTAG chain If you select IDCODE the device identific...

Page 267: ...h the selected devices to adjacent devices while holding the I O pins to a state defined by the data in the boundary scan register If you are testing the device after configuration the programmable weak pull up resistor or the bus hold feature overrides the CLAMP value at the pin The CLAMP value is the value stored in the update register of the boundary scan cell BSC 00 0000 1010 CLAMP Emulates pu...

Page 268: ...read the device IDCODE correctly you must issue the IDCODE JTAG instruction only when the nCONFIG and nSTATUS signals are high Note Related Information JTAG Secure Mode on page 7 35 Provides more information about PULSE_NCONFIG CONFIG_IO LOCK and UNLOCK JTAG instructions Configuration Design Security and Remote System Upgrades in Cyclone V Devices Provides more information about PULSE_NCONFIG CONF...

Page 269: ...st meet the specification of the TDI pin it drives Table 9 3 Supported TDO and TDI Voltage Combinations The TDO output buffer for VCCPD of 3 3 V or 3 0 V meets VOH MIN of 2 4 V and the TDO output buffer for VCCPD of 2 5 V meets VOH MIN of 2 0 V Cyclone V TDO VCCPD TDI Input Buffer Power V Device VCCPD 2 5 V VCCPD 3 0 V VCCPD 3 3 V Yes Yes Yes VCCPD 3 3 Cyclone V Yes Yes Yes VCCPD 3 0 Yes Yes Yes V...

Page 270: ...ons Configuration Design Security and Remote System Upgrades in Cyclone V Devices Provides more information about JTAG configuration Cyclone V Device Datasheet Provides more information about JTAG configuration timing Enabling and Disabling IEEE Std 1149 1 BST Circuitry The IEEE Std 1149 1 BST circuitry is enabled after the Cyclone V device powers up However for Cyclone V SoC FPGAs you must power ...

Page 271: ...t to avoid contention with other devices in the system Do not perform EXTEST testing during in circuit reconfiguration because EXTEST is not supported during in circuit reconfiguration To perform testing wait for the configuration to complete or issue the CONFIG_IO instruction to interrupt configuration After configuration you cannot test any pins in a differential pin pair To perform BST after co...

Page 272: ...OUTJ OEJ and PIN_IN signals Update registers Connect to external data through the PIN_OUT and PIN_OE signals The TAP controller generates the global control signals for the IEEE Std 1149 1 BST registers shift clock and update internally A decode of the instruction register generates the MODE signal The data signal path for the boundary scan register runs from the serial data in SDI signal to the s...

Page 273: ...e capture and update register capabilities of all BSCs within Cyclone V devices Comments Drives Captures Pin Type Input Update Register OE Update Register Output Update Register Input Capture Register OE Capture Register Output Capture Register INJ PIN_OE PIN_OUT PIN_IN OEJ OUTJ User I O pins PIN_IN drives to the clock network or logic array N C N C No Connect N C PIN_IN 1 0 Dedicated clock input ...

Page 274: ...hanges Version Date Added a note to the Performing BST section Updated the KEY_CLR_VREG JTAG instruction 2014 01 10 January 2014 Added link to the known document issues in the Knowledge Base Moved all links to the Related Information section of respective topics for easy reference 2013 05 06 May 2013 Reorganized content and updated template 2012 12 28 December 2012 Restructured the chapter Updated...

Page 275: ...ignal activity or toggling Dynamic Power Equation Figure 10 1 Dynamic Power The following equation shows how to calculate dynamic power where P is power C is the load capacitance and V is the supply voltage level ISO 9001 2008 Registered 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporati...

Page 276: ...wer up or power down Because the Cyclone V device does not drive signals out before or during power up the device does not affect the other operating buses You can insert or remove a Cyclone V device from a powered up system board without damaging or interfering with the system board s operation This capability allows you to avoid sinking current through the device signal pins to the device power ...

Page 277: ...lone V Devices VCCIO PAD R Voltage Tolerance Control Output Enable Hot Socket Output Pre Driver Power On Reset POR Monitor Weak Pull Up Resistor Input Buffer to Logic Array The POR circuitry monitors the voltage level of the power supplies and keeps the I O pins tri stated until the device is in user mode The weak pull up resistor R in the Cyclone V input output element IOE is enabled during confi...

Page 278: ...about the minimum current requirements refer to the PowerPlay Early Power Estimator EPE and compare to the information listed in the following table If the current transient exceeds the minimum current requirements in the PowerPlay EPE you need to take the information into consideration for your power regulator design Table 10 1 Maximum Power Supply Current Transient and Typical Duration Typical D...

Page 279: ...rogramming registers remain tri stated during which device configuration could fail 28 Only typical duration is provided as it may vary on the board design 33 These power rails are only available on Cyclone V SX SE and ST devices 34 You may observe the current transient at VCCPD_HPS only when you do not follow the recommended power up sequence To avoid the current transient at VCCPD_HPS follow the...

Page 280: ...power up In user mode the main POR signal is asserted when any of the monitored power goes below its POR trip level Asserting the POR signal forces the device into the reset state The POR circuitry checks the functionality of the I O level shifters powered by the VCCPD and VCCPGM power supplies during power up mode The main POR circuitry waits for all the individual POR circuitries to release the ...

Page 281: ...nformation about the MSEL pin settings for each POR delay Document Revision History Changes Version Date Updated the note to the VCCPD_HPS power rail that current transient at VCCPD_HPS is observed only when the recommended power up sequence is not followed To avoid the current transient at VCCPD_HPS follow the recommended power up sequence Added Group 1 and Group 2 to the Power Up Sequence 2014 0...

Page 282: ...Reorganized content and updated template 2012 12 28 December 2012 Restructured the chapter 2 0 June 2012 Initial release 1 0 October 2011 Power Management in Cyclone V Devices Altera Corporation Send Feedback CV 52010 Document Revision History 10 8 2014 01 10 ...

Page 283: ...Cyclone V Device Handbook Volume 2 Transceivers 101 Innovation Drive San Jose CA 95134 www altera com CV 5V3 2013 10 17 Subscribe Send Feedback ...

Page 284: ...Bonding 1 49 PLL Sharing 1 49 Document Revision History 1 49 Transceiver Clocking in Cyclone V Devices 2 1 Input Reference Clocking 2 1 Dedicated Reference Clock Pins 2 2 Fractional PLL fPLL 2 4 Internal Clocking 2 5 Transmitter Clock Network 2 5 Transmitter Clocking 2 9 Receiver Clocking 2 14 FPGA Fabric Transceiver Interface Clocking 2 18 Transceiver Datapath Interface Clocking 2 21 Transmitter ...

Page 285: ...ransceiver Reset Control Signals Using Avalon Memory Map Registers 3 11 Clock Data Recovery Manual Lock Mode Reset Sequence 3 12 Control Settings for CDR Manual Lock Mode 3 12 Resetting the Transceiver in CDR Manual Lock Mode 3 13 Resetting the Transceiver During Dynamic Reconfiguration 3 13 Guidelines for Dynamic Reconfiguration if Transmitter Duty Cycle Distortion Calibration is Required during ...

Page 286: ...Cyclone V Devices 5 1 Standard PCS Configuration 5 1 Custom Configuration Channel Options 5 2 Rate Match FIFO in Custom Configuration 5 5 Standard PCS in Low Latency Configuration 5 6 Low Latency Custom Configuration Channel Options 5 7 Document Revision History 5 10 Transceiver Loopback Support 6 1 Serial Loopback 6 1 Forward Parallel Loopback 6 2 PIPE Reverse Parallel Loopback 6 3 Reverse Serial...

Page 287: ...iguration 7 5 Transceiver Interface Reconfiguration 7 5 Reduced mif Reconfiguration 7 6 Unsupported Reconfiguration Modes 7 6 Document Revision History 7 7 Altera Corporation TOC 5 Cyclone V Device Handbook Volume 2 Transceivers ...

Page 288: ...ical medium attachment PMA layers ISO 9001 2008 Registered 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respe...

Page 289: ...ock Networks Transceiver Individual Channels The embedded high speed clock networks in Cyclone V devices provide dedicated clocking connectivity for the transceivers You can also use the fractional phase locked loop fPLL between the PMA and PCS to clock the transceivers The embedded PCIe hard intellectual property IP of Cyclone V devices implements the following PCIe protocol stacks Physical inter...

Page 290: ...2 and GXB_L3 The location of the transceiver bank boundaries are important for clocking resources bonding channels and fitting In some package variations the total transceiver count is reduced Figure 1 2 GX GT Devices with Three or Five Transceiver Channels and One PCIe HIP Block The PCIe HIP block is located across Ch 1 and Ch 2 of banks GXB_L0 GXB_L1 GXB_L0 Transceiver Bank Names PCIe Hard IP No...

Page 291: ... GXB_L1 GXB_L0 Transceiver Bank Names PCIe Hard IP Notes 1 4 channel device transceiver channels are located on bank L0 and Ch 5 of bank L1 2 6 channel device transceiver channels are located on banks L0 and L1 Ch 2 Ch 1 Ch 0 Ch 5 Ch 4 Ch 3 4 Ch 1 6 Ch 2 PCIe Hard IP Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback CV 53001 Transceiver Banks 1 4 2013 05 06 ...

Page 292: ... and Ch 1 and Ch 2 of bank GXB_L2 GXB_L1 GXB_L0 Transceiver Bank Names PCIe Hard IP Note 1 9 channel device transceiver channels are located on banks L0 L1 and L2 Ch 2 Ch 1 Ch 0 Ch 5 Ch 4 Ch 3 9 Ch 1 PCIe Hard IP Ch 2 Ch 1 Ch 0 GXB_L2 Altera Corporation Transceiver Architecture in Cyclone V Devices Send Feedback 1 5 Transceiver Banks CV 53001 2013 05 06 ...

Page 293: ... of bank GXB_L2 GXB_L1 GXB_L0 Transceiver Bank Names PCIe Hard IP Note 1 12 channel device transceiver channels are located on banks L0 L1 L2 and L3 Ch 2 Ch 1 Ch 0 Ch 5 Ch 4 Ch 3 12 Ch 1 PCIe Hard IP GXB_L2 Ch 2 Ch 1 Ch 0 Ch 5 Ch 4 Ch 3 GXB_L3 Transceiver Architecture in Cyclone V Devices Altera Corporation Send Feedback CV 53001 Transceiver Banks 1 6 2013 05 06 ...

Page 294: ...ed channels The affected channels can still be used as a CMU to clock the CPRI channels Table 1 1 Usage Restrictions on Specific Channels Across Device Variants Usage Restriction Channel Bank Location Channels No 6 144 Gbps CPRI support NosupportforPCSwithphasecompensationFIFO in registered mode GXB_L0 Ch 1 Ch 2 GXB_L1 1 Ch 4 Ch 5 GXB_L2 1 Ch 1 Ch 2 Cyclone V GX transceiver channels are comprised ...

Page 295: ...lock frequency for the 6 144 Gbps CPRI channel must be 307 2 MHz Related Information Transceiver Protocol Configurations in Cyclone V Devices Transceiver Channel Architecture Cyclone V transceiver channels support the following interface methods with the FPGA fabric Directly bypassing the PIPE interface for the PCIe interface and PCIe hard IP block Through the PIPE interface and PCIe hard IP block...

Page 296: ...optionally for the receiver PCS The central clock divider can additionally feed the clock lines used to bond channels compared to the local clock divider Figure 1 8 PMA Block Diagram of a Transceiver Channel in Cyclone V Devices Transmitter PMA Receiver PMA Physical Transmission Medium Serializer Clock Divider Transmitter Buffer Receiver Buffer From the Transmitter PCS or FPGA Fabric 1 High speed ...

Page 297: ... The serializer block sends out the LSB of the input data first The transmitter serializer also has polarity inversion and bit reversal capabilities Transmitter Polarity Inversion The positive and negative signals of a serial differential link might accidentally be swapped during board layout The transmitter polarity inversion feature is provided to correct this situation without requiring a board...

Page 298: ...es withing transmitter output buffers can be performed by a single reconfig uration controller for the entire FPGA or multiple reconfiguration controllers if desired Within each transceiver bank three transceiver channels a maximum of one reconfiguration controller is allowed There is only one slave interface to all PLLs and PMAs within each transceiver bank Therefore many transceiver banks can be...

Page 299: ...the receiver end Use the pre emphasis feature to maximize the data opening at the far end receiver Programmable Pre Emphasis Controls the rate of change for the signal transition Programmable Slew Rate Establishes the required transmitter common mode voltage TX VCM level at the transmitter output The circuitry is available only if you enable OCT When you disable OCT you must implement off chip bia...

Page 300: ...nality the series capacitor AC coupled link and receiver termination values must comply with the PCI Express Base Specification 2 0 for Gen1 and Gen2 signaling rates The circuit is clocked using fixedclk and requires an enabled transmitter OCT with the output tri stated Receiver Detect Transmitter Buffer Features and Capabilities Table 1 5 Transmitter Buffer Features Capability Feature Up to 1200 ...

Page 301: ...you enable transmitter OCT for receiver detect operation TX VCM Differential Termination Transmitter Receiver RX VCM Differential Termination Physical Medium Physical Medium AC Coupling Capacitor AC Coupling Capacitor 1 Notes 1 When you disable OCT you must implement external termination and off chip biasing circuitry to establish the required TX VCM level Programmable Transmitter Analog Settings ...

Page 302: ... PCIe Receiver Detect The transmitter buffers have a built in receiver detection circuit for use in PCIe configurations for Gen1 and Gen2 data rates This circuit detects whether there is a receiver downstream by sending out a pulse on the common mode of the transmitter and monitoring the reflection PCIe Electrical Idle The transmitter output buffers support transmission of PCIe electrical idle or ...

Page 303: ...cts causing incorrect sampling on the input data at the receiver The amount of the high frequency boost required at the receiver to overcome signal attenuation depends on the loss characteristics of the physical medium Programmable Continuous Time Linear Equalization CTLE Improve Signal Integrity Provides equal boost to the received signal across the frequency spectrum Programmable DC Gain Establi...

Page 304: ...ple the receiver to a transmitter In an AC coupled link the AC coupling capacitor blocks the transmitter common mode voltage At the receiver end the termination and biasing circuitry restores the common mode voltage level that is required by the receiver Figure 1 13 AC Coupled Link with a Cyclone V Receiver TX VCM Differential Termination Transmitter Receiver RX VCM Differential Termination Physic...

Page 305: ...ization circuitry provides up to 4 dB of high frequency boost Each receiver buffer also supports the programmable DC gain circuitry that provides an equal boost to the incoming signal across the frequency spectrum The DC gain circuitry provides up to 3 dB of gain setting Programmable Receiver VCM The receiver buffers have on chip biasing circuitry to establish the required VCM at the receiver inpu...

Page 306: ...lock from CDR D2 D1 Figure 1 16 Deserializer Bit Order with 10 bit Deserialization Factor The serial stream 0101111100 is deserialized to a 10 h17C value The serial data is received LSB to MSB dataout 1010000011 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0101111100 datain Serial Clock Parallel Clock Clock slip Word alignment in the PCS may contribute up to one parallel clock cycle of latency uncertai...

Page 307: ...ols the VCO output frequency to half the data rate with the appropriate counter M or L value given an input reference clock frequency The lock detect determines whether the PLL has achieved lock to the phase and frequency of the input reference clock In LTD mode the channel PLL tracks the incoming serial data The phase detector compares the phase of the VCO output and the incoming serial data The ...

Page 308: ...rence clock You must hold the receiver PCS in reset until the CDR PLL locks to data and produces a stable recovered clock After the receiver power up and reset cycle you must keep the CDR in LTR mode until the CDR locks to the input reference clock When locked to the input reference clock the CDR output clock is trained to the configured data rate The CDR then switches to LTD mode to recover the c...

Page 309: ...erence clock The receiver PCS logic must be held in reset until the CDR produces a stable recovered clock CDR PLL in Automatic Lock Mode In automatic lock mode the LTR LTD controller directs the transition between the LTR and LTD modes when a set of conditions are met to ensure proper CDR PLL operation The mode transitions are indicated by the rx_is_lockedtodata status signal After power up or res...

Page 310: ...des the flexibility to manually control the CDR PLL mode transitions bypassing the PPM detection as required by certain applications that include but not limited to the following Link with frequency differences between the upstream transmitter and the local receiver clocks exceeding the CDR PLL ppm threshold detection capability For example a system with asynchronous spread spectrum clocking SSC d...

Page 311: ... x6 clock lines Related Information Transceiver Clocking in Cyclone V Devices fPLL as a Transmitter PLL In addition to CMU PLL the fPLL located adjacent to the transceiver banks are available for clocking the transmitters for serial data rates up to 3 125 Gbps Related Information Clock Networks and PLLs in Cyclone V Devices Clock Divider Each Cyclone V transmitter channel has a clock divider There...

Page 312: ... can divide the serial clock input to provide the parallel and serial clocks for the serializer in the channel if you use clocks from the clock lines or transmit PLLs The central clock divider can additionally drive the x6 clock lines used to bond multiple channels In bonded channel configurations both types of clock dividers can feed the serializer with the parallel and serial clocks directly wit...

Page 313: ...al reference voltage and external reference resistor to generate constant reference currents You must connect the external reference resistor to the RREF pin Note These reference currents are used by the analog block calibration circuit to calibrate the transceiver banks You must connect a separate 2 kΩ tolerance max 1 external resistor on each RREF pin to ground To ensure the calibration block op...

Page 314: ...eclkin rx_coreclkin Recovered Clock from Master Channel Parallel Clock Serial Clock Serial Clock Parallel Clock tx_clkout rx_clkout The transceiver channel PCS datapath is categorized into two configurations single width and double width based on the transceiver channel PMA PCS width or serialization deserialization factor Table 1 10 PCS Datapath Configurations Double Width Single Width Parameters...

Page 315: ... modes and running disparity control 8B 10B Encoder Enables user controlled bit level delay in the data prior to serialization for serial transmission Supports operation in single and double width modes Transmitter Bit Slip Transmitter Phase Compensation FIFO The transmitter phase compensation FIFO is four words deep and interfaces with the transmitter channel PCS and the FPGA fabric or PCIe hard ...

Page 316: ...at higher data rates while keeping the FPGA fabric interface frequency within the maximum limit The byte serializer supports operation in single and double width modes The datapath clock rate at the output of the byte serializer is twice the FPGA fabric transmitter interface clock frequency The byte serializer forwards the least significant word first followed by the most significant word You must...

Page 317: ...dth mode the 8B 10B encoder generates 10 bit code groups from 8 bit data and 1 bit control identifier with proper disparity according to the PCS reference diagram in the Clause 36 of the IEEE 802 3 specification The 10 bit code groups are generated as valid data code groups Dx y or special control code groups Kx y depending on the 1 bit control identifier Figure 1 23 8B 10B Encoder in Single Width...

Page 318: ...der LSB Encoding Running Disparity Control The 8B 10B encoder automatically performs calculations that meet the running disparity rules when generating the 10 bit code groups The running disparity control feature provides user controlled signals tx_dispval and tx_forcedisp to manually force encoding into a positive or negative current running disparity code group When you enable running disparity ...

Page 319: ...lags Reset Condition The reset_tx_digital signal resets the 8B 10B encoder During reset the running disparity and data registers are cleared Also the 8B 10B encoder outputs a K28 5 pattern from the RD column continuously until reset_tx_digital is deasserted The input data and control code from the FPGA fabric is ignored during the reset state After reset the 8B 10B encoder starts with a negative d...

Page 320: ...e sending encoded 8 bit data at its input Continuously sends the K28 5 code from the RD column Single Width Some don t cares are seen due to pipelining in the transmitter channel followed by Three K28 5 codes from the RD column before sending encoded 8 bit data at its input on LSByte Three K28 5 codes from the RD column before sending encoded 8 bit data at its input on MSByte Continuously sends th...

Page 321: ... frequency differences of up to 300 parts per million ppm 600 ppm total between the upstream transmitter and the local receiver clocks by inserting or deleting skip symbols when necessary Supports operation that is compliant to the clock rate compensation function in supported protocols Rate Match FIFO Receives 10 bit data and decodes the data into an 8 bit data and a 1 bit control identifier in c...

Page 322: ...oring the word boundary the word aligner implements the following features Synchronization state machine Programmable run length violation detection for all transceiver configurations Receiver polarity inversion for all transceiver configurations except PCIe Receiver bit reversal for custom single and double width configurations only Receiver byte reversal for custom double width configuration onl...

Page 323: ...ent 16 User controlled signal shifts data one bit at a time 8 16 and 32 Bit Slip Alignment happens automatically after RX PCS reset User controlled signal starts the alignment process thereafter Alignment happens once unless the signal is reasserted 7 10 and 20 Manual Alignment 20 User controlled signal shifts data one bit at a time 7 10 and 20 Bit Slip User controlled signal starts the alignment ...

Page 324: ...esynchronize to the new word boundary create a 0 to 1 transition to the rx_enapatternalign register 6 When the word aligner synchronized to the new word boundary the rx_patterndetect and rx_syncstatus signals will assert for one parallel clock cycle 8 Single Width 1 After the rx_digitalreset signal deasserts setting the rx_ enapatternalign register to 1 triggers the word aligner to look for the pr...

Page 325: ...m effectively shifting the word boundary by one bit Also in bit slip mode the word aligner pcs8g_rx_wa_status register bit for rx_patterndetect is driven high for one parallel clock cycle when the received data after bit slipping matches the 16 bit word alignment pattern programmed To achieve word alignment you can implement a bit slip controller in the FPGA fabric that monitors the rx_parallel_da...

Page 326: ... the predefined word alignment pattern or its complement in the received data stream and automatically aligns to the new word boundary 2 Synchronization is achieved only after the word aligner receives the programmed number of valid synchronization code groups in the same word boundary and is indicated with the assertion of the rx_syncstatus signal 3 After assertion and achieving synchronization t...

Page 327: ... aligner indicates loss of synchronization rx_syncstatus remains low until the programmed number of valid synchronization code groups are received again Word Aligner Operations in Deterministic Latency State Machine Mode In deterministic latency state machine mode word alignment is achieved by performing a clock slip in the deserializer until the deserialized data coming into the receiver PCS is w...

Page 328: ...on feature inverts the polarity of every bit at the input to the word aligner which has the same effect as swapping the positive and negative signals of the serial differential link Inversion is controlled dynamically with the rx_invpolarity register When you enable the polarity inversion feature initial disparity errors may occur at the receiver with the 8B 10B coded data The receiver must be abl...

Page 329: ... width at the word aligner the two symbols are bits 15 8 and bits 7 0 For a 20 bit input data width at the word aligner the two symbols are bits 19 10 and bits 9 0 The byte reversal feature at the word aligner output corrects the swapped signal error by swapping the two symbols in double width mode at the word aligner output as listed in Table 1 26 Table 1 26 Byte Reversal Feature Word Aligner Out...

Page 330: ...r defined for custom configurations For protocol configurations the rate match FIFO is automatically configured to support a clock rate compensation function as required by the following specifications The PCIe protocol per clock tolerance compensation requirement as specified in the PCI Express Base Specification 2 0 for Gen1 and Gen2 signaling rates The Gbps Ethernet GbE protocol per clock rate ...

Page 331: ...When receiving the 20 bit code group the 10 bit LSByte is decoded first and the ending running disparity is forwarded to the other 8B 10B decoder for decoding the 10 bit MSByte Figure 1 29 8B 10B Decoder in Double Width Mode datain 19 10 dataout 15 8 control identifier error status 8B 10B Decoder MSByte Decoding datain 9 0 dataout 7 0 control identifier error status 8B 10B Decoder LSByte Decoding ...

Page 332: ... ordered in the MSByte or LSByte position The data is assumed to be received as LSByte first the least significant 8 or 10 bits in single width mode or the least significant 16 or 20 bits in double width mode Table 1 27 Byte Deserializer Input Datapath Width Conversion Receiver Output Datapath Width Byte Deserializer Input Datapath Width Mode 16 8 Single Width 20 10 32 16 Double Width 40 20 Byte D...

Page 333: ...yte deserializer enabled A predefined byte ordering pattern that must be ordered at the LSByte position of the data A predefined pad pattern Byte ordering supports operation in single and double width modes Both modes support operation in word aligner based and manual ordering modes Byte Ordering in Single Width Mode Byte ordering is supported only when you enable the byte deserializer Table 1 28 ...

Page 334: ...of a byte ordering operation in double width mode 16 bit PMA PCS interface width where A1A2 is the predefined byte ordering pattern and P is the predefined pad pattern Byte Serializer Byte Ordering Byte Deserializer datain 31 16 MSByte datain 15 0 LSByte Transmitter Channel Receiver D2D3 D0D1 D4D5 D8D9 D6D7 dataout 31 16 MSByte dataout 15 0 LSByte B1B2 D0D1 xxxx A1A2 D6D7 D4D5 D2D3 D0D1 xxxx PP D4...

Page 335: ... the pattern is in the LSByte position byte ordering indicates the byte alignment Any byte misalignment found thereafter is ignored unless another rising edge on the rx_enabyteord signal is observed Receiver Phase Compensation FIFO The receiver phase compensation FIFO is four words deep and interfaces the status and data signals between the receiver PCS and the FPGA fabric or the PCIe hard IP bloc...

Page 336: ... and control logic generated in the central clock divider resulting in equal latency in the transmitter phase compensation FIFO of all bonded channels The lower transceiver clock skew and equal latency in the transmitter phase compensation FIFOs in all channels provide lower channel to channel skew in bonded channel configurations Non bonded channel configurations the parallel clock in each channe...

Page 337: ... CDR PLL in Automatic Lock Mode section Added the CDR PLL in Manual Lock Mode section Updated the Channel PLL as a CMU PLL section Added the fPLL as a Transmitter PLL section Updated the Clock Divider section Updated the Receiver PMA Datapath section Updated the Receiver Buffer section Updated the Programmable Receiver VCM section Updated the Transmitter PMA Datapath section Added the Bit Reversal...

Page 338: ...Updated the Receiver Phase Compensation FIFO section Updated the Channel Bonding section Updated the PLL Sharing section Clarified note to Figure 1 6 to indicate only certain transceiver channels support interfacing to PCIe Removed DC Coupling information from Transmitter Buffer Features and Capabilities and PMA Receiver Buffer 2012 12 03 December 2012 Reorganized content and updated template 2012...

Page 339: ...ork 3 Yes Yes Dual purpose RX refclk pin 4 Yes Yes Fractional PLL 6 The lower number indicates better jitter performance ISO 9001 2008 Registered 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other wo...

Page 340: ...ference clock to the transmitter PLL and CDR For specifications about the input frequency supported by the refclk pins refer to the Cyclone V Device Datasheet Note As shown in the following figure the dedicated refclk pin direct connection to the channel PLL which can be configured either as a CMU PLL or CDR is only available in channel 1 of a transceiver bank and channel 4 of the neighboring tran...

Page 341: ...same dedicated refclk pin Each dedicated refclk pin can drive any channel PLL CMU PLL CDR and the fractional PLL through the reference clock network Figure 2 2 shows the input reference clock sources for six channel PLLs across two transceiver banks For six transceiver channels the total number of clock lines in the reference clock network is 2 N 6 3 Dual Purpose RX refclk Pins When not used as a ...

Page 342: ...L or CDR The fPLL synthesizes a supported input reference clock for the transmitter PLL or CDR A fPLL is available for each bank of three transceiver channels Each fPLL drives one of two fPLL cascade clock network lines that can provide an input reference clock to any transmitter PLL or CDR on the same side of a device fPLLs support fractional and integer modes The fractional mode allows you to sy...

Page 343: ...tter Clock Network A Clocking architecture within transmitter channel datapath Transmitter Clocking B Clocking architecture within receiver channel datapath Receiver Clocking C Figure 2 5 Internal Clocking Transmit PLL 1 6 Clock Lines N Transmitter Clock Network Transceiver Channel Transmitter A Receiver CDR rx_serial_data tx_serial_data Input Reference Clock Input Reference Clock Transceiver Chan...

Page 344: ...pport non bonded and bonded transceiver clocking configurations Non bonded configuration Only the serial clock from the transmit PLL is routed to the transmitter channel The clock divider of each channel generates the local parallel clock Bonded configuration Both the serial clock and parallel clock are routed from the central clock divider in channel 1 or 4 to the bonded transmitter channels The ...

Page 345: ... of CMU PLLs from channels 1 and 4 The serial clock in the x1 clock line is then distributed to the local and central clock dividers of every channel within both the neighboring transceiver banks When you configure the channel PLL as a CMU PLL to drive the local clock divider or the central clock divider of its own channel you cannot use the channel PLL as a CDR Without a CDR you can use the chann...

Page 346: ...n the same side of the device To reach a xN clock line the clocks must be provided on the x6 clock line The serial and parallel clocks in the x6 clock line are distributed to every channel within the two transceiver banks The serial and parallel clocks are distributed to other channels beyond the two banks or the six channels using the xN clock line In bonded configurations serial and parallel clo...

Page 347: ...ver Figure 2 8 Clocking Architecture for Transmitter PCS and PMA Configuration Transmitter PCS Transmitter PMA FPGA Fabric TX Phase Compensation FIFO Byte Serializer 8B 10B Encoder TX Bit Slip Serializer tx_serial_data tx_parallel_data 2 tx_coreclkin tx_std_coreclkin tx_clkout tx_std_clkout Both Parallel and Serial Clocks Local Central clock divider Serial Clock Parallel Clock Data Path Transmitte...

Page 348: ...dual clock divider serializer 7 CMU x6 xN 7 Non bonded channels within the neighboring two banks or within the six channels of TX PLL are driven by clocks from x6 clock line Channels in other banks outside the 6 channels are driven by the xN clock line Transceiver Clocking in Cyclone V Devices Altera Corporation Send Feedback CV 53002 Non Bonded Channel Configurations 2 10 2013 05 06 ...

Page 349: ...lel and Serial Clocks Serial Clock Channels 0 1 2 Parallel Clock Unused Resources Data Path x1_top TX PCS Ch4 TX PMA Ch4 Central Clock Divider CMU PLL Serializer tx_serial_data Clock Divider TX PCS Ch3 TX PMA Ch3 Local Clock Divider CMU PLL Serializer tx_serial_data Clock Divider Altera Corporation Transceiver Clocking in Cyclone V Devices Send Feedback 2 11 Non Bonded Channel Configurations CV 53...

Page 350: ... Clock Divider CMU PLL Serializer tx_serial_data Clock Divider TX PCS Ch4 TX PMA Ch4 Central Clock Divider CMU PLL Serializer tx_serial_data Clock Divider TX PCS Ch3 TX PMA Ch3 Local Clock Divider CMU PLL Serializer tx_serial_data Clock Divider Bonded Channel Configurations This section describes the clock path for bonded configurations The following table describes the clock path for bonded confi...

Page 351: ...ider xN_top x6_top x6_bot xN_top Channels 0 1 2 TX PCS Ch5 TX PMA Ch5 Local Clock Divider CMU PLL Serializer tx_serial_data Clock Divider TX PCS Ch4 TX PMA Ch4 Central Clock Divider CMU PLL Serializer tx_serial_data Clock Divider TX PCS Ch3 TX PMA Ch3 Local Clock Divider CMU PLL Serializer tx_serial_data Clock Divider 8 Bonded channels within the neighboring two banks or within the six channels of...

Page 352: ...nerates the parallel clock recovered by dividing the serial clock recovered The deserializer uses both clocks The receiver PCS can use the following clocks depending on the configuration of the receiver channel Parallel clock recovered from the CDR in the PMA Parallel clock from the clock divider that is used by the channel s transmitter PCS Table 2 8 Clock Sources for All Receiver PCS Blocks Cloc...

Page 353: ...eceiver clocking in non bonded mode varies depending on whether the rate match FIFO is enabled When the rate match FIFO is not enabled the receiver PCS in every channel uses the parallel recovered clock When the rate match FIFO is enabled the receiver PCS in every channel uses both the parallel recovered clock and parallel clock from the clock divider Altera Corporation Transceiver Clocking in Cyc...

Page 354: ...Clock Lines To Transmitter Channel Parallel Clock from the Clock Divider Parallel Clock Recovered Input Reference Clock From the x6 or xN Clock Lines To Transmitter Channel Parallel Clock from the Clock Divider Parallel Clock Recovered Input Reference Clock From the x6 or xN Clock Lines To Transmitter Channel Parallel Clock from the Clock Divider Parallel Clock Recovered Input Reference Clock Both...

Page 355: ...Channel Parallel Clock from the Clock Divider Parallel Clock Recovered Input Reference Clock Both Parallel and Serial Clocks Serial Clock Parallel Clock Unused Resources Data Path Channels 0 1 2 x1_top Receiver Bonded Channel Configurations Receiver channels can only be bonded in configurations where rate match FIFOs are enabled When bonded the receiver PCS requires the parallel clock recovered an...

Page 356: ...ivider Parallel Clock Recovered Input Reference Clock From the x1 Clock Lines To Transmitter Channel Parallel Clock from the Clock Divider Parallel Clock Recovered Input Reference Clock From the x1 Clock Lines To Transmitter Channel Parallel Clock from the Clock Divider Parallel Clock Recovered Input Reference Clock From the x1 Clock Lines To Transmitter Channel Parallel Clock from the Clock Divid...

Page 357: ...en the FPGA fabric and the transceiver channels The transceiver channel forwards the tx_clkout signal to the FPGA fabric to clock the data and control signals into the transmitter The transceiver channel also forwards the recovered rx_clkout clock in configurations without the rate matcher or the tx_clkout clock in configurations with the rate matcher to the FPGA fabric to clock the data and statu...

Page 358: ...x_pma_clkout FPGA fabric to transceiver User selected clock for clocking the transmitter datapath interface tx_coreclkin User selected clock for clocking the receiver datapath interface rx_coreclkin PCIe receiver detect clock fixed_clk Avalon MM interface management clock mgmt_clk 9 For more information about the GCLK RCLK and PCLK resources available in each device refer to the Clock Networks and...

Page 359: ...ng clocks to the FPGA fabric tx_clkout for each transmitter channel in a non bonded configuration tx_clkout 0 for all transmitter channels in a bonded configuration Figure 2 16 Transmitter Datapath Interface Clocking for Transceivers TX Phase Compensation FIFO tx_coreclkin User Selected Clock tx_clkout Transmitter Data Transmitter Data Parallel Clock FPGA Fabric Transmitter PCS tx_clkout Quartus I...

Page 360: ...face Clocking for Non Bonded Channels TX Phase Compensation FIFO tx_coreclkin 0 Parallel Clock Transmitter Data FPGA Fabric Channel 1 Channel 0 tx_clkout 0 TX Phase Compensation FIFO tx_coreclkin 1 Parallel Clock Transmitter Data Transmitter Data Transmitter Data tx_clkout 1 Channel 1 Transmitter Data and Control Logic Channel 0 Transmitter Data and Control Logic The following figure shows the tra...

Page 361: ...nels saves clock resources Multiple transmitter channels that are non bonded lead to high utilization of GCLK RCLK and PCLK resources one clock resource per channel You can significantly reduce GCLK RCLK and PCLK resource use for transmitter datapath clocks if the transmitter channels are identical Identical transmitter channels have the same input reference clock source transmit PLL configuration...

Page 362: ... all six channels Note The common clock must have a 0 ppm difference for the read side of the transmitter phase compensation FIFO of all the identical channels A frequency difference causes the FIFO to under run or overflow depending on whether the common clock is slower or faster respectively You can drive the 0 ppm common clock by one of the following sources tx_clkout of any channel in non bond...

Page 363: ...about interface clocking for each configuration refer to the Transceiver Custom Configuration in Cyclone V Devices and Transceiver Protocol Configurations in Cyclone V Devices chapters Note You can clock the receiver datapath interface with one of the following options The Quartus II selected receiver datapath interface clock The user selected receiver datapath interface clock To reduce GCLK RCLK ...

Page 364: ...m the central clock divider of channel 1 or 4 of the two transceiver banks Figure 2 22 Receiver Datapath Interface Clocking for Three Bonded Channels RX Phase Compensation FIFO rx_coreclkin 1 Receiver Data FPGA Fabric Channel 2 Channel 1 Channel 0 rx_clkout 0 RX Phase Compensation FIFO rx_coreclkin 2 Parallel Clock Recovered Clock Parallel Clock Recovered Clock Parallel Clock Recovered Clock Recei...

Page 365: ...tting Note To achieve clock resource savings select a common clock driver for the receiver datapath interface of all identical receiver channels To select a common clock driver perform these steps 1 Instantiate the rx_coreclkin port for all the identical receiver channels 2 Connect the common clock driver to their receiver datapath interface and receiver data and control logic The following figure...

Page 366: ...he rate matcher tx_clkout 0 in bonded receiver channel configurations Dedicated refclk pins The Quartus II software does not allow gated clocks or clocks generated in the FPGA logic to drive the rx_coreclkin ports Note You must ensure a 0 ppm difference The Quartus II software is unable to ensure a 0 ppm difference because it allows you to use external pins such as dedicated refclk pins Note Docum...

Page 367: ...sceiver reconfiguration controller before or at the same time as phy_mgmt_clk_reset to start calibration Note The PHY IP embedded reset controller is enabled by default in all transceiver PHY IP cores except the Native PHY IP core Note Embedded Reset Controller Signals The following figure shows the embedded reset controller and signals in the PHY IP instance These signals reset your transceiver w...

Page 368: ...ol and Status Signals Description Signal Signal Name Clock for the embedded reset controller Control Input phy_mgmt_clk A high to low transition of this asynchronous reset signal initiates the automatic reset sequence control Hold this signal high to keep the reset signals asserted Control Input phy_mgmt_clk_reset A continuous high on this signal indicates that the transmitter TX channel is out of...

Page 369: ...t the CDR is locked to the reference clock Status Output rx_is_lockedtoref Clock for the Transceiver Reconfiguration Controller This clock must be stable before releasing mgmt_ rst_reset Clock mgmt_clk_clk Reset for the Transceiver Reconfiguration Controller Reset mgmt_rst_reset Resetting the Transceiver with the PHY IP Embedded Reset Controller during Device Power Up Follow this reset sequence to...

Page 370: ...or after certain dynamic reconfigurations The numbers in the following figure correspond to the numbered list which guides you through the transceiver reset sequence during device operation 1 Assert phy_mgmt_clk_reset for two phy_mgmt_clk clock cycles to re start the entire transceiver reset sequence 2 After the transmitter reset sequence is complete the tx_ready status signal is asserted and rema...

Page 371: ...ch provides a ready made reset controller IP to place your own verilog vhdl code You must disable the embedded reset controller before using the user coded reset controller Note The embedded reset controller can only be disabled for non protocol transceiver PHY IPs such as custom PHY low latency PHY and deterministic latency PHY Native PHY IP does not have an embedded reset controller so you must ...

Page 372: ...PCS tx_analogreset Transmitter PLL Table 3 2 Signals Used by the Transceiver PHY instance Transceiver Reconfiguration Controller and User Coded Reset Controller Description Signal Type Signal Name Clock for the Transceiver Reconfiguration Controller This clock must be stable before releasing mgmt_ rst_reset Clock mgmt_clk_clk Reset for the Transceiver Reconfiguration Controller Reset mgmt_rst_rese...

Page 373: ...e calibration IPs Hold mgmt_rst_reset active for a minimum of two reset controller clock cycles Assert and hold pll_powerdown tx_analogreset and tx_digitalreset at power up to reset the transmitter You can deassert tx_analogreset at the same time as pll_powerdown 2 After the transmitter PLL locks the pll_locked status gets asserted after tpll_lock 3 After the transmitter calibration completes the ...

Page 374: ...hing a link or after certain dynamic reconfigurations The numbers in the following figure correspond to the following numbered list which guides you through the transmitter reset sequence during device operation 1 To reset the transmitter Assert pll_powerdown tx_analogreset and tx_digitalreset tx_digitalreset must be asserted every time pll_powerdown and tx_analogreset are asserted to reset the PC...

Page 375: ...active at power up to hold the receiver in reset You can deassert them after all the gating conditions are removed 2 After the receiver calibration completes the rx_cal_busy status is de asserted 3 Deassertrx_analogresetafteraminimumdurationoftrx_analogreset afterrx_cal_busyisdeasserted 4 rx_is_lockedtodata is a status signal from the receiver CDR indicating that the CDR is in the lock to data LTD...

Page 376: ...spond to the following numbered list which guides you through the receiver reset sequence during device operation 1 Assert rx_analogreset and rx_digitalreset at any point independently However you must assert rx_digitalreset every time rx_analogreset is asserted to reset the PCS blocks 2 Deassert rx_analogreset after a minimum duration of 40 ns trx_analogreset 3 rx_is_lockedtodata is a status sign...

Page 377: ...ng Avalon Memory Map Registers The following table lists the memory map registers for CDR lock mode and channel reset These signals help you reset your transceiver when you use Memory Map registers within the PHY IP Table 3 4 Transceiver Reset Control Using Memory Map Registers Description Register Name This register is for CDR manual lock mode only When you set the register to high the RX CDR PLL...

Page 378: ...e certain channels in a PHY IP instance for reset control By default all channels in a PHY IP instance are enabled for reset control reset_ch_bitmask When asserted the TX phase locked loop PLL is turned off pll_powerdown Related Information Altera Transceiver PHY IP Core User Guide For information about register addresses Clock Data Recovery Manual Lock Mode Reset Sequence Use the clock data recov...

Page 379: ...ignal gets de asserted 4 Assert the rx_set_locktodata signal high after tLTR_LTD_manual to switch the CDR to the lock to data mode The rx_is_lockedtodata status signal gets asserted when it acquires lock to the data The rx_is_lockedtoref status signal can be a high or low and can be ignored 5 Deassert the rx_digitalreset signal after tLTD_Manual 6 After the rx_digitalreset signal is de asserted th...

Page 380: ...roller blocks must not be in the reset state during TX DCD calibration Ensure the following signals are not asserted during TX DCD calibration pll_powerdown tx_digitalreset tx_analogreset mgmt_rst_reset Note Repeat the reset sequence when TX DCD calibration is complete Transceiver Blocks Affected by the Reset and Powerdown Signals The following table lists blocks that are affected by specific rese...

Page 381: ...ll channels on a side of the device where you do not use the transceivers The hard power down granularity control of the transceiver PMA is per side To enable PMA hard power down on the left or right side of the device ground the transceiver power supply of the respective side Related Information Cyclone V Device Datasheet For information about the transceiver power supply operating conditions of ...

Page 382: ...rganized content and updated template Updated reset sequence procedures Included sequences for resetting transceiver during device operation 2012 11 19 November 2012 Added User Controlled Reset Controller section Updated Figure 3 1 and Table 3 1 1 1 November 2011 Initial release 1 0 August 2011 Transceiver Reset Control in Cyclone V Devices Altera Corporation Send Feedback CV 53003 Document Revisi...

Page 383: ...cy 0 6144 1 2288 2 4576 3 072 4 9152 6 144 11 Common Public Radio Interface CPRI 10 The 0 27 gigabits per second Gbps data rate is supported using oversampling user logic that must be implemented by the user in the FPGA core 11 Cyclone V GT devices support data rates greater than 5 0 Gbps only in CPRI ISO 9001 2008 Registered 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOP...

Page 384: ...nd transaction layers The PCIe Hard IP supports the PCIe Gen1 end point and root port up to x4 lane configurations The PCIe endpoint support includes multifunction support for up to eight functions and Gen2 x4 lane configurations Figure 4 1 PCIe Multifunction for Cyclone V Devices FPGA Device PCIe Link Host CPU Memory Controller Root Complex Local Peripheral 1 Local Peripheral 2 PCIe RP PCIe EP CA...

Page 385: ...ne PCS Hard IP Interface Frequency 10 Bit Automatic Synchronization State Machine K28 5 K28 5 Enabled Functional Mode PCIe HIP Enabled Disabled 8 Bit Gen1 250 MHz Gen2 500 MHz Enabled 2 5 for Gen1 x1 x2 x4 5 for Gen2 Refer to the Cyclone V Device Datasheet for the mgmt_clk_clk frequency specification when PCIe HIP is used Note Altera Corporation Transceiver Protocol Configurations in Cyclone V Dev...

Page 386: ...l Clocks CMU PLL 2 2 Byte Serializer PCIe hard IP pipe_pclk pipe_txdata pipe_rxdata Related Information Transceiver Architecture in Cyclone V Devices Cyclone V Device Datasheet PCIe Supported Features The PIPE configuration for the 2 5 Gbps Gen1 and 5 Gbps Gen2 data rates supports these features PCIe compliant synchronization state machine x1 and x4 link configurations 300 parts per million ppm to...

Page 387: ...CIe Base Specification 2 1 for the PCIe Gen2 data rate The PCIe specification requires that the transmitter buffer be placed in electrical idle in certain power states Power State Management The PCIe specification defines four power states P0 P0s P1 and P2 The physical layer device must support these power states to minimize power consumption P0 is the normal operating state during which packet da...

Page 388: ...operation that you must drive on the fixedclk port For the receiver detect circuitry to function reliably the AC coupling capacitor on the serial link and the receiver termination values used in your system must be compliant with the PCIe Base Specification 2 1 Note The PCI Express PHY PIPE IP core provides a 1 bit PHY status pipe_phystatus and a 3 bit receiver status signal pipe_rxstatus 2 0 to i...

Page 389: ...d Serial Clocks CMU PLL 2 2 Byte Serializer PCIe hard IP pipe_pclk pipe_txdata pipe_rxdata PCIe Supported Configurations and Placement Guidelines Placement by the Quartus II software may vary with design and device The following figures show examples of transceiver channel and PCIe Hard IP block locations supported x1 x2 and x4 bonding configurations and channel placement guidelines The Quartus II...

Page 390: ... Master Ch3 Ch4 Ch2 Ch1 Ch0 Figure 4 6 12 Transceiver Channels and 2 PCIe HIP Blocks with PCIe x1 Channel Placement Transceiver Bank Transceiver Bank PCIe x1 PCIe x1 PCIe Hard IP PCIe Hard IP Ch5 CMU PLL Master CMU PLL Ch3 Ch4 Ch2 Ch1 Ch0 Ch5 Master Ch3 Ch4 Ch2 Ch1 Ch0 Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback CV 53004 PCIe Supported Configurations a...

Page 391: ... Ch0 Ch5 Master Ch3 Ch4 Ch2 Ch1 Ch0 PCIe x2 Figure 4 8 9 Transceiver Channels and 2 PCIe HIP Blocks with PCIe x1 Channel Placement Transceiver Bank Transceiver Bank PCIe x1 PCIe x1 PCIe Hard IP PCIe Hard IP CMU PLL CMU PLL Ch2 Ch1 Ch0 Ch5 Master Master Ch3 Ch4 Ch2 Ch1 Ch0 Altera Corporation Transceiver Protocol Configurations in Cyclone V Devices Send Feedback 4 9 PCIe Supported Configurations and...

Page 392: ... PCIe Hard IP CMU PLL Ch5 Master Ch3 Ch4 Ch2 Ch1 Ch0 PCIe x1 PCIe Hard IP PCIe Hard IP OR Transceiver Bank CMU PLL Ch5 Master Ch3 Ch4 Ch2 Ch1 Ch0 Figure 4 11 3 Transceiver Channels and 1 PCIe HIP Blocks with PCIe x1 Channel Placement Transceiver Bank PCIe x1 PCIe Hard IP CMU PLL Ch2 Ch1 Ch0 Master For PCIe Gen1 and Gen2 there are restrictions on the achievable x1 and x4 bonding configurations if y...

Page 393: ...e V GT or Cyclone V ST device variants Table 4 3 Recommended Channel Placement for PCIe Gen2 CMU channels are not counted as data channels Maximum Channels Utilization Device 6 5CGTD7F672 5CGTD7F896 5CGTD9F672 5CSTD5F896 5CSTD6F896 8 5CGTD9F896 5CGTD9F1152 Related Information Transceiver Architecture in Cyclone V Devices Gigabit Ethernet The IEEE 802 3 specification defines the 1000BASE X PHY as a...

Page 394: ...ication 8B 10B encoding and decoding Synchronization Upstream transmitter and local receiver clock frequency compensation rate matching Clock recovery from the encoded data forwarded by the receiver PMD Serialization and deserialization The transceivers do not have built in support for other PCS functions such as the autonegotiation state machine collision detect and carrier sense functions If you...

Page 395: ...t K28 5 156 25 Enabled 16 bit Disabled Enabled Gigabit Ethernet Transceiver Datapath Figure 4 14 Transceiver Datapath in GbE 1 25 Gbps Configuration FPGA Fabric tx_coreclk 0 rx_coreclk 0 tx_clkout 0 Transmitter Channel PCS Transmitter Channel PMA Receiver Channel PCS Receiver Channel PMA High Speed Serial Clock Low Speed Parallel Clock Parallel Recovered Clock Low Speed Parallel Clock FPGA Fabric ...

Page 396: ...and generates 10 bit encoded data The 10 bit encoded data is fed to the serializer For more information about the 8B 10B encoder functionality refer to the Transceiver Architecture for Cyclone V Devices chapter Rate Match FIFO In GbE configuration the rate match FIFO is capable of compensating for up to 100 ppm 200 ppm total difference between the upstream transmitter and the local receiver refere...

Page 397: ...ernating C1 and C2 Configuration C K28 5 D21 5 Config_Reg 12 4 Configuration 1 C1 K28 5 D2 2 Config_Reg 4 Configuration 2 C2 Correcting I1 Preserving I2 IDLE I K28 5 D5 6 2 IDLE 1 I1 K28 5 D16 2 2 IDLE 2 I2 Encapsulation K23 7 1 Carrier_Extend R K27 7 1 Start_of_Packet S K29 7 1 End_of_Packet T K30 7 1 Error_Propagation V Table 4 6 Synchronization State Machine Parameters in GbE Mode Setting Synch...

Page 398: ...even SUDI good_cgs 0 rx_even rx_even SUDI good_cgs 0 rx_even rx_even SUDI good_cgs good_cgs 1 rx_even rx_even SUDI good_cgs good_cgs 1 PUDI D PUDI COMMA INVALID rx_even FALSE PUDI COMMA PUDI COMMA INVALID rx_even FALSE PUDI COMMA cggood good_cgs 3 cggood good_cgs 3 cggood good_cgs 3 good_cgs 3 cggood cggood good_cgs 3 cggood good_cgs 3 cgbad 2 3 Related Information Refer to the Custom PHY IP Core ...

Page 399: ...conciliation Media Access Control MAC PCS 10 Gigabit Media Independent Interface XGMII Extender Sublayer XGMII Extender Sublayer 10 Gigabit Attachment Unit Interface 10 Gigabit Media Independent Interface Medium Dependent Interface Related Information Refer to the XAUI PHY IP Core chapter in the Altera Transceiver PHY IP Core User Guide Transceiver Datapath in a XAUI Configuration The XAUI PCS is ...

Page 400: ... 1 Note 1 Implemented in soft logic FPGA Fabric to Transceiver Interface Width FPGA Fabric to Transceiver Interface Frequency 10 Bit K28 5 10 Bit XAUI PHY IP 3 125 Gbps 4 Enabled 8B 10B Encoder Decoder 1 Enabled 156 25 MHz Enabled 16 Bit Disabled Enabled Transceiver Protocol Configurations in Cyclone V Devices Altera Corporation Send Feedback CV 53004 Transceiver Datapath in a XAUI Configuration 4...

Page 401: ...CS Soft PCS Soft PCS Soft PCS FPGA Fabric Channel 3 Channel 2 Channel 1 Channel 0 XAUI Supported Features 64 Bit SDR Interface to the MAC RS Clause 46 of the IEEE 802 3 2008 specification defines the XGMII interface between the XAUI PCS and the Ethernet MAC RS The specification requires each of the four XAUI lanes to transfer 8 bit data and 1 bit wide control code at both the positive and negative...

Page 402: ... to the incoming data The XAUI PHY IP core provides status signals to indicate running disparity as well as the 8B 10B code group error Transmitter and Receiver State Machines In a XAUI configuration the Cyclone V soft PCS implements the transmitter and receiver state diagrams shown in Figure 48 6 and Figure 48 9 of the IEEE802 3 2008 specification In addition to encoding the XGMII data to PCS cod...

Page 403: ...valid word boundary The XAUI PHY IP core provides a status signal to indicate successful lane deskew in the receiver PCS Clock Compensation The rate match FIFO in the receiver PCS datapath compensates up to 100 ppm difference between the remote transmitter and the local receiver It does so by inserting and deleting Skip R columns depending on the ppm difference The clock compensation operation beg...

Page 404: ...ric Channel 3 Channel 2 Channel 1 Channel 0 16 16 20 20 20 20 10 10 xgmii_tx_clk xgmii_rx_clk 2 Parallel Clock Recovered from Channel 0 Parallel Clock 2 Clock Divider Parallel and Serial Clocks From the 6 or N Clock Lines Serial Clock From the 1 Clock Lines Central Local Clock Divider Parallel Clock Serial Clock Parallel and Serial Clocks CMU PLL Table 4 7 Input Reference Clock Frequency and Inter...

Page 405: ...GA Fabric Channel 3 Channel 2 Channel 1 Channel 0 16 16 20 20 20 20 10 10 xgmii_tx_clk xgmii_rx_clk 2 Parallel Clock Recovered from Channel 0 Parallel Clock 2 Clock Divider Parallel and Serial Clocks From the 6 or N Clock Lines Serial Clock From the 1 Clock Lines Central Local Clock Divider Parallel Clock Serial Clock Parallel and Serial Clocks CMU PLL Transceiver Channel Placement Guidelines In t...

Page 406: ...Y IP Core chapter in the Altera Transceiver PHY IP Core User Guide Serial Digital Interface The Society of Motion Picture and Television Engineers SMPTE defines various Serial Digital Interface SDI standards for transmission of uncompressed video The following SMPTE standards are popular in video broadcasting applications SMPTE 259M standard more popularly known as the standard definition SD SDI d...

Page 407: ...f Bonded Channels Low Latency PCS 8B 10B Encoder Decoder Rate Match FIFO Byte SERDES Byte Ordering FPGA Fabric Transceiver Interface Width FPGA Fabric Transceiver Interface Frequency MHz Disabled SDI PMA PCS Interface Width 10 bit HD SDI 1 485 1 4835 3G SDI 2 97 2 967 x1 Disabled Word Aligner Pattern Length Bit Slip Bit Slip 148 5 148 35 Disabled 10 bit Disabled 74 25 74 175 Enabled 20 bit Disable...

Page 408: ...c redundancy check CRC code generation in the FPGA logic array Note Receiver Datapath In the 10 bit channel width SDI configuration the receiver datapath consists of the clock recovery unit CRU 1 10 deserializer word aligner in bit slip mode and receiver phase compensation FIFO In the 20 bit channel width SDI configuration the receiver datapath also includes the byte deserializer You must implemen...

Page 409: ...e Width 10 bit PMA PCS Interface Width Configuration option for data rate range of 312 5 Mbps 1 5625 Gbps Configuration option for data rate range of 1 5625 Gbps 3 125 Gpbs 78 125 156 25 Enabled 16 bit Enabled Disabled 10 bit Single Width Single Width SATA and SAS Protocols Serial ATA SATA and Serial Attached SCSI SAS are data storage protocol standards that have the primary function of transferri...

Page 410: ...it PMA PCS Interface Width 150 Disabled Enabled Disabled Enabled 1 5 Disabled 75 150 Disabled Disabled 16 Bit 8 Bit Cyclone V Configurations Basic 10 Bit Configuration Option for SATA SAS 3 0 Gbps Data Rate Configuration Option for SATA SAS 1 5 Gbps Data Rate Enabled Manual 10 Bit x1 Basic Single Width 10 Bit PMA PCS Interface Width Disabled Enabled Disabled Enabled 3 0 Disabled 150 150 16 Bit Ena...

Page 411: ...moves the uncertainty in latency The latency through the transmitter and receiver phase compensation FIFO in register mode is one clock cycle The following options are available Single width mode with 8 bit channel width and 8B 10B encoder enabled or 10 bit channel width with 8B 10B disabled Double width mode with 16 bit channel width and 8B 10B encoder enabled or 20 bit channel width with 8B 10B ...

Page 412: ...res that the accuracy of measurement of roundtrip delay on single hop and multi hop connections be within 16 276 ns to properly estimate the cable delay For a single hop system this allows a variation in roundtrip delay of up to 16 276 ns However for multi hop systems the allowed delay variation is divided among the number of hops in the connection typically equal to 16 276 ns the number of hops b...

Page 413: ...No 3072 Yes No No No 4915 2 Yes No No No 6144 13 6 144 Gbps Support Capability in Cyclone V GT Devices Cyclone V GT devices support a 6 144 Gbps data rate for the CPRI protocol only For CPRI 6 144 Gbps transmit jitter compliance Altera recommends you use only up to three full duplex channels for every two transceiver banks The transceivers are grouped in banks of three channels For transceiver ban...

Page 414: ...ion based on the following figure Figure 4 31 6 144 Gbps CPRI Channel Placement Restriction The channels next to a PCIe Hard IP block are not timing optimized for the 6 144 Gbps CPRI data rate Affected channels are shaded in gray in the above figure Avoid placing the 6 144 Gbps CPRI channels in the affected channels The affected channels can still be used as a CMU for the CPRI channels Related Inf...

Page 415: ...s to Achieve Deterministic Latency Mode in Cyclone V Devices Enhanced Feature 14 Existing Feature Requirement Description Requirement Description None Deterministic latency state machine alignment reduces the knowndelayvariation in word alignment operation Extra user logic to manipulate the TX bit slipper with a bit position indicator from the word aligner for constant total round trip delay Manua...

Page 416: ...n the Knowledge Base Removed the Receiver Electrical Idle Inference section Added the Recommended Channel Placement for PCIe Gen2 table Updated the figures in the PCIe Supported Configurations and Placement Guidelines section Added the Transceiver Clocking Guidelines for Soft PCS Implementation section Added the 6 Gbps Support Capability in Cyclone V GT Devices section 2013 05 06 May 2013 Reorgani...

Page 417: ...igabit Ethernet section Added the Serial Digital Interface section Added the Serial Data Converter SDC JESD204 section Added the SATA and SAS Protocols section 1 1 June 2012 Initial release 1 0 October 2011 Altera Corporation Transceiver Protocol Configurations in Cyclone V Devices Send Feedback 4 35 Document Revision History CV 53004 2013 10 17 ...

Page 418: ...nctions that your application requires The transceiver channel interfaces with the FPGA fabric through the PCS ISO 9001 2008 Registered 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and lo...

Page 419: ...tion The supported interface width varies depending on the usage of the byte serializer deserializer SERDES and the 8B 10B encoder or decoder The byte serializer or deserializer is assumed to be enabled Otherwise the maximum data rate supported is half of the specified value The maximum supported data rate varies depending on the customization Table 5 1 Maximum Supported Data Rate The following ta...

Page 420: ...isabled are not used but incur latency The blocks shown as Bypassed are not used and do not incur any latency The transmitter bit slip is disabled Figure 5 3 Configuration Options for Custom Single Width Mode 8 bit PMA PCS Interface Width Word Aligner Pattern Length 8B 10B Encoder Decoder Rate Match FIFO Byte SERDES Disabled Disabled Enabled Manual Alignment or Bit Slip Disabled FPGA Fabric Transc...

Page 421: ...h 10 Bit 20 Bit 8 Bit 16 Bit 8 Bit 16 Bit 10 Bit 20 Bit Data Rate Gbps 1 875 GX SX 3 125 GT ST 3 75 GX SX 3 125 GT ST 3 75 1 875 3 125 1 875 3 125 1 875 Figure 5 5 Configuration Options for Custom Double Width Mode 16 bit PMA PCS Interface Width Word Aligner Pattern Length 8B 10B Encoder Decoder Rate Match FIFO Byte SERDES Disabled Disabled Enabled Manual Alignment or Bit Slip Disabled FPGA Fabric...

Page 422: ...given parts per million ppm difference between the clocks The rate match FIFO operation requires 8B 10B coded data Rate Match FIFO Behaviors in Custom Single Width Mode The different operations available in custom single width mode for the rate match FIFO are symbol insertion symbol deletion full condition and empty condition Table 5 2 Rate Match FIFO Behaviors in Custom Single Width Mode 10 bit P...

Page 423: ... the pair 20 bit word of data bytes that causes the FIFO to go full Full Condition Inserts a pair of K30 7 9 h1FE 9 h1FE after the data byte that causes the FIFO to go empty Empty Condition Standard PCS in Low Latency Configuration In this configuration you can customize the transceiver channel to include a PMA and PCS that bypasses most of the PCS logical functionality for a low latency datapath ...

Page 424: ...The serial and parallel clocks are sourced from the clock divider The maximum supported data rate varies depending on the customization and is identical to the custom configuration except that the 8B 10B block is disabled Low Latency Custom Configuration Channel Options There are multiple channel options when you use Low Latency Custom Configuration In the following figures The blocks shown as Dis...

Page 425: ... 1 5 3 0 Figure 5 9 Configuration Options for Low Latency Custom Single Width Mode 10 bit PMA PCS Interface Width Word Aligner Pattern Length 8B 10B Encoder Decoder Rate Match FIFO Byte SERDES Byte Ordering FPGA Fabric Transceiver Interface Width Disabled Disabled Bypassed Bypassed Bypassed 10 Bit Bypassed Enabled 20 Bit Data Rate Gbps 1 875 GX SX 3 125 GT ST 3 75 Transceiver Custom Configurations...

Page 426: ...125 GT ST 5 Figure 5 11 Configuration Options for Low Latency Custom Double Width Mode 20 bit PMA PCS Interface Width Word Aligner Pattern Length 8B 10B Encoder Decoder Rate Match FIFO Byte SERDES Byte Ordering FPGA Fabric Transceiver Interface Width Disabled Disabled Bypassed Bypassed Bypassed 20 Bit Bypassed Enabled 40 Bit Data Rate Gbps GX SX 3 125 GT ST 5 GX SX 3 125 GT ST 3 2768 Altera Corpor...

Page 427: ...dge Base 2013 05 06 May 2013 Reorganized content and updated template 2012 11 19 November 2012 Updated for the Quartus II software version 12 0 release 1 1 June 2012 Initial release 1 0 October 2011 Transceiver Custom Configurations in Cyclone V Devices Altera Corporation Send Feedback CV 53005 Document Revision History 5 10 2013 05 06 ...

Page 428: ... Decoder Rate Match FIFO Word Aligner Deserializer CDR TX Phase Compensation FIFO Byte Serializer 8B 10B Encoder TX Bit Slip Serializer rx_serial_data tx_serial_data When you enable serial loopback the transmitter channel sends data to both the tx_serial_data output port and to the receiver channel The differential output voltage on the tx_serial_data port is based on the selected differential out...

Page 429: ... Related Information Altera Transceiver PHY IP Core User Guide Forward Parallel Loopback Forward parallel loopback is a debugging aid to ensure the enabled PCS blocks in the transmitter and receiver channel function correctly Forward parallel loopback is only available in transceiver Native PHY You enable forward parallel loopback by enabling the PRBS test mode through the dynamic reconfiguration ...

Page 430: ...lel loopback is enabled Transmitter PMA Receiver PMA Receiver PCS FPGA Fabric PIPE Interface Byte Ordering RX Phase Compensation FIFO rx_parallel_data Byte Deserializer 8B 10B Decoder Rate Match FIFO Word Aligner Deserializer CDR TX Phase Compensation FIFO Byte Serializer 8B 10B Encoder TX Bit Slip Serializer rx_serial_data tx_serial_data Reverse Parallel Loopback Path PCI Express Hard IP Reverse ...

Page 431: ... data path through the rx_serial_data port to the tx_serial_data port and before the receiver CDR You can enable reverse serial pre CDR loopback through the reconfiguration controller For further details refer to the Altera Transceiver PHY IP Core User Guide Note In reverse serial pre CDR loopback the data received through the rx_serial_data port is looped back to the tx_serial_data port before th...

Page 432: ... Related Information Altera Transceiver PHY IP Core User Guide Document Revision History The table below lists the revision history for this chapter Table 6 1 Document Revision History Changes Version Date Added the Forward Parallel Loopback topic Updated the Reverse Serial Loopback topic Updated the Reverse Serial Pre CDR Loopback topic Added link to the known document issues in the Knowledge Bas...

Page 433: ...itter TX and receiver RX analog settings while bringing up a link Analog Controls Reconfiguration PMA Enable or disable Pre and Post CDR Reverse Serial Loopback dynamically Loopback Modes ISO 9001 2008 Registered 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the ...

Page 434: ... to compensate for the offset variations that are caused by process operations The offset cancellation circuitry is controlled by the offset cancellation control logic IP within the Transceiver Reconfiguration Controller Resetting the Transceiver Reconfiguration Controller during user mode does not trigger the offset cancellation process When offset cancellation calibration is complete the reconfi...

Page 435: ... and offset cancellation are enabled the reconfig_busy status signal from the reconfiguration controller is deasserted to indicate the completion of both processes If DCD calibration is not enabled the deassertion of reconfig_busy signal indicates the completion of the offset cancellation process Related Information AN 676 Using the Transceiver Reconfiguration Controller for Dynamic Reconfiguratio...

Page 436: ... quality of the RX and TX buffers Enabling or disabling the pre CDR reverse serial loopback mode Serial loopback can be implemented with the transceiver PHY IP directly using the Avalon interface or a control port Note Related Information Transceiver Reconfiguration Controller chapter of the Altera Transceiver PHY IP Core User Guide Transceiver Loopback Support in Cyclone V Devices Transceiver PLL...

Page 437: ...S interfaces For example you can reconfigure the custom PHY IP to enable or disable the 8B 10B encoder decoder There is no limit to the number of functional modes you can reconfigure the transceiver channel to if the various clocks involved support the transition When you switch the custom PHY IP from one function mode to a different function mode you may need to reconfigure the FPGA fabric transc...

Page 438: ...figuration Reduced mif Reconfiguration Reduce reconfiguration time by reconfiguring only the affected blocks in the transceiver channels This reconfiguration mode affects only the modified settings of the channel to reduce reconfiguration time significantly For example in SATA SAS applications auto rate negotiation must be completed within a short period of time to meet the protocol specification ...

Page 439: ...and a custom proprietary IP mode also configured using Native PHY IP you can reconfigure these two modes within the Native PHY IP The switching refers to enabling and disabling the PCS sub blocks for both SDI and the custom proprietary IP mode Document Revision History Changes Version Date Updated TX DCD calibration information Included link AN 661 for fPLL reconfiguration Added link to the known ...

Page 440: ...Cyclone V Device Handbook Volume 3 Hard Processor System Technical Reference Manual 101 Innovation Drive San Jose CA 95134 www altera com cv_5v4 2013 12 30 Subscribe Send Feedback ...

Page 441: ... Clock Manager 2 1 Features of the Clock Manager 2 1 Clock Manager Block Diagram and System Integration 2 2 Functional Description of the Clock Manager 2 3 Clock Manager Building Blocks 2 3 Hardware Managed and Software Managed Clocks 2 5 Clock Groups 2 5 Flash Controller Clocks 2 14 Resets 2 15 Safe Mode 2 16 Interrupts 2 16 Clock Usage By Module 2 16 Clock Manager Address Map and Register Defini...

Page 442: ...aves 4 4 L4 Slaves 4 6 Functional Description of the Interconnect 4 7 Master to Slave Connectivity Matrix 4 7 Address Remapping 4 9 Master Caching and Buffering Overrides 4 12 Security 4 13 Arbitration 4 13 Cyclic Dependency Avoidance Schemes 4 13 Interconnect Master Properties 4 14 Interconnect Slave Properties 4 15 Upsizing Data Width Function 4 17 Downsizing Data Width Function 4 18 Lock Suppor...

Page 443: ... MPU Subsystem Components 6 4 Cortex A9 MPCore 6 4 ACP ID Mapper 6 24 L2 Cache 6 28 Debugging Modules 6 33 Cortex A9 MPU Subsystem Register Implementation 6 34 Document Revision History 6 35 CoreSight Debug and Trace 7 1 Features of CoreSight Debug and Trace 7 1 ARM CoreSight Documentation 7 2 CoreSight Debug and Trace Block Diagram and System Integration 7 3 Functional Description of CoreSight De...

Page 444: ...m Interfaces 8 2 Memory Controller Architecture 8 4 Multi Port Front End 8 5 SinglePort Controller 8 6 Functional Description of the SDRAM Controller Subsystem 8 7 MPFE Operation Ordering 8 7 MPFE Multiport Scheduling 8 7 MPFE SDRAM Burst Scheduling 8 8 SinglePort SDRAM Controller Operational Behavior 8 9 Command and Data Reordering 8 9 Bank Policy 8 9 Write Combining 8 10 Burst Length Support 8 1...

Page 445: ...ontroller Address Map and Register Definitions 8 33 Document Revision History 8 33 On Chip Memory 9 1 On Chip RAM 9 1 Features of the On Chip RAM 9 1 On Chip RAM Block Diagram and System Integration 9 2 Functional Description of the On Chip RAM 9 2 Boot ROM 9 3 Features of the Boot ROM 9 3 Boot ROM Block Diagram and System Integration 9 3 Functional Description of the Boot ROM 9 3 On Chip Memory A...

Page 446: ...on 11 3 Functional Description of the SD MMC Controller 11 3 SD MMC CE ATA Protocol 11 4 BIU 11 4 CIU 11 14 Clocks 11 27 Resets 11 29 Interface Signals 11 29 SD MMC Controller Programming Model 11 29 Initialization 11 29 Controller DMA FIFO Buffer Reset Usage 11 35 Enabling FIFO Buffer ECC 11 35 Data Transfer Commands 11 37 Transfer Stop and Abort Commands 11 44 Internal DMA Controller Operations ...

Page 447: ... 11 Data Slave Sequential Access Detection 12 11 Clocks 12 11 Resets 12 11 Interrupts 12 12 Interface Signals 12 13 Quad SPI Flash Controller Programming Model 12 14 Setting Up the Quad SPI Flash Controller 12 14 Indirect Read Operation with DMA Disabled 12 14 Indirect Read Operation with DMA Enabled 12 15 Indirect Write Operation with DMA Disabled 12 15 Indirect Write Operation with DMA Enabled 1...

Page 448: ...s Map and Register Definitions 14 8 Document Revision History 14 8 Scan Manager 15 1 Features of the Scan Manager 15 1 Scan Manager Block Diagram and System Integration 15 2 Functional Description of the Scan Manager 15 5 Configuring HPS I O Scan Chains 15 5 Communicating with the JTAG TAP Controller 15 6 JTAG AP FIFO Buffer Access and Byte Command Protocol 15 6 Clocks 15 7 Resets 15 7 Scan Manage...

Page 449: ...ffer Usage Overview 16 44 DMA Controller Registers 16 52 Address Map and Register Definitions 16 53 Document Revision History 16 53 Ethernet Media Access Controller 17 1 Features of the Ethernet MAC 17 1 MAC 17 1 PHY Interface 17 2 DMA Interface 17 2 Management Interface 17 2 Acceleration 17 2 Other Features 17 2 EMAC Block Diagram and System Integration 17 3 EMAC to RGMII Interface 17 3 EMAC to F...

Page 450: ...lines for Flexible Pulse Per Second PPS Output 17 56 Ethernet MAC Address Map and Register Definitions 17 58 Document Revision History 17 58 USB 2 0 OTG Controller 18 1 Features of the USB OTG Controller 18 2 Supported PHYs 18 3 USB OTG Controller Block Diagram and System Integration 18 4 Functional Description of the USB OTG Controller 18 5 USB OTG Controller Block Description 18 5 ULPI PHY Inter...

Page 451: ...20 Slave SPI and SSP Serial Transfers 19 22 Slave Microwire Serial Transfers 19 23 Software Control for Slave Selection 19 23 DMA Controller Operation 19 24 SPI Controller Address Map and Register Definitions 19 27 Document Revision History 19 28 I2 C Controller 20 1 Features of the I2 C Controller 20 1 I2 C Controller Block Diagram and System Integration 20 2 Functional Description of the I2 C Co...

Page 452: ... Programming Model 21 7 DMA Controller Operation 21 7 UART Controller Address Map and Register Definitions 21 10 Document Revision History 21 11 General Purpose I O Interface 22 1 Features of the GPIO Interface 22 1 GPIO Interface Block Diagram and System Integration 22 1 Functional Description of the GPIO Interface 22 2 Debounce Operation 22 2 Pin Directions 22 3 GPIO Interface Programming Model ...

Page 453: ... 3 Watchdog Timer Programming Model 24 4 Setting the Timeout Period Values 24 4 Selecting the Output Response Mode 24 4 Enabling and Initially Starting a Watchdog Timer 24 4 Reloading a Watchdog Counter 24 4 Pausing a Watchdog Timer 24 4 Disabling and Stopping a Watchdog Timer 24 4 Watchdog Timer State Machine 24 5 Watchdog Timer Address Map and Register Definitions 24 6 Document Revision History ...

Page 454: ...g the HPS Component 27 1 FPGA Interfaces 27 1 General Interfaces 27 1 Boot and Clock Selection Interfaces 27 2 AXI Bridges 27 3 FPGA to HPS SDRAM Interface 27 3 Reset Interfaces 27 5 DMA Peripheral Request 27 5 Configuring Peripheral Pin Multiplexing 27 5 Configuring Peripherals 27 5 Connecting Unassigned Pins to GPIO 27 7 Configuring HPS Clocks 27 7 User Clocks 27 7 PLL Reference Clocks 27 8 Conf...

Page 455: ...Interface 28 7 Peripheral Signal Interfaces 28 7 Other Interfaces 28 7 MPU Standby and Event Interfaces 28 8 FPGA to HPS Interrupts 28 8 General Purpose Interfaces 28 8 Document Revision History 28 9 HPS Simulation Support 29 1 Clock and Reset Interfaces 29 2 Clock Interface 29 2 Reset Interface 29 3 FPGA to HPS AXI Slave Interface 29 4 HPS to FPGA AXI Master Interface 29 4 Lightweight HPS to FPGA...

Page 456: ...ting HPS Simulation Model in Qsys 29 13 Running the Simulation 29 13 Document Revision History 29 17 Booting and Configuration Introduction A 1 HPS Boot A 3 Boot Process Overview A 3 Boot ROM A 5 HPS State on Entry to the Preloader A 11 Preloader A 12 Flash Memory Devices A 14 FPGA Configuration A 22 Full Configuration A 22 Document Revision History A 24 Altera Corporation TOC 17 Cyclone V Device ...

Page 457: ...ltiple boot sources including the FPGA fabric and external flash devices and the FPGA gets configured through the HPS or any external source supported by the device For more information refer to the Booting and Configuration appendix in volume 3 of the Cyclone V Device Overview The HPS and FPGA portions of the device each have their own pins Pins are not freely shared between the HPS and the FPGA ...

Page 458: ...r to the Booting and Configuration appendix in volume 3 of the Cyclone V Device Handbook Features of the HPS The following list contains the main modules of the HPS MPU subsystem featuring dual ARM Cortex A9 MPCore processors General purpose Direct Memory Access DMA controller Two Ethernet media access controllers EMACs Two USB 2 0 On The Go OTG controllers NAND flash controller Quad SPI flash con...

Page 459: ...t 32 Bit 32 Bit 32 Bit 64 Bit L3 Slave Peripheral Switch ACP CPU0 CPU1 SCU ARM Cortex A9 MPCore MPU Subsystem ACP ID Mapper SDRAM Controller Subsystem STM Boot ROM On Chip RAM DMA Quad SPI Flash FPGA Manager FPGA to HPS Bridge HPS to FPGA Bridge Lightweight HPS to FPGA Bridge L4 32 Bit Bus 32 Bit AXI 2 32 Bit 64 Bit AXI 64 Bit AXI L3 Main Switch FPGA Portion Control Block Masters Slaves Slaves 32 ...

Page 460: ...rconnect one 64 bit master port connected directly to the SDRAM L3 Interconnect and three ports that connect the FPGA to the SDRAM L3 Interconnect A programmable address filter in the L2 cache controls which portions of the 32 bit physical address space use which master Related Information Cortex A9 Microprocessor Unit Subsystem on page 6 1 Interconnect The interconnect consists of the L3 intercon...

Page 461: ...ntroller contains a multiport front end MPFE that accepts requests from HPS masters and from soft logic in the FPGA fabric via the FPGA to HPS SDRAM interface The SDRAM controller offers the following features Up to 4 GB address range 8 16 and 32 bit data widths Optional ECC support Low voltage 1 35V DDR3L and 1 2V DDR3U support Full memory device power management support Two chip selects The SDRA...

Page 462: ...quad SPI serial NOR flash devices Supports direct access and indirect access modes Supports single I O dual I O quad I O instructions Programmable data frame size of 8 16 or 32 bits Support up to four chip selects Related Information Quad SPI Flash Controller on page 12 1 SD MMC Controller The SD MMC controller is based on Synopsys DesignWare Mobile Storage Host controller and offers the following...

Page 463: ... places I O elements into a safe state for configuration Related Information System Manager on page 14 1 Scan Manager The scan manager offers the following features Drives serial scan chains to FPGA JTAG and HPS I O bank configuration Related Information Scan Manager on page 15 1 Timers The four timers are based on the Synopsys DesignWare APB Timers peripheral and offer the following features 32 b...

Page 464: ...nformation DMA Controller on page 16 1 FPGA Manager The FPGA manager offers the following features Manages configuration of the FPGA portion of the device 32 bit fast passive parallel configuration interface to the FPGA CSS block Partial reconfiguration Compressed FPGA configuration images Advanced Encryption Standard AES encrypted FPGA configuration images Monitors configuration related signals i...

Page 465: ...s generic root hub Automatic ping capability Configurable to OTG 1 3 and OTG 2 0 modes Related Information USB 2 0 OTG Controller on page 18 1 I 2 C Controllers The four I2 C controllers are based on Synopsys DesignWare APB I2 C controller and offer the following features Two controllers support I2 C management interfaces for the EMAC controllers which are for Ethernet control Support both 100 KBp...

Page 466: ...t processor DMA controller may be used for large transfers Available on certain device variants only Related Information CAN Controller Introduction on page 25 1 SPI Master Controllers The two SPI master controllers are based on Synopsys DesignWare Synchronous Serial Interface SSI controller and offer the following features Programmable data frame size from 4 to 16 bits Supports full and half dupl...

Page 467: ...ers the following features 64 KB size Contains the code required to support HPS boot from cold or warm reset Used exclusively for booting the HPS Related Information On Chip Memory on page 9 1 Endian Support The HPS is natively a little endian system All HPS slaves are little endian The processors masters are software configurable to interpret data as little endian or big endian byte invariant BE8...

Page 468: ...e FPGA fabric FPGA to HPSinterface aconfigurableinterfacetotheSDRAMschedulerintheSDRAML3interconnect You can configure the following parameters AXI 3 or Avalon Memory Mapped Avalon MM protocol Up to six ports 32 64 128 or 256 bit data width of each port FPGA clocks and resets provide flexible clocks to and from the HPS HPS to FPGA JTAG allows the HPS to master the FPGA JTAG chain TPIU trace sends ...

Page 469: ... thin black arrows indicate which address space is accessed by a window region arrows point to accessed address space For example accesses to the ACP window in the L3 address space map to a 1 GB region of the MPU address space The SDRAM window in the MPU address space can grow and shrink at the top and bottom short blue vertical arrows at the expense of the FPGA slaves and boot regions For specifi...

Page 470: ... controller define the SDRAM window boundaries The boundaries are megabyte aligned Addresses within the boundaries route to the SDRAM master Addresses outside the boundaries route to the L3 interconnect master As shown in the HPS Address Space Relationship diagram the reset values of the SDRAM window boundaries are shown By default processor accesses to locations between 0x100000 1 MB to 0xC000000...

Page 471: ...emap control register bits refer to the Interconnect chapter Cortex A9 Microprocessor Unit Subsystem on page 6 1 For details about L2 address filtering refer to the Cortex A9 Microprocessor Unit Subsystem chapter L3 Address Space The L3 address space is 4 GB and applies to all L3 masters except the MPU subsystem The L3 address space configurations contain the following regions The peripheral regio...

Page 472: ...ve Identifier column lists the names used in the HPS register map The Slave Title column contains the module name for modules with only one slave and module names plus a suffix for modules with more than one slave Table 1 5 Peripheral Region Address Map Size Base Address Slave Title Slave Identifier 48 MB 0xFC000000 STM STM 2 MB 0xFF000000 DAP DAP 2 MB 0xFF200000 FPGA slaves accessed with lightwei...

Page 473: ...controller registers USB1 64 KB 0xFFB80000 NAND controller registers NANDREGS 4 KB 0xFFB90000 FPGA manager configura tion data FPGAMGRDATA 4 KB 0xFFC00000 CAN0 controller registers CAN0 4 KB 0xFFC01000 CAN1 controller registers CAN1 4 KB 0xFFC02000 UART0 UART0 4 KB 0xFFC03000 UART1 UART1 4 KB 0xFFC04000 I2C0 I2C0 4 KB 0xFFC05000 I2C1 I2C1 4 KB 0xFFC06000 I2C2 I2C2 4 KB 0xFFC07000 I2C3 I2C3 4 KB 0x...

Page 474: ...4 KB 0xFFF01000 SPI master1 SPIM1 4 KB 0xFFF02000 Scan manager registers SCANMGR 64 KB 0xFFFD0000 Boot ROM ROM 8 KB 0xFFFEC000 MPU SCU registers MPUSCU 4 KB 0xFFFEF000 MPU L2 cache controller registers MPUL2 64 KB 0xFFFF0000 On chip RAM OCRAM Document Revision History Table 1 6 Document Revision History Changes Version Date Maintenance release 2013 12 30 December 2013 Minor updates 1 3 November 20...

Page 475: ...for enabling and disabling most clocks Initializes and sequences clocks for the following events Cold reset Safe mode request from reset manager on warm reset ISO 9001 2008 Registered 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Offi...

Page 476: ...r the FPGA to HPS HPS to FPGA and FPGA to HPS SDRAM interfaces The FPGA logic designer is responsible for selecting and managing these clocks Software must not program the clock manager with illegal values If it does the behavior of the clock manager is undefined and could stop the operation of the HPS The only guaranteed means for recovery from an illegal clock setting is a cold reset Related Inf...

Page 477: ...ctional Description of the Clock Manager Clock Manager Building Blocks PLLs The clock manager contains three PLLs main peripherals and SDRAM These PLLs generate the majority of clocks in the HPS There is no phase control between the clocks generated by the three PLLs Each PLL has the following features Phase detector and output lock signal generation Registers to set VCO frequency Multiplier range...

Page 478: ...ter than the values stored in the CSRs N 1 64 Phase Shift 1 8 Per Step C0 Divide 1 512 K 0 1 Phase Shift 1 8 Per Step C1 Divide 1 512 K 0 1 CLKOUT1 Phase Shift 1 8 Per Step C2 Divide 1 512 K 0 1 CLKOUT2 Phase Shift 1 8 Per Step C3 Divide 1 512 0 1 CLKOUT3 Phase Shift 1 8 Per Step C4 Divide 1 512 0 1 CLKOUT4 Phase Shift 1 8 Per Step C5 Divide 1 512 0 1 CLKOUT5 CLKOUT0 PFD VCO M 1 4096 FIN FREF FVCO...

Page 479: ...enerated from the main PLL outputs C0 C1 and C2 All other clocks in the HPS are software managed clocks Clock Groups The clock manager contains one clock group for each PLL and one clock group for the EOSC1 pin OSC1 Clock Group The clock in the OSC1 clock group is derived directly from the EOSC1 pin This clock is never gated or divided It is used as a PLL input and also by HPS logic that does not ...

Page 480: ...divided by programmable dividers external to the PLL Transitions to a different divide value occur on the fastest output clock one clock cycle prior to the slowest clock s rising edge For example cycle 15 of the divide by 16 divider for the main C2 output and cycle 3 of the divide by 4 divider for the main C0 output The following figure shows how each counter output from the main PLL can have its ...

Page 481: ...by 2 or 4 mpu_periph_clk mpu_l2_ram_clk l4_main_clk periph_base_clk from Peripheral PLL C4 l3_main_clk l3_sp_clk Divide by 1 2 4 8 or 16 Divide by 1 2 4 8 or 16 The clocks derived from main PLL C0 C2 outputs are hardware managed meaning hardware ensures that a clean transition occurs and can have the following control values changed dynamically by software write accesses to the control registers P...

Page 482: ... L4 main bus Main PLL C1 l4_main_clk Clock for L4 MP bus osc1_clk 16 to 100 MHz divided from main PLL C1 or peripheral PLL C4 l4_mp_clk Clock for L4 SP bus osc1_clk 16 to 100 MHz divided from main PLL C1 or peripheral PLL C4 l4_sp_clk Clock for CoreSight debug trace bus osc1_clk 4 to main PLL C2 2 dbg_at_clk Clock for CoreSight debug Trace Port Interface Unit TPIU osc1_clk 16 to main PLL C2 dbg_tr...

Page 483: ...g the VCO frequency in increments of 20 percent or less allow a slow ramp of the VCO base frequency without loss of lock For example to change a VCO frequency by 40 without losing lock change the frequency by 20 then change it again by 16 7 Peripheral Clock Group The peripheral clock group consists of a PLL dividers and clock gating The clocks in the peripheral clock group are derived from the per...

Page 484: ...for the SPI masters and up to 200 MHz for the scan manager periph_base_ base_clk C4 No osc1_clk to 100 MHz h2f_user1_ base_clk C5 The following figure shows programmable post PLL dividers and clock gating for the peripheral clock group Clock gate blocks in the diagram indicate clocks which may be gated off under software control Software is expected to gate these clocks off prior to changing any P...

Page 485: ...24 Bit Divider Clock Gate spi_m_clk Clock Gate can0_clk Clock Gate can1_clk Clock Gate gpio_db_clk Clock Gate To main PLL group l4_mp_clk l4_sp_clk multiplexer Clock Gate h2f_user1_clock usb_mp_clk Divide by 1 2 4 8 or 16 Divide by 1 2 4 8 or 16 Divide by 1 2 4 8 or 16 Divide by 1 2 4 8 or 16 To Flash Controller Clocks To Flash Controller Clocks Altera Corporation Clock Manager Send Feedback 2 11 ...

Page 486: ...Clock for L4 master peripheral bus Main PLL C1 or peripheral PLL C4 Up to 100 MHz l4_mp_clk Clock for L4 slave peripheral bus Main PLL C1 or peripheral PLL C4 Up to 100 MHz l4_sp_clk Controller area network CAN controller 0 clock Peripheral PLL C4 Up to 100 MHz can0_clk CAN controller 1 clock Peripheral PLL C4 Up to 100 MHz can1_clk Used to debounce GPIO0 GPIO1 and GPIO2 Peripheral PLL C4 Up to 1 ...

Page 487: ...ng for SDRAM PLL clock group Clock gate blocks in the diagram indicate clocks which may be gated off under software control Software is expected to gate these clocks off prior to changing any PLL or divider settings that might create incorrect behavior on these clocks Figure 2 5 SDRAM Clock Group Divide and Gating h2f_user2_base_clk Clock Gate Clock Gate Clock Gate Clock Gate ddr_dqs_base_clk ddr_...

Page 488: ...ipherals can be driven by the main PLL the peripheral PLL or from clocks provided by the FPGA fabric Figure 2 6 Flash Peripheral Clock Divide and Gating Clock Gate sdmmc_clk Divide by 4 Clock Gate nand_clk f2h_periph_ref_clk main_nand_sdmmc_base_clk periph_nand_sdmmc_base_clk f2h_periph_ref_clk main_nand_sdmmc_base_clk periph_nand_sdmmc_base_clk Clock Gate qspi_clk f2h_periph_ref_clk main_qspi_bas...

Page 489: ...managed clocks into safe mode the software managed clocks into their default state and asynchronously resets all registers in the clock manager Related Information Safe Mode on page 2 16 Warm Reset Registers in the clock manager control how the clock manager responds to warm reset Typically software places the clock manager into a safe state in order to generate a known set of clocks for the ROM c...

Page 490: ...clk clock including counters in the main PLL Programmable dividers select the reset default values The flash controller clocks multiplexer selects the output from the peripheral PLL All clocks are enabled A write by software is the only way to clear the safe mode bit safemode of the ctrl register Before coming out of safe mode all registers and clocks need to be configured correctly It is possible...

Page 491: ...for the System Trace Macrocell STM slave and Embedded Trace Router ETR master connections dbg_at_clk Clock for the DAP master connection dbg_clk Clock for the L3 master peripheral switch l3_mp_clk Clock for the L4 MP bus Secure Digital SD MultiMediaCard MMC master and EMAC masters l4_mp_clk Clock for the USB masters and slaves usb_mp_clk Clock for the NAND master nand_x_clk Clock for the FPGA mana...

Page 492: ... dbg_at_clk Clock synchronous to the quad SPI flash l4_mp_clk Clock for the control block CB data interface and configuration data slave cfg_clk FPGA manager Clock for the control slave l4_mp_clk Clock for the data slave l3_main_clk HPS to FPGA bridge Clock for the global programmer s view GPV slave l4_mp_clk Clock for the data master l3_main_clk FPGA to HPS bridge Clock for the GPV slave l4_mp_cl...

Page 493: ...estamp clock osc1_clk Clock for the master and slave usb_mp_clk USB 0 Clock for the master and slave usb_mp_clk USB 1 NAND high speed master and slave clock nand_x_clk NAND flash controller NAND flash clock nand_clk Clock for the OSC1 timer 0 osc1_clk OSC1 timer 0 Clock for the OSC1 timer 1 osc1_clk OSC1 timer 1 Clock for the SP timer 0 l4_sp_clk SP timer 0 Clock for the SP timer 1 l4_sp_clk SP ti...

Page 494: ...r the slave l4_sp_clk CAN controller 1 CAN 1 controller clock can1_clk Clock for the slave l4_mp_clk GPIO interface 0 Debounce clock gpio_db_clk Clock for the slave l4_mp_clk GPIO interface 1 Debounce clock gpio_db_clk Clock for the slave l4_mp_clk GPIO interface 2 Debounce clock gpio_db_clk Clock for the system manager osc1_clk System manager Clock for the control slave l4_sp_clk SDRAM subsystem ...

Page 495: ...aster controller 0 Clock for the SPI master 1 spi_m_clk SPI master controller 1 Clock for the SPI slave 0 l4_main_clk SPI slave controller 0 Clock for the SPI slave 1 l4_main_clk SPI slave controller 1 System bus clock l4_mp_clk Debug subsystem Debug clock dbg_clk Trace bus clock dbg_at_clk Trace port clock dbg_trace_clk Clock for the reset manager osc1_clk Reset manager Clock for the slave l4_sp_...

Page 496: ...ion to Cyclone V Hard Processor System HPS on page 1 1 The base addresses of all modules are also listed in the Introduction to the Hard Processor System chapter in the Cyclone V Device Handbook Volume 3 hps html For more information refer to this hps html chapter of the Cyclone V Device Handbook Document Revision History Table 2 10 Document Revision History Changes Version Date Minor formatting u...

Page 497: ...debug logic in the FPGA fabric connected to the HPS reset signals System ISO 9001 2008 Registered 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or servic...

Page 498: ...lready been through a cold reset Used to recover system from a non responsive condition Resets a subset of the HPS state reset by a cold reset Only affects the system reset domain which allows debugging including trace to operate through the warm reset Debug reset Occurs after HPS has already been through a cold reset Used to recover debug logic from a non responsive condition Only affects the deb...

Page 499: ... Interface L4 Peripheral Bus osc1_clk MPU DAP POR Voltage Detector Watchdog 2 nPOR nRST Signal Assertion De Assertion mpumodrst permodrst per2modrst brgmodrst and miscmodrst swcoldrstreq and swwarmrstreq bits of ctrl Scan Manager Reset Request Scan Manager load_csr fpga_config_complete HPS Modules HPS External Reset Sources The following table lists the reset sources external to the HPS All signal...

Page 500: ...set Controller The reset controller performs the following functions Accepts reset requests from the FPGA CB FPGA fabric modules in the HPS and reset pins Generates an individual reset signal for each module instance for all modules in the HPS Provides reset handshaking signals to support system reset behavior The reset controller generates module reset signals from external reset requests and int...

Page 501: ...r The reset controller supports the following cold reset requests Power on reset POR voltage monitor Cold reset request pin nPOR FPGA fabric FPGA CB and scan manager Software cold reset request bit swcoldrstreq of the control register ctrl The reset controller supports the following warm reset requests Warm reset request pin nRST FPGA fabric Software warm reset request bit swwarmrstreq of the ctrl...

Page 502: ...ts each processor in the MPU mpu_cpu_rst_n 0 X X X System Resets each processor in the MPU mpu_cpu_rst_n 1 X X System Resets both per processor watchdogs in the MPU mpu_wd_rst_n X X System Resets Snoop Control Unit SCU and peripherals mpu_scu_periph_rst_n X X System Level 2 L2 cache reset mpu_l2_rst_n Table 3 4 PER Group Generated Module Resets Software Deassert Debug Reset Warm Reset Cold Reset R...

Page 503: ...quest interface from FPGA fabric to DMA controller dma_periph_if_rst_n 7 0 Table 3 6 Bridge Group Generated Module Resets Software Deassert Debug Reset Warm Reset Cold Reset Reset Domain Description Module Reset Signal X X X System Resets HPS to FPGA AMBA Advanced eXtensibleInterface AXI bridge hps2fpga_bridge_rst_n X X X System Resets FPGA to HPS AXI bridge fpga2hps_bridge_rst_n X X X System Rese...

Page 504: ...timestamp_cold_rst_n X System Resets clock manager resets logic associated with cold reset only clk_manager_cold_rst_n X X System Resets scan manager scan_manager_rst_n X System Resets freeze controller resets logic associated with cold reset only frz_ctrl_cold_rst_n X X System Resets debug masters and slaves connected to L3 interconnect and level 4 L4 buses sys_dbg_rst_n X X Debug Resets debug co...

Page 505: ...reset manager at the same time Cold reset requests take priority over warm and debug reset requests Higher priority reset requests preempt lower priority reset requests There is no priority difference among reset requests within the same domain If a cold reset request is issued while another cold reset is already underway the reset manager extends the reset period for all the module reset outputs ...

Page 506: ...egisters Software can also bypass the reset controller and generate reset signals directly through the module reset control registers In this case software is responsible for asserting module reset signals driving them for the appropriate duration and deasserting them in the correct order The clock manager is not typically in safe mode during this time so software is responsible for knowing the re...

Page 507: ... the warm reset button whichever occurs later The cold and warm reset sequences consist of different reset assertion sequences and the same deassertion sequence The following sections describe the sequences Related Information Clock Manager on page 2 1 For more information about safe mode refer to the Clock Manager chapter Cold Reset Assertion Sequence The following list describes the assertion st...

Page 508: ... handshake which is deasserted by software 7 Proceed to the Cold and Warm Reset Deassertion Sequence section using the following link Related Information Cold and Warm Reset Deassertion Sequence on page 3 12 Cold and Warm Reset Deassertion Sequence The following list describes the deassertion steps for both cold and warm reset shown in the Cold Reset Timing Diagram and Warm Reset Timing Diagram 1 ...

Page 509: ...your software becomes more stable or for debug purposes you can alter the system response to a warm reset The following suggestions provide ways to alter the system response to a warm reset None of the register bits that control these items are affected by warm reset Boot from on chip RAM enables warm boot from on chip RAM instead of the boot ROM When enabled the boot ROM code validates the RAM co...

Page 510: ...r transactions to the L3 interconnect before the debug reset is issued This action ensures that when ETR undergoes a debug reset the reset has no adverse effects on the system domain portion of the ETR Reset Manager Address Map and Register Definitions The address map and register definitions reside in the hps html file that accompanies this handbook volume Click the link below to open the file To...

Page 511: ...mber 2013 Added cold and warm reset timing diagrams Minor updates 1 2 November 2012 Added reset controller functional description and address map and register definitions sections 1 1 May 2012 Initial release 1 0 January 2012 Altera Corporation Reset Manager Send Feedback 3 15 Document Revision History cv_54003 2013 12 30 ...

Page 512: ...ammable master priority with single cycle arbitration Full pipelining to prevent master stalls Programmable control for FIFO buffer transaction release Security of the following types Secure Nonsecure Per transaction security Five independent L4 buses ISO 9001 2008 Registered 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and l...

Page 513: ...lk 64 Bit AXI l3_main_clk 32 Bit AXI l3_main_clk M M M M M M M M M M 32 Bit AXI nand_x_clk 32 Bit AXI nand_x_clk 32 Bit AHB usb_mp_clk 32 Bit AHB l4_mp_clk S 32 Bit AXI l3_sp_clk 64 Bit AXI l4_main_clk l3_main_clk S L3 Slave Peripheral Switch l3_sp_clk M M M M S ACP CPU0 CPU1 SCU ARM Cortex A9 MPCore L2 Cache S S MPU Subsystem mpu_clk S S S ACP ID Mapper S 64 Bit AXI mpu_l2_ram_clk SDRAM Controlle...

Page 514: ...es 32 bit data width Five independent L4 buses The L3 master and slave peripheral switches are fully connected crossbars The L3 main switch is a partially connected crossbar The following table shows the connectivity matrix of all the master and slave interfaces of the L3 main switch Table 4 1 L3 Main Switch Connectivity Matrix Connected Slaves Masters HPS to FPGA Bridge ACP ID Mapper Data On Chip...

Page 515: ...ral switch USB1 Connected to the L3 master peripheral switch NAND Connected to the L3 master peripheral switch SD MMC Connected to the L3 master peripheral switch ETR Connected to the L3 master peripheral switch DAP Connected to the L3 main switch L3 Slaves The following list contains all of the slave interfaces connected to the L3 interconnect USB0 CSR slave interface connected to the L3 slave pe...

Page 516: ...connected to the L3 main switch STM Connected to the L3 main switch Boot ROM Connected to the L3 main switch On chip RAM Connected to the L3 main switch SDRAM controller subsystem SDRAM multi port front end slave interface connected to the L3 main switch Altera Corporation Interconnect Send Feedback 4 5 L3 Slaves cv_54004 2013 12 30 ...

Page 517: ...access FPGA manager CSR access DAP CSR access Quad SPI flash CSR access SD MMC CSR access EMAC0 CSR access EMAC1 CSR access GPIO0 CSR access GPIO1 CSR access GPIO2 CSR access L4 oscillator 1 OSC1 bus APB dedicated to peripherals that operate on the external oscillator 1 domain OSC1 timer 0 CSR access OSC1 timer 1 CSR access Watchdog 0 CSR access Watchdog 1 CSR access Clock manager CSR access Reset...

Page 518: ...vity matrix of all the master and slave interfaces of the interconnect Table 4 2 Interconnect Connectivity Matrix Connected Slaves Masters L4 SP Bus Slaves L4 MP Bus Slaves L4 OSC1 Bus Slaves L4 MAIN Bus Slaves L4 SPIM Bus Slaves Lightweight HPS to FPGA Bridge USB OTG 0 1 CSR NAND CSR NAND Command and Data Quad SPI Flash Data FPGA Manager HPS to FPGA Bridge STM Boot ROM On Chip RAM L2 Cache Master...

Page 519: ...us Slaves L4 MAIN Bus Slaves L4 SPIM Bus Slaves Lightweight HPS to FPGA Bridge USB OTG 0 1 CSR NAND CSR NAND Command and Data Quad SPI Flash Data FPGA Manager HPS to FPGA Bridge ACP ID Mapper Data STM On Chip RAM SDRAM Controller Subsystem L3 Data DMA HPS to FPGA Bridge ACP ID Mapper Data On Chip RAM SDRAM Controller Subsystem L3 Data EMAC 0 1 HPS to FPGA Bridge ACP ID Mapper Data On Chip RAM SDRA...

Page 520: ...p register Remapping allows software to control which memory device SDRAM on chip RAM or boot ROM is accessible at address 0x0 and the accessibility of the HPS to FPGA and lightweight HPS to FPGA bridges The remap register is one of the NIC 301 Global Programmers View GPV registers and maps into the address space of the following L3 masters MPU FPGA to HPS bridge DAP The remapping bits in the rema...

Page 521: ...ter interface L2 cache master 0 interface Non MPU master interfaces DMA master interface Master peripheral interfaces Debug Access Port DAP master interface FPGA to HPS bridge master interface Interconnect Altera Corporation Send Feedback cv_54004 Address Remapping 4 10 2013 12 30 ...

Page 522: ... another master that connects directly to the SDRAM controller subsystem The address filter registers in the MPU L2 control which MPU addresses are sent to each master This figure assumes the filter registers contain their reset values 4 This address range is configurable 5 This address range is not accessible from the master peripheral interfaces 6 This address range is not accessible from the DA...

Page 523: ... master 3 hps2fpga When set to 1 the lightweight HPS to FPGA bridge slave port is visible to the L3 masters When set to 0 accesses to the associated address range return an AXI decode error to the master 4 lwhp2fpga Must always be set to 0 31 5 Reserved L2 filter registers in the MPU subsystem not the interconnect allow the SDRAM to be remapped to address 0 for the MPU Note Related Information Cor...

Page 524: ...rity Masters of the interconnect are either secure nonsecure or the security is set on a per transaction basis The DAP is capable of performing only secure accesses The L2 cache master 0 FPGA to HPS bridge and DMA perform secure and nonsecure accesses on a per transaction basis All other interconnect masters perform nonsecure accesses Accesses to secure slaves by unsecure masters result in a respo...

Page 525: ...ensures the following conditions at a slave interface of a switch All outstanding read transactions with the same ID go the same destination All outstanding write transactions with the same ID go the same destination When a master issues a transaction the following situations can occur If the transaction has an ID that does not match any outstanding transactions it passes the CDAS If the transacti...

Page 526: ...6 16 32 SSPID No Nonsecure L3 master peripheral switch l4_main_clk 32 EMAC0 1 AHB 2 2 2 2 2 4 SSPID No Nonsecure L3 master peripheral switch usb_mp_clk 32 USB OTG 0 1 AXI 2 2 2 2 2 1 8 9 SSPID No Nonsecure L3 master peripheral switch nand_x_clk 32 NAND AHB 2 2 2 2 2 4 SSPID No Nonsecure L3 master peripheral switch l4_mp_clk 32 SD MMC AXI 2 2 2 2 2 32 1 32 SSPID No Nonsecure L3 master peripheral sw...

Page 527: ...1 1 1 L4 SP bus master l4_mp_clk 32 Quad SPI flash CSR APB 2 2 2 1 1 1 L4 SP bus master l4_mp_clk 32 SD MMC CSR APB 2 2 2 1 1 1 L4 SP bus master l4_mp_clk 32 EMAC 0 1 CSR APB 2 2 2 1 1 1 L4 OSC1 bus master osc1_clk 32 System manager APB 2 2 2 1 1 1 L4 OSC1 bus master osc1_clk 32 OSC1 timer 0 1 APB 2 2 2 1 1 1 L4 OSC1 bus master osc1_clk 32 Watchdog 0 1 APB 2 2 2 1 1 1 L4 OSC1 bus master osc1_clk 3...

Page 528: ... Width Function The upsizing function combines narrow transactions into wider transactions to increase the overall system bandwidth Upsizing only packs data for read or write transactions that are cacheable If the interconnect splits input exclusive transactions into more than one output bus transaction it removes the exclusive information from the multiple transactions it creates The upsizing fun...

Page 529: ...ptimal data width at the destination Downsizing does not merge multiple transaction data narrower than the destination bus if the transactions are marked as noncacheable The downsizing function reduces the data width by the following ratios 2 1 4 1 Incrementing Bursts The interconnect converts INCR bursts that fall within the maximum payload size of the output data bus to a single INCR burst It co...

Page 530: ...FIFO Buffers and Clocks The interconnect contains FIFO buffers in the majority of the interfaces exposed to the HPS master and slaves as well as between the subswitches These FIFO buffers also provide clock domain crossing for masters and slaves that operate at a different clock frequency than the switch they connect to Data Release Mechanism For network ports containing write data FIFO buffers wi...

Page 531: ... relative to the base address of each module instance Related Information Introduction to Cyclone V Hard Processor System HPS on page 1 1 The base addresses of all modules are also listed in the Introduction to the Hard Processor chapter Cyclone V SoC HPS Address Map and Register Definitions Document Revision History Table 4 6 Document Revision History Changes Version Date Maintenance release 2013...

Page 532: ...mponents such as a Nios II processor in the FPGA fabric and their master interfaces can access memories or peripherals in the HPS logic Table 5 1 AXI Bridge Features Lightweight HPS to FPGA Bridge HPS to FPGA Bridge FPGA to HPS Bridge Feature Y Y Y Supports the AMBA AXI3 interface protocol ISO 9001 2008 Registered 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACO...

Page 533: ...PS Component on page 27 1 For information about configuring the AXI bridges refer to the Instantiating the HPS Component chapter AXI Bridges Block Diagram and System Integration Figure 5 1 AXI Bridge Connectivity The following figure shows a block diagram of the AXI bridges in the context of the FPGA fabric and the L3 interconnect to the HPS Each master M and slave S interface is shown with its da...

Page 534: ... control the bridge properties and behavior Access to the GPV registers of all three bridges is provided through the lightweight HPS to FPGA bridge The GPV registers can only be accessed by secure masters in the HPS or the FPGA fabric FPGA to HPS Bridge The FPGA to HPS bridge provides access to the peripherals and memory in the HPS This access is available to any master implemented in the FPGA fab...

Page 535: ...r correction code ECC option is enabled in the level 2 L2 cache controller all accesses from the FPGA to HPS bridge to the ACP must be 64 bits wide and aligned on 8 byte boundaries after up or downsizing takes place Table 5 3 FPGA Master and FPGA to HPS Bridge Configurations The following table lists some possible master and FPGA to HPS bridge slave configurations that support accesses to the L2 c...

Page 536: ...tion Width Signal Write address ID Input 8 bits AWID Write address Input 32 bits AWADDR Burst length Input 4 bits AWLEN Burst size Input 3 bits AWSIZE Burst type Input 2 bits AWBURST Lock type Valid values are 00 normal access and 01 exclusive access Input 2 bits AWLOCK Cache policy type Input 4 bits AWCACHE Protection type Input 3 bits AWPROT Write address channel valid Input 1 bit AWVALID Write ...

Page 537: ...ype Valid values are 00 normal access and 01 exclusive access Input 2 bits ARLOCK Cache policy type Input 4 bits ARCACHE Protection type Input 3 bits ARPROT Read address channel valid Input 1 bit ARVALID Read address channel ready Output 1 bit ARREADY Read user sideband signals Input 5 bits ARUSER Table 5 8 FPGA to HPS Bridge Slave Read Data Channel Signals Description Direction Width Signal Read ...

Page 538: ...able lists the properties of the HPS to FPGA bridge including the configurable master interface exposed to the FPGA fabric Table 5 9 HPS to FPGA Bridge Properties FPGA Master Interface L3 Slave Interface Bridge Property 32 64 or 128 bits 64 bits Data width 3 h2f_axi_clk l3_main_clk Clock domain 30 bits 32 bits Byte address width 12 bits 12 bits ID width 16 transactions 16 transactions Read accepta...

Page 539: ...s Description Direction Width Signal Write address ID Output 12 bits AWID Write address Output 30 bits AWADDR Burst length Output 4 bits AWLEN Burst size Output 3 bits AWSIZE Burst type Output 2 bits AWBURST Lock type Valid values are 00 normal access and 01 exclusive access Output 2 bits AWLOCK Cache policy type Output 4 bits AWCACHE Protection type Output 3 bits AWPROT Write address channel vali...

Page 540: ...RADDR Burst length Output 4 bits ARLEN Burst size Output 3 bits ARSIZE Burst type Output 2 bits ARBURST Lock type Valid values are 00 normal access and 01 exclusive access Output 2 bits ARLOCK Cache policy type Output 4 bits ARCACHE Protection type Output 3 bits ARPROT Read address channel valid Output 1 bit ARVALID Read address channel ready Input 1 bit ARREADY Table 5 14 HPS to FPGA Bridge Maste...

Page 541: ...o FPGA peripherals This approach diverts traffic from the high performance HPS to FPGA bridge and can improve both CSR access latency and overall system performance The following table lists the properties of the lightweight HPS to FPGA bridge including the master interface exposed to the FPGA fabric Table 5 15 Lightweight HPS to FPGA Bridge Properties FPGA Master Interface L3 Slave Interface Brid...

Page 542: ...the lightweight HPS to FPGA master interface to the FPGA fabric Table 5 16 Lightweight HPS to FPGA Bridge Master Write Address Channel Signals Description Direction Width Signal Write address ID Output 12 bits AWID Write address Output 21 bits AWADDR Burst length Output 4 bits AWLEN Burst size Output 3 bits AWSIZE Burst type Output 2 bits AWBURST Lock type Valid values are 00 normal access and 01 ...

Page 543: ...Output 12 bits ARID Read address Output 21 bits ARADDR Burst length Output 4 bits ARLEN Burst size Output 3 bits ARSIZE Burst type Output 2 bits ARBURST Lock type Valid values are 00 normal access and 01 exclusive access Output 2 bits ARLOCK Cache policy type Output 4 bits ARCACHE Protection type Output 3 bits ARPROT Read address channel valid Output 1 bit ARVALID Read address channel ready Input ...

Page 544: ...anager chapter HPS Component Interfaces on page 28 1 For information about the f2h_axi_clk clock refer to the HPS Component Interfaces chapter HPS to FPGA Bridge The master interface into the FPGA fabric operates in the h2f_axi_clk clock domain The h2f_axi_clk clock is provided by user logic The slave interface of the bridge in the HPS logic operates in the l3_main_clk clock domain The bridge prov...

Page 545: ...ted Information The Global Programmers View on page 5 3 Data Width Sizing The HPS to FPGA and FPGA to HPS bridges allow 32 64 and 128 bit interfaces to be exposed to the FPGA fabric For 32 bit and 128 bit interfaces the bridge performs data width conversion to the fixed 64 bit interface within the HPS This conversion is called upsizing in the case of data being converted from a 64 bit interface to...

Page 546: ...ck the register names The register addresses are offsets relative to the base address of each module instance Related Information Introduction to Cyclone V Hard Processor System HPS on page 1 1 The base addresses of all modules are also listed in the Introduction to the Hard Processor chapter hps html Document Revision History Table 5 21 Document Revision History Changes Version Date Maintenance r...

Page 547: ...ll rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants perfo...

Page 548: ... L2 cache can access either the level 3 L3 interconnect fabric or the SDRAM L2 Cache MPU Subsystem L3 Interconnect NIC 301 SDRAM Controller Subsystem ACP ID Mapper Interrupts Debug Infrastructure CPU1 SCU ACP M1 M0 ARM Cortex A9 MPCore CPU0 Cortex A9 Microprocessor Unit Subsystem Altera Corporation Send Feedback cv_54006 Cortex A9 MPU Subsystem Block Diagram and System Integration 6 2 2013 12 30 ...

Page 549: ...gine with FPU MMU 32 KB Instruction Cache 32 KB Data Cache NEON Media SIMD Processing Engine with FPU MMU 32 KB Instruction Cache 32 KB Data Cache ARM Cortex A9 Processor CPU0 Private Interval Timer CPU1 Private Watchdog Timer CPU1 Private Interval Timer CoreSight Multicore Debug and Trace Cross Triggering Event Trace CPU0 Performance Monitor CPU0 Program Trace CPU1 Performance Monitor CPU1 Progra...

Page 550: ...dog timer for each processor core Global timer Interrupt controller Each transaction originating from the Altera Cortex A9 MPU subsystem can be flagged as secure or nonsecure Implementation Details Table 6 1 Cortex A9 MPCore Processor Configuration This table shows the parameter settings for the Altera Cortex A9 MPCore Options Feature 1 or 2 Cortex A9 processors 32 KB Instruction cache size per Co...

Page 551: ...vel 1 L1 cache with parity checking 32 KB four way set associative instruction cache 32 KB four way set associative data cache CoreSight Program Trace Macrocell PTM supporting instruction trace Each Cortex A9 processor supports the following features Dual issue superscalar pipeline with advanced branch prediction Out of order OoO dispatch and speculative instruction execution 2 5 million instructi...

Page 552: ...l JTAG tools or by processor based monitor code For more information about the interactive debugging system refer to the Debug chapter of the Cortex A9 Technical Reference Manual available on the ARM website infocenter arm com Related Information ARM Infocenter www infocenter arm com L1 Caches Cache memory that is closely coupled with an associated processor is called level 1 or L1 cache Each Cort...

Page 553: ...ating Point Unit Each ARM Cortex A9 processor includes full support for IEEE 754 floating point operations The floating point unit FPU fully supports half single and double precision variants of the following operations Add Subtract Multiply Divide Multiply and accumulate MAC Square root The FPU also converts between floating point data formats and integers including special operations to round to...

Page 554: ...on for single bit coefficients The following operations are available Addition and subtraction Multiplication with optional accumulation MAC Maximum or minimum value driven lane selection operations Inverse square root approximation Comprehensive data structure load instructions including register bank resident table lookup For more information about the Cortex A9 NEON MPE refer to the Cortex A9 N...

Page 555: ...on The FPGA slaves region The HPS peripherals region Related Information ARM Infocenter www infocenter arm com The Boot Region The boot region is 1 MB in size based at address 0 After power on or after reset of the L3 interconnect the boot region is occupied by the boot ROM allowing the Cortex A9 MPCore to boot Although the boot region size is 1 MB accesses beyond 64 KB are illegal because the boo...

Page 556: ...rt reg12_address_filtering_end address_filtering_end To remap the lower 1MB of SDRAM into the boot region set the filter start address to 0x0 to ensure accesses between 0x0 and 0xFFFFF are routed to the SDRAM Independently you can set the filter end address in 1 MB increments above 0xC0000000 to extend the upper bounds of the SDRAM region However you achieve this extended range at the expense of t...

Page 557: ...can access it If the watchdog timer is not needed it can be configured as a second interval timer Each private interval and watchdog timer has the following features A 32 bit counter that optionally generates an interrupt when it reaches zero Configurable starting values for the counter An eight bit prescaler value to qualify the clock period Implementation Details The timers are configurable to e...

Page 558: ...CortexA9_0 32 Edge cpu0_parityfail_BTAC CortexA9_0 33 Edge cpu0_parityfail_GHB CortexA9_0 34 Edge cpu0_parityfail_I_Tag CortexA9_0 35 Edge cpu0_parityfail_I_Data CortexA9_0 36 Edge cpu0_parityfail_TLB CortexA9_0 37 Edge cpu0_parityfail_D_Outer CortexA9_0 38 Edge cpu0_parityfail_D_Tag CortexA9_0 39 Edge cpu0_parityfail_D_Data CortexA9_0 40 Level cpu0_deflags0 CortexA9_0 41 Level cpu0_deflags1 Corte...

Page 559: ...xA9_1 57 Level cpu1_deflags1 CortexA9_1 58 Level cpu1_deflags2 CortexA9_1 59 Level cpu1_deflags3 CortexA9_1 60 Level cpu1_deflags4 CortexA9_1 61 Level cpu1_deflags5 CortexA9_1 62 Level cpu1_deflags6 CortexA9_1 63 Edge scu_parityfail0 SCU 64 Edge scu_parityfail1 SCU 65 Edge scu_ev_abort SCU 66 6 To ensure that you are using the correct GIC interrupt number your code should refer to the symbolic int...

Page 560: ... or Edge FPGA_IRQ10 FPGA 82 Level or Edge FPGA_IRQ11 FPGA 83 Level or Edge FPGA_IRQ12 FPGA 84 Level or Edge FPGA_IRQ13 FPGA 85 Level or Edge FPGA_IRQ14 FPGA 86 Level or Edge FPGA_IRQ15 FPGA 87 Level or Edge FPGA_IRQ16 FPGA 88 6 To ensure that you are using the correct GIC interrupt number your code should refer to the symbolic interrupt name as shown in the InterruptName column Symbolic interrupt ...

Page 561: ...Q30 FPGA 102 Level or Edge FPGA_IRQ31 FPGA 103 Level or Edge FPGA_IRQ32 FPGA 104 Level or Edge FPGA_IRQ33 FPGA 105 Level or Edge FPGA_IRQ34 FPGA 106 Level or Edge FPGA_IRQ35 FPGA 107 Level or Edge FPGA_IRQ36 FPGA 108 Level or Edge FPGA_IRQ37 FPGA 109 Level or Edge FPGA_IRQ38 FPGA 110 Level or Edge FPGA_IRQ39 FPGA 111 6 To ensure that you are using the correct GIC interrupt number your code should ...

Page 562: ...GA_IRQ53 FPGA 125 Level or Edge FPGA_IRQ54 FPGA 126 Level or Edge FPGA_IRQ55 FPGA 127 Level or Edge FPGA_IRQ56 FPGA 128 Level or Edge FPGA_IRQ57 FPGA 129 Level or Edge FPGA_IRQ58 FPGA 130 Level or Edge FPGA_IRQ59 FPGA 131 Level or Edge FPGA_IRQ60 FPGA 132 Level or Edge FPGA_IRQ61 FPGA 133 Level or Edge FPGA_IRQ62 FPGA 134 6 To ensure that you are using the correct GIC interrupt number your code sh...

Page 563: ...d_IRQ EMAC0 150 Level emac0_rx_ecc_uncorrected_IRQ EMAC0 151 Level 10 emac1_IRQ EMAC1 152 Level emac1_tx_ecc_corrected_IRQ EMAC1 153 Level emac1_tx_ecc_uncorrected_IRQ EMAC1 154 Level emac1_rx_ecc_corrected_IRQ EMAC1 155 Level emac1_rx_ecc_uncorrected_IRQ EMAC1 156 6 To ensure that you are using the correct GIC interrupt number your code should refer to the symbolic interrupt name as shown in the ...

Page 564: ...c_IRQ SDMMC 171 Level sdmmc_porta_ecc_corrected_IRQ SDMMC 172 Level sdmmc_porta_ecc_uncorrected_IRQ SDMMC 173 Level sdmmc_portb_ecc_corrected_IRQ SDMMC 174 Level sdmmc_portb_ecc_uncorrected_IRQ SDMMC 175 Level nand_IRQ NAND 176 Level nandr_ecc_corrected_IRQ NAND 177 Level nandr_ecc_uncorrected_IRQ NAND 178 Level nandw_ecc_corrected_IRQ NAND 179 6 To ensure that you are using the correct GIC interr...

Page 565: ... 197 Level gpio2_IRQ GPIO2 198 6 To ensure that you are using the correct GIC interrupt number your code should refer to the symbolic interrupt name as shown in the InterruptName column Symbolic interrupt names are defined in a header file distributed with the source installation for your operating system 11 This interrupt combines the following interrupts ssi_txe_intr ssi_txo_intr ssi_rxf_intr ss...

Page 566: ...am_ecc_uncorrected_IRQ On chip RAM 211 Related Information Implementation Details on page 6 12 Global Timer The MPU features a global 64 bit auto incrementing timer which is primarily used by the operating system 6 To ensure that you are using the correct GIC interrupt number your code should refer to the symbolic interrupt name as shown in the InterruptName column Symbolic interrupt names are def...

Page 567: ...vailable on the ARM website infocenter arm com Related Information ARM Infocenter www infocenter arm com Snoop Control Unit The SCU manages data traffic for the Cortex A9 processors and the memory system including the L2 cache In a multi master system the processors and other masters can operate on shared data The SCU ensures that each processor operates on the most up to date copy of data maintai...

Page 568: ... the data is not in the L2 cache memory the read is finally forwarded to main memory The primary goal is to minimize power consumption and maximize overall memory performance The SCU maintains bidirectional coherency between the L1 data caches belonging to the processors When one processor writes to a location in its L1 cache if the same location is cached in the other L1 cache the SCU updates it ...

Page 569: ...tually overwrite all the bytes in the word Instead the cache assumes the whole cache line is valid If this line is dirty and therefore gets written out to SDRAM data corruption might occur Exclusive and Locked Accesses The ACP does not support exclusive accesses to coherent memory The ACP supports exclusive accesses to non coherent memory however it is important that the exclusive access transacti...

Page 570: ... ARM website infocenter arm com Related Information ARM Infocenter www infocenter arm com Implementation Details The ACP is accessed by masters that require access to coherent memory The ACP slave port can be accessed by the master peripherals of the L3 interconnect as well as by masters implemented in the FPGA fabric via the FPGA to HPS bridge The ACP ID mapper supports the following ID mapping m...

Page 571: ...ontrol overriding this signal The ACP ID mapper can also control which 1 GB coherent window into memory is accessed by masters of the L3 interconnect Each fixed mapping can be assigned a different user sideband signal and memory window to allow specific settings for different masters All dynamic mappings share a common user sideband signal and memory window setting Transaction Capabilities At any ...

Page 572: ...lways assigned to a specific output ID Unlike dynamic mode ID 7 is not available for fixed mapping because it is reserved for dynamic mode only to avoid system deadlocks The ACP ID mapper has two banks of registers to control the behavior of the mappings namely a request bank and a read only status bank Both banks contain the same number of registers To change the settings for a particular mapping...

Page 573: ...configure the default values of the user sideband signals for all transactions and fixed values of these signals for particular transactions in fixed mapping mode In dynamic mode the user sideband signals of incoming transactions are mapped with the default values stored in the register In fixed mapping mode the input ID of the transaction is mapped to the 3 bit output ID and the user sideband sig...

Page 574: ...apped to output ID 2 so the debugger can vary the 1 GB window that the DAP accesses without affecting any other traffic flow to the ACP L2 Cache The MPU subsystem includes a secondary 512 KB L2 shared unified cache memory Functional Description The L2 cache is much larger than the L1 cache The L2 cache has significantly lower latency than external memory The L2 cache is up to eight way associative...

Page 575: ...cate Related Information L2 Cache Event Monitoring on page 6 31 System Manager on page 14 1 L2 Cache Address Filtering The L2 cache can access either the L3 interconnect fabric or the SDRAM The L2 cache address filtering determines how much address space is allocated to the HPS to FPGA bridge and how much is allocated to SDRAM depending on the configuration of the memory management unit Memory Man...

Page 576: ...re the cache data is likely to be incorrect on subsequent reads To use ECCs the software and system must meet the following requirements L1 and L2 cache must be configured as write back allocate for any cacheable memory region FPGA soft IP using the ACP must only perform the following types of data writes 64 bit aligned in memory 64 bit wide accesses For more information about SEU errors refer to ...

Page 577: ...r all of the eight cache ways to be locked This is commonly used for loading critical data or code into the cache Lockdown by master Allows cache ways to be dedicated to a single master port This allows a large cache to look like smaller caches to multiple master ports The L2 cache can be mastered by CPU0 CPU1 or the six ACP masters for a total of eight possible master ports For more information a...

Page 578: ... confirmed in slave port S0 SRCONFS0 Speculative read confirmed in slave port S1 SRCONFS1 Speculative read received by slave port S0 SRRCVDS0 Speculative read received by slave port S1 SRRCVDS1 Allocation into the L2 cache caused by a write with write allocate attribute miss WA For more information about the built in L2 event monitoring capability refer to Implementation details in the Functional ...

Page 579: ...s Supported by the PTM Additional Waypoint Information Type Target address and condition code Indirect branches Condition code Direct branches Instruction barrier instructions Location where the exception occurred Exceptions Changes in processor instruction set state Changes in processor security state Context ID changes Entry to and return from debug state when Halting debug mode is enabled The P...

Page 580: ... Information CoreSight Debug and Trace on page 7 1 Cortex A9 MPU Subsystem Register Implementation The following configurations are available through registers in the Cortex A9 subsystem All processor related controls including the MMU and L1 caches are controlled using the Coprocessor 15 CP15 registers of each individual processor All SCU registers including control for the timers and GIC are mem...

Page 581: ... 2013 12 30 December 2013 Minor updates 1 2 November 2012 Add description of the ACP ID mapper Consolidate redundant information 1 1 May 2012 Initial release 1 0 January 2012 Altera Corporation Cortex A9 Microprocessor Unit Subsystem Send Feedback 6 35 Document Revision History cv_54006 2013 12 30 ...

Page 582: ...system trace messages Instruction trace interface through TPIU for trace analysis tools Custom message injection through STM into trace stream for delivery to host debugger STM and PTM trace sources multiplexed into a single stream through the Trace Funnel ISO 9001 2008 Registered 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words ...

Page 583: ...ARM Debug Interface v5 Architecture Specification ARM IHI 0031A Embedded Cross Trigger Technical Reference Manual ARM DDI 0291A CoreSight Components Technical Reference Manual ARM DDI 0314H CoreSight Program Flow Trace Architecture Specification ARM IHI 0035A CoreSight PTM A9 Technical Reference Manual ARM DDI 0401B CoreSight System Trace Macrocell Technical Reference Manual ARM DDI 0444A System T...

Page 584: ...gers to from FPGA CTM 1 4 0 Events from FPGA L3 Interconnect Master Peripheral Switch System AHB System APB HPS JTAG Pins Debug APB PTM 0 ATB PTM 1 ATB Debug APB Hardware Events CTI Triggers 3 0 To FPGA MPU Debug Subsystem HPS Debug System CTI NOC Triggers to from NOC 3 Functional Description of CoreSight Debug and Trace CoreSight systems provide all the infrastructure you require to debug monitor...

Page 585: ... peripheral registers The HPS JTAG interface does not support boundary scan tests BST To perform boundary scan testing on HPS I Os use the FPGA JTAG pins Note Related Information Info center For more information refer to the CoreSight Components Technical Reference Manual on the ARM info center website System Trace Macrocell STM The STM allows messages to be injected into the trace stream for deli...

Page 586: ...ace unit TPIU Related Information Info center For more information refer to the CoreSight Components Technical Reference Manual on the ARM info center website Embedded Trace Router ETR The ETR can route trace data to the HPS on chip RAM the HPS SDRAM and any memory in the FPGA fabric connected to the HPS to FPGA bridge The ETR receives trace data from the Replicator By default the buffer to receiv...

Page 587: ...hows how CTIs and CTMs are used in a generic ECT setup The red line depicts an trigger input to one CTI generating a trigger output in another CTI Though the signal travels throughout channel 2 it only enters and exits through trigger inputs and outputs you configure Trigger Inputs Trigger Outputs CTI Channel 0 Channel 1 Channel 2 Channel 3 CTI CTI CTI CTM Trigger Interface Trigger Interface Trigg...

Page 588: ...ss triggering between the STM ETF ETR and TPIU FPGA CTI exposes the cross triggering system to the FPGA fabric CTI 0 and CTI 1 reside in the MPU debug subsystem Each CTI is associated with a processor and the processor s associated PTM Cross Trigger Matrix CTM A CTM is a transport mechanism for triggers traveling from one CTI to one or more CTIs or CTMs The HPS contains two CTMs One CTM connects c...

Page 589: ...re The following figure shows the structure of a CTM channel Paths inside the CTM are purely combinatorial In Out Channel 0 CoreSight Debug and Trace Altera Corporation Send Feedback cv_54007 Cross Trigger Matrix CTM 7 8 2013 12 30 ...

Page 590: ...hannel Interface Related Information Info center For more information refer to the CoreSight Components Technical Reference Manual on the ARM info center website Program Trace Macrocell PTM The PTM performs real time program flow instruction tracing and provides a variety of filters and triggers that can be used to trace specific portions of code The HPS contains two PTMs Each PTM is paired with a...

Page 591: ... the FPGA fabric can signal an event which triggers an STM message injection into the trace stream CoreSight components are configured through memory mapped registers located at offsets relative to the CoreSight component base address CoreSight component base addresses are accessible through a ROM table Related Information Info center Programming interface details of each CoreSight component ROM T...

Page 592: ... allocates 48 MB of consecutive address space to the STM AXI slave port divided in three 16 MB segments Table 7 2 STM AXI Slave Port Address Allocation End Address Start Address Segment 0xFCFF_FFFF 0xFC00_0000 0 0xFDFF_FFFF 0xFD00_0000 1 0xFEFF_FFFF 0xFE00_0000 2 Each of the three masters can access any one of the three address segments Your software design determines which master uses which segme...

Page 593: ...debug system to the FPGA DAP The DAP uses the system APB port to connect to the FPGA Table 7 5 DAP The following table shows the signal description between DAP and FPGA Description Segment Address bus to system APB port h2f_dbg_apb_PADDR 18 Address bus to system APB port h2f_dbg_apb_PADDR31 Enable signal from system APB port h2f_dbg_apb_PENABLE 32 bit system APB port read data bus h2f_dbg_apb_PRDA...

Page 594: ...able to the NoC interconnect TPIU Signal descriptions between TPIU and FPGA Table 7 7 TPIU Description Signal Selects whether trace data is captured using the internal TPIU clock or an external clock provided as an input to the TPIU from the FPGA 0 use h2f_tpiu_clock_in 1 use internal clock Note When the FPGA is powered down or not configured the TPIU uses the internal clock h2f_tpiu_clk_ctl 32 bi...

Page 595: ...Input Signals The following table lists the trigger input pin connections implemented for csCTI Source Signal Number STM ASYNCOUT 7 STM TRIGOUTHETE 6 STM TRIGOUTSW 5 STM TRIGOUTSPTE 4 ETR ACQCOMP 3 ETR FULL 2 ETF ACQCOMP 1 ETF FULL 0 Table 7 9 csCTI Trigger Output Signals The following table lists the trigger output pin connections implemented for csCTI Destination Signal Number ETF TRIGIN 7 ETF F...

Page 596: ...ble to the debugger 0x80000000 Each CTI has two interfaces the trigger interface and the channel interface The trigger interface is the interface between the CTI and other components It has eight trigger signals which are hardwired to other components The channel interface is the interface between a CTI and its CTM with four bidirectional channels The mapping of trigger interface to channel interf...

Page 597: ...ation Info center Debug Clocks The CoreSight system uses several different clocks Port Name is the name of the clock signal inputs described for individual CoreSight debug components in the ARM documentation Signal Name is the name of the clock signal used with other HPS components Table 7 11 CoreSight Clocks Description Signal Name Clock Source Port Name Trace bus clock dbg_at_clk Clock manager A...

Page 598: ...nfo center website Debug Resets The CoreSight system uses several resets Port Name is the name of the clock signal inputs described for individual CoreSight debug components in the ARM documentation Signal Name is the name of the clock signal used with other HPS components Table 7 12 CoreSight Resets Description Signal Name Clock Source Port Name Trace bus reset It resets all registers in ATCLK do...

Page 599: ...center For more information about the CoreSight port names refer to the CoreSight Technology System Design Guide CoreSight Debug and Trace Address Map and Register Definitions The address map resides in the hps html file that accompanies this handbook volume The register definitions reside in separate ARM documentation Click the hps htmllink below to open the file To view the debug related module ...

Page 600: ...se 2013 12 30 December 2013 Minor updates 1 2 November 2012 Added functional description programming model and address map and register definitions sections 1 1 June 2012 Initial release 1 0 January 2012 Altera Corporation CoreSight Debug and Trace Send Feedback 7 19 Document Revision History cv_54007 2013 12 30 ...

Page 601: ...nterfaces Power management supporting self refresh partial array self refresh PASR power down and LPDDR2 deep power down SDRAM Controller Subsystem Block Diagram The SDRAM controller subsystem connects to the MPU subsystem the main switch of the L3 interconnect and the FPGA fabric The memory interface consists of the SDRAM controller the physical layer PHY control and status registers CSRs and the...

Page 602: ...ommunicates with and manages each external memory device The MPFE FPGA to HPS SDRAM interface port has an asynchronous FIFO buffer followed by a synchronous FIFO buffer Both the asynchronous and synchronous FIFO buffers have a read and write data FIFO depth of 8 and a command FIFO depth of 4 The MPU sub system 64 bit AXI and L3 interconnect 32 bit AXI have asynchronous FIFO buffers with read and w...

Page 603: ...rom a memory read 64 bit write data ports transmit write data The FPGA to HPS SDRAM interface supports six command ports allowing up to six Avalon MM interfaces or three AXI interfaces Each command port can be used to implement either a read or write command port for AXI or be used as part of an Avalon MM interface The AXI and Avalon MM interfaces can be configured to support 32 64 128 and 256 bit...

Page 604: ...MM read only Notes to Table 1 Because the AXI protocol allows simultaneous read and write commands to be issued two SDRAM control ports are required to form an AXI interface 2 Because the native size of the data ports is 64 bits extra read and write ports are required to form an AXI interface Memory Controller Architecture The SDRAM controller consists of an MPFE a single port controller and an in...

Page 605: ...scribed below Command Block The command block accepts read and write transactions from the FPGA fabric and the HPS When the command FIFO buffer is full the command block applies backpressure by deasserting the ready signal For each pending transaction the command block calculates the next SDRAM burst needed to progress on that transaction The command block schedules pending SDRAM burst commands ba...

Page 606: ...banks can be put into the correct state to allow a read or write command to be executed and data reordering allowing data transactions to be dispatched even if the data transactions are executed in an order different than they were received from the multiport logic Command Generator The command generator accepts commands from the MPFE and from the internal ECC logic and provides those commands to ...

Page 607: ... should read from the location that was previously written to ensure that the write operation has completed When a port is configured to support AXI the master accessing the port can safely issue a read operation to the same address as a write operation as soon as the write has been acknowledged To keep write latency low writes are acknowledged as soon as the transaction order is guaranteed meanin...

Page 608: ...SDRAM burst has been received Read operations can only be scheduled when sufficient internal memory is free and the port is not occupying too much of the read buffer The multiport scheduling configuration can be updated while traffic is flowing Both priority and weight for a port can be updated without interrupting traffic on a port Updates are used in scheduling decisions within 10 memory clock c...

Page 609: ...hat operations which impact the same address preserve the data integrity The following figure shows the relative timing for a write read write read command sequence performed in order and then the same command sequence performed with data reordering Data reordering allows the write and read operations to occur in bursts without bus turnaround timing delay or bank reassignment Figure 8 3 Data Reord...

Page 610: ...us command has finished execution before the new command has been received Burst Length Support The controller supports burst lengths of 2 4 8 and 16 and data widths of 8 16 and 32 bits for non ECC operation and widths of 24 and 40 operations with ECC enabled The following table shows the type of SDRAM for each burst length Table 8 3 SDRAM Burst Lengths SDRAM Burst Length LPDDR2 DDR2 4 DDR2 DDR3 L...

Page 611: ...imer bank pool Controller ECC enabled sub word writes use two entries The first operation is a read and the second operation is a write These two operations are transferred to the timer bank pool with an address dependency so that the write cannot be performed until the read data has returned This approach ensures that any subsequent operations to the same address from the same port are executed a...

Page 612: ...nterleaved address mapping This interleaving allows smaller data structures to spread across all banks in a chip The following figure shows bank interleave without chip select interleave address decoding Figure 8 5 Bank Interleave Without Chip Select Interleave Address Decoding 0 4 8 12 16 20 24 28 C 9 0 R 15 0 B 2 0 S Bank Interleave with Chip Select Interleave Bank interleave with chip select in...

Page 613: ...e regions are specified by rules containing a starting address and ending address with 1 MB boundaries for both addresses You can override the port defaults and allow or disallow all transactions The memory protection table which is an internal table addressed through the CSR interface contains rules to permit or deny memory access You can configure up to a maximum of twenty rules to control memor...

Page 614: ...a rule allows that transaction to pass Exclusive transactions are security checked on the read operation only A write operation can occur only if a valid read is marked in the internal exclusive table Consequently a master performing an exclusive read followed by a write can write to memory only if the exclusive read was successful Related Information http www arm com Information about TrustZone E...

Page 615: ...rlap between the memory blocks you could specify the address ranges in the two rules of the Memory Protection Table to be mutually exclusive Depending on your desired TrustZone configuration you can add rules to the memory protection table to create multiple blocks of protected or unprotected space SDRAM Power Management The SDRAM controller subsystem supports the following power saving features i...

Page 616: ...be asynchronous with respect to the ddr_dqs_clk memory clock All transactions are synchronized to memory clock domain Table 8 7 SDRAM Controller Subsystem Clock Domains Description Clock Name Clock for PHY ddr_dq_clk Clock for MPFE single port controller CSR access and PHY ddr_dqs_clk Clock for PHY ddr_2x_dqs_clk Clock for CSR interface l4_sp_clk Clock for MPU interface mpu_l2_ram_clk Clock for L3...

Page 617: ... bits are set for you when you configure your implementation using the HPS GUI in Qsys The CSRs are configured using a dedicated slave interface which provides accesses to registers This region controls all SDRAM operation MPFE scheduler configuration and PHY calibration The FPGA fabric interface configuration is programmed into the FPGA fabric and the values of these register bits can be read by ...

Page 618: ...t data 32 256 bit data byteenable Indicates need for additional cycles to complete a transaction Out 1 waitrequest Transaction burst length In 11 burstcount The read and write interfaces are configured to the same size The byte enable size scales with the data bus size Related Information Avalon Interface Specifications Information about the Avalon MM protocol Avalon MM Write Port The Avalon MM wr...

Page 619: ...a byteenable Indicates need for additional cycles to complete a transaction Out 1 waitrequest Transaction burst length In 11 burstcount Related Information Avalon Interface Specifications Information about the Avalon MM protocol Avalon MM Read Port The Avalon MM read ports are standard Avalon MM ports used only to dispatch read operations Each configured Avalon MM read port consists of the signals...

Page 620: ...d to accept the read command Out 1 waitrequest Transaction burst length In 11 burstcount Related Information Avalon Interface Specifications Information about the Avalon MM protocol AXI Port The AXI port uses an AXI 3 interface Each configured AXI port consists of the signals listed in the following table Each AXI interface signal is independent of the other interfaces for all signals including cl...

Page 621: ...mmand In 1 AWVALID Write Data Channel Signals Write data transfer ID In 4 WID Write data In 32 64 128 or 256 WDATA Byte based write data strobe Each bit width corresponds to 8 bit wide transfer for 32 bit wide to 256 bit wide transfer In 4 8 16 32 WSTRB Last transfer in a burst In 1 WLAST Indicates write data strobes are valid In 1 WVALID Indicates ready for write data and strobes Out 1 WREADY Alt...

Page 622: ...eady signal In 1 BREADY Read Address Channel Signals Read identification tag In 4 ARID Read address In 32 ARADDR Read burst length In 4 ARLEN Width of the transfer size In 3 ARSIZE Burst type In 2 ARBURST Indicates ready for a read command Out 1 ARREADY Indicates valid read command In 1 ARVALID SDRAM Controller Subsystem Altera Corporation Send Feedback cv_54008 AXI Port 8 22 2013 12 30 ...

Page 623: ... HPS Memory Interface Architecture The configuration and initialization of the memory interface by the ARM processor is a significant difference compared to the FPGA memory interfaces and results in several key differences in the way the HPS memory interface is defined and configured Boot up configuration of the HPS memory interface is handled by the initial software boot code not by the FPGA prog...

Page 624: ...the boot up code using values provided by the configuration process You may accept the values provided by UniPHY or you may use your own PLL settings If you choose to specify your own PLL settings you must indicate that the clock frequency that UniPHY should use is the requested clock frequency and not the achieved clock frequency calculated by UniPHY The HPS does not support EMIF synthesis genera...

Page 625: ...ry Timing and Board Settings tabs 6 Add other Qsys components in your Qsys design and make the appropriate bus connections 7 Save the Qsys project 8 Click Generate on the Generation tab to generate the Qsys design Creating a Top Level File and Adding Constraints This topic describes adding your Qsys system to your top level design and adding constraints to your design 1 Add your Qsys system to you...

Page 626: ...tion of a Preloader image 1 At the command shell change the directory to design path software spl_bsp 2 To compile the Preloader sources and generate a Preloader image type make all The Preloader image preloader mkpimage bin is created in the design path software spl_bsp folder after the compliation You must regenerate the Preloader image if any of the source files bsp c or h files change Note Deb...

Page 627: ... Enabling Simple Memory Test To enable the simple memory test follow these steps 1 When you create the bsp file in the BSP Editor turn on HARDWARE_DIAGNOSTIC in the spl debug window to enable the simple memory test Altera Corporation SDRAM Controller Subsystem Send Feedback 8 27 Enabling Simple Memory Test cv_54008 2013 12 30 ...

Page 628: ...ze open the file design folder spl_bsp uboot socfpga include configs socfpga_ cyclone5 h in a text editor and change the PHYS_SDRAM_1_SIZE parameter at line 292 to specify your actual memory size in bytes SDRAM Controller Subsystem Altera Corporation Send Feedback cv_54008 Enabling Simple Memory Test 8 28 2013 12 30 ...

Page 629: ...ng open the file project directory hps_isw_ handoff sequencer_defines hin a text editor 2 Locate the line define RUNTIME_CAL_REPORT 0 and change it to define RUNTIME_CAL_REPORT 1 Figure 8 7 Semihosting Printout With Debug Support Enbled Analysis of Debug Report The following analysis will help you interpret the debug report Altera Corporation SDRAM Controller Subsystem Send Feedback 8 29 Enabling ...

Page 630: ...roup 0 Rank 0 End VFIFO 6 Phase 5 Delay 9 SEQ C DQS Enable Group 0 Rank 0 Center VFIFO 6 Phase 2 Delay 1 Analysis of DQS Enable results A VFIFO tap is 1 clock period a phase is 1 8 clock period 45 degrees and delay is nominally 25ps per tap The DQSen window is the difference between the start and end for the above example assuming a frequency of 400 MHz 2500ps that calculates as follows start is 5...

Page 631: ...for exact incremental delay values for delay chains Related Information Functional Description UniPHY Writing a Predefined Data Pattern to SDRAM in the Preloader You can include your own code to write a predefined data pattern to the SDRAM in the preloader for debugging purposes 1 Include your code in the following file project_folder software spl_bsp uboot socfpga arch arm cpu armv7 socfpga spl c...

Page 632: ... 1 num_address cnt addr base cnt pointer arith sync addr data_temp i data_temp i ROTATE_RIGHT data_temp i read for cnt 0 i num_address cnt i 1 num_address cnt cnt addr base cnt pointer arith sync read_data addr printf Address X Expected 08X Read 08X n addr expected_data i read_data if expected_data i read_data puts FAILED n n hang expected_data i ROTATE_RIGHT expected_data i End Of Code SDRAM Cont...

Page 633: ...ffsets relative to the base address of each module instance Related Information Introduction to Cyclone V Hard Processor System HPS on page 1 1 Base addresses of all HPS modules Cyclone V SoC HPS Address Map and Register Definitions Register and field descriptions for all HPS modules Document Revision History Changes Version Date Added Generating a Preloader Image for HPS with EMIF section Added D...

Page 634: ...ncy and maximum throughput refer to the Clock Manager chapter ISO 9001 2008 Registered 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are...

Page 635: ...ted Information Interconnect on page 4 1 For more information about security refer to the Interconnect chapter Functional Description of the On Chip RAM The on chip RAM serves as a general purpose memory accessible from the FPGA The on chip RAM uses an 64 bit slave interface The slave interface supports transfers between memory and the NIC 301 L3 interconnect All reads and writes are serviced in o...

Page 636: ...ed by the l3_main_clk interconnect clock The entire RAM is either secure or nonsecure Security is enforced by the NIC 301 L3 interconnect Figure 9 2 Boot ROM Block Diagram S Boot ROM NIC 301 L3 Interconnect M Data Interface Related Information Interconnect on page 4 1 For more information about security refer to the Interconnect chapter Functional Description of the Boot ROM The boot ROM is used o...

Page 637: ... There are no registers for on chip memory The address map resides in the hps html file that accompanies this handbook volume Click the link to open the file To view the module descriptions and base addresses scroll to and click the links for the following module instances rom ocram Related Information Introduction to Cyclone V Hard Processor System HPS on page 1 1 The base addresses of all module...

Page 638: ...Changes Version Date Initial release 1 0 January 2012 Altera Corporation On Chip Memory Send Feedback 9 5 Document Revision History cv_54009 2013 12 30 ...

Page 639: ...t through the command and data slave interface The host accesses the flash controller s control and status registers CSRs through the register slave interface The flash controller handles all command sequencing and flash device interactions The bootstrap interface supports configuration of the NAND flash controller when booting the HPS from NAND flash memory The flash controller generates interrup...

Page 640: ... after the HPS receives power and the flash device is stable During initialization the flash controller queries the flash device and configures itself according to one of the following flash device types ONFI 1 0 compliant devices Legacy non ONFI NAND devices The NAND flash controller identifies ONFI compliant connected devices using ONFI discovery protocol by sending the Read Electronic Signature...

Page 641: ...ice configuring direct read access so the processor can boot from that page The processor can start reading from the first page of the device which is the expected location of the preloader software The system manager can bypass this step by asserting bootstrap_inhibit_b0p0_load before reset is deasserted Note 7 The flash controller sends the reset command to the device 8 The flash controller sets...

Page 642: ... devices_connected 0 indicating an 8 bit NAND flash device device_width 1 indicating a single plane device number_of_planes The value of this register must reflect the flash device s page main area size device_main_area_size The value of this register must reflect the flash device s page spare area size device_spare_area_size The value of this register must reflect number of pages per block in the...

Page 643: ...s four times the frequency of nand_clk For more information about the clock inputs refer to the Clock Manager chapter in the Cyclone V Device Handbook Volume 3 Resets The NAND flash controller has one reset signal nand_flash_rst_n The reset manager drives this signal to the NAND flash controller on a cold or warm reset Before the NAND flash controller comes out of the reset state the pin multiplex...

Page 644: ...t This action provides the flash address parameters to the NAND flash controller 2 Perform 32 bit read or write in the Data register at offset 0x10 of the data command slave port 3 Perform additional 32 bit reads and writes if they are in the same page and block in flash memory It is unnecessary to write to the control register for every data transfer if a group of data transfers targets the same ...

Page 645: ... to perform a boot read Use MAP00 commands in read modify write RMW operations to read or write any word in the buffer MAP00 commands allow a direct data path to the page buffer in the device The host can access the page buffer directly using the MAP00 commands only if there are no other MAP01 or MAP10 commands active on the NAND flash controller Related Information MAP00 Address Mapping on page 1...

Page 646: ...Commands MAP01 commands transfer complete pages between the host memory and a specific page of the NAND flash device Because the NAND flash controller supports only page addresses the entire page must be read or written at once The actual number of commands required depends on the size of the data transfer You must use the same address until the entire page is transferred even if multiple commands...

Page 647: ...ntroller while DMA is enabled the flash controller discards the request and generates an unsup_cmd interrupt MAP10 Commands MAP10 commands provide an interface to the control plane of the NAND flash controller MAP10 commands control special functions of the flash device such as erase lock unlock copy back and page spare area access Data passed in this command pathway targets the NAND flash control...

Page 648: ...iates unlock 0x11 Initiates a lock of all blocks 0x21 Initiates a lock tight of all blocks 0x31 Sets up for spare area access 0x41 Sets up for default area access 0x42 Sets up for main spare area access 0x43 Loads page to the buffer for a RMW operation 0x60 20 M depends on the number of pages per block in the device M ceil log2 device pages per block Therefore use the following values 32 pages per...

Page 649: ...ing MAP10 pipeline read or write commands DMA must be disabled the flag bit of the dma_enable register in the dma group must be set to 0 DMA must be disabled because the host is directly transferring data from and to the flash device through the flash controller MAP11 Commands MAP11 commands provide direct access to the NAND flash controller s address and control cycles allowing software to issue ...

Page 650: ...s one DMA transfer per MAP10 command over the DMA master interface When the DMA is disabled all operations with the flash controller occur through the data command slave interface The NAND flash controller supports up to four outstanding DMA commands and ignores additional DMA commands If software issues more than four outstanding DMA commands the flash controller issues the unsup_cmd interrupt On...

Page 651: ...ock boundary If it does the flash controller generates an unsupported command unsup_cmd interrupt and drops the command Data DMA commands are typically multi page read and write commands with an associated pointer in host memory The multi page data is transferred to or from the host memory starting from the host memory pointer Data DMA uses the flash_burst_length register in the dma group to deter...

Page 652: ...w 23 0x0 0x2 0x0 Command 7 0 11 8 15 12 31 16 0x0 0x3 0x2 0x0 Data 21 M depends on the number of pages per block in the device M ceil log2 device pages per block Therefore use the following values 32 pages per block M 5 64 pages per block M 6 128 pages per block M 7 256 pages per block M 8 384 pages per block M 9 512 pages per block M 9 22 The buffer address in host memory which must be aligned to...

Page 653: ...Indexed Addressing on page 10 5 Burst DMA Command on page 10 15 System Manager on page 14 1 Burst DMA Command You can initiate a DMA transfer by sending a command to the NAND flash controller as a burst transaction of four 16 bit accesses This form of DMA command might be useful for initiating DMA transfers from custom IP in the FPGA fabric Most processor cores cannot use this form of DMA command ...

Page 654: ...forms one distinct operation on the flash controller The host software can chain these command descriptors sequentially as a linked list of command descriptors and initiate command DMA to operate on the descriptor chain The DMA controller fetches a descriptor carres out the operation as described in the descriptor writes the status of the operation completed generates an interrupt if required and ...

Page 655: ... Command DMA issues an interrupt desc_comp_channel x for channel x if the Int bit is set in the command flags field After issuing the interrupt the next descriptor is fetched if the Cont bit is set in the command flags field This descriptor processing happens in parallel for all channels that have been enabled by a MAP10 command DMA command TheMAP10commandcanbesentasfourseparatesingle beattransact...

Page 656: ... 0x0 Reserved Table 10 15 Transaction 4 Address Encoding 7 0 23 8 25 24 27 26 31 28 0x0 Reserved Res 0x2 0x0 Table 10 16 Transaction 4 Data 3 0 7 4 15 8 31 16 0x0 0xb 0x0 Reserved Related Information Multitransaction DMA Commands on page 10 17 Out Of Order DMA Commands The flash controller ignores out of order DMA commands If transactions are not in the expected order the flash controller resets i...

Page 657: ...flash controller The flash controller processes the last descriptor and continues with the appended descriptors Whenever a DMA channel receives error indication the status field of the descriptor is updated with the error information The affected channel stops any subsequent descriptors for the channel and sets the error bit in the cmd_dma_channel_error register The channel does not execute any sy...

Page 658: ...mand which specifies the flash controller operations such as erase data DMA or copyback The command type field dictates if additional information is needed for data DMA commands such as the memory address or burst length specified in the command flag field Command type System memory address required for data DMA commands Memory pointer The flash controller updates this field when the command opera...

Page 659: ... from or to system memory Valid values depend on the host data bus width Typically single 4 beat 8 beat and 16 beat bursts are supported For example for 32 bit data bus the valid values are 4 16 32 and 64 bytes Burst length 7 0 Related Information Command Descriptor Fields on page 10 20 Status Fields Description Name Bits When set denotes that controller has updated status information and the oper...

Page 660: ...itiated on a locked block Valid only when the Fail bit is set Locked Block 2 Denotes that intended operation is not supported at the current controller state Valid only when Fail bit is set UnsupportedCommand 1 Reserved Reserved 0 Related Information Command Descriptor Fields on page 10 20 Synchronized Data Transfers Sync flag pointer and sync arguments in the descriptor are used to synchronize da...

Page 661: ... and performs an Increment operation The descriptor flash command is considered a NOP and ignored This bit is valid only when the Valid bit is set Setting of this bit also means that the Int bit in the Commands Flags field is ignored SyncInt 4 Must be set to zero by firmware Reserved 15 5 Value to be stored to the sync buffer flag upon the successful completion of the operation unless the type is ...

Page 662: ...porates ECC logic to calculate and correct bit errors The flash controller uses a Bose Chaudhuri Hocquenghem BCH algorithm for detection of multiple errors in a page The NAND flash controller supports 512 and 1024 byte ECC sectors The flash controller inserts ECC check bits for every 512 or 1024 bytes of data depending on the selected sector size After 512 or 1024 bytes the flash controller writes...

Page 663: ...e NAND flash controller inserts ECC check bits in the data stream on writes and strips ECC check bits on reads Software does not need to manage the ECC sectors when writing a page ECC checking is performed by the flash controller so software simply transfers the data If ECC is turned off the NAND flash controller does not read or write ECC check bits Figure 10 2 Main Area Transfer Mode Programming...

Page 664: ... bad block markers in the first two bytes in the spare area set the spare_area_skip_bytes register to 2 When the flash controller writes the last sector of the page that overlaps with the spare area it starts at offset 2 in the spare area skipping the bad block marker at offset 0 A value of 0 default specifies that no bytes are skipped The value of spare_area_skip_bytes must be an even number For ...

Page 665: ...ntains ECC error correction information in the max_errors_b0 and uncor_err_b0 fields At the end of data correction for the transaction in progress ECCCorInfo_b01 holds the maximum number of corrections applied to any ECC sector in the transaction In addition this register indicates whether the transaction as a whole has correctable errors uncorrectable errors or no errors at all A transaction has ...

Page 666: ...ling mode the software must also program the additional registers to select the times and frequencies of the polling Program the following registers in the config group Set the rb_pin_enabled register to the desired mode of operation for each flash device For polling mode set the load_wait_cnt register to the appropriate value depending on the speed of operation of the NAND flash controller and th...

Page 667: ... use other means to ensure that the initialization registers are set up correctly Related Information Discovery and Initialization on page 10 2 Device Operation Control This section provides a list of registers that you need to program while choosing to use multi plane or cache operations on the device If the device does not support multi plane operations or cache operations then these registers c...

Page 668: ...out ECCs refer to ECC Related Information ECC on page 10 24 NAND Flash Controller Performance Registers These registers specify the size of the bursts on the device interface which maximizes the overall performance on the NAND flash controller Initializetheflash_burst_lengthregisterinthedmagrouptoavaluewhichmaximizestheperformance of the device interface by minimizing the number of bursts required...

Page 669: ...mand c page_xfer_inc at the end of each page data transfer d program_fail if failure e pipe_cpybck_cmd_comp f program_comp g dma_cmd_comp If DMA enabled 9 For a read command a pipe_cmd_err if the pipeline sequence is broken by a MAP01 command b page_xfer_inc at the end of each page data transfer c pipe_cpybck_cmd_comp d load_comp e ecc_uncor_error if failure f dma_cmd_comp If DMA enabled Timing Re...

Page 670: ...ster multiplane_operation in the config group must be reset After device completes erase operation the controller generates an erase_comp interrupt If the erase operation fails the erase_fail interrupt is issued The failing block s address is updated in the err_block_addr0 register in the status group Multi Plane Erase For multi plane erases the number_of_planes register in the config group holds ...

Page 671: ...be less than the end block address Otherwise the NAND flash controller exhibits undetermined behavior Locking All Memory Blocks To lock the entire memory 1 Write to the command register setting the CMD_MAP field to 2 and the BLK_ADDR field to any memory address 2 Write 0x21 to the Data register Setting Lock Tight on All Memory Blocks After the lock tight is applied unlocked areas cannot be locked ...

Page 672: ...spare area To configure default area access 1 Write to the command register setting the CMD_MAP field to 2 and the BLK_ADDR field to any block 2 Write 0x42 to the Data register The NAND flash controller determines the default area transfer mode from the setting of the transfer_spare_reg register in the config group If it is set to 1 then the transfer mode becomes main spare area otherwise it is ma...

Page 673: ...RMW operations Software must update the ECC during RMW operations Note For a read modify write command to work with hardware ECC the entire page must be read into system memory modified then written back to flash without relying on the RMW feature Note Read Modify Write Operation Flow 1 The flow starts by reading a page from the memory Write to the command register setting the CMD_MAP field to 2 a...

Page 674: ...hold until the current copy back completes For a multi plane device if the flag bit in the multiplane_operation register in the config group is set to 1 multi plane copy back is available as an option In this case the block address specified must be plane aligned and the value PP must specify the total number of pages to copy as a multiple of the number of planes The block address continues increm...

Page 675: ...continuous streaming of data into the flash device MAP01 commands must read or write pages in the same sequence that the pipelined commands were issued to the NAND flash controller If the host issues multiple pipeline commands pages must be read or written in the order the pipeline commands were issued It is not possible to read or write pages for a second pipeline command before completing the fi...

Page 676: ...mand set requires the NAND flash controller to issue a load command for the last page in the pipeline read command a load_comp interrupt is generated after the last page load operation completes For pipeline write commands if any page program results in a failure in the device a program_fail interrupt is issued The failing page s block and page address is updated in the err_block_addr0 and err_pag...

Page 677: ...r where the value 1 sets this command as a write ahead and PP is the number of pages to pre write The pages must not cross a block boundary If a block boundary is crossed the NAND flash controller generates an unsupported command unsup_cmd interrupt and drops the command After you set up the write ahead use a MAP01 command to actually write the data In the MAP01 command specify the same starting a...

Page 678: ...ument Revision History Changes Version Date Maintenance release 2013 12 30 December 2013 Supports one 8 bit device Show additional supported block sizes Bad block marker handling 1 2 November 2012 Added programming model section 1 1 May 2012 Initial release 1 0 January 2012 NAND Flash Controller Altera Corporation Send Feedback cv_54010 Document Revision History 10 40 2013 12 30 ...

Page 679: ...and 8 bit in some packages as described in MMC Support Matrix Integrated descriptor based direct memory access DMA Internal 4 KB receive and transmit FIFO buffer The SD MMC controller does not directly support voltage switching card interrupts or back end power control of eSDIO card devices However you can connect these signals to general purpose I Os GPIOs The SD MMC controller does not contain a...

Page 680: ...atrix Table 11 2 MMC Support Matrix Bus Speed Modes Supported Bus Modes Supported Voltages Supported Max Data Rate MBps Max Clock Speed MHz Card Device Type High Speed Default Speed 8 bit 4 bit 1 bit SPI 30 1 8 V 3 3 V 2 5 20 MMC 10 20 RSMMC 25 50 31 MMCPlus 6 5 50 MMCMobile 28 SDR25 speed mode requires 1 8 V signaling Note that even if a card supports UHS I modes for example SDR50 SDR104 DDR50 it...

Page 681: ...A protocols on the controller and provides clock management through the clock control block The interrupt control block for generating an interrupt connects to the generic interrupt controller in the ARM Cortex A9 microprocessor unit MPU subsystem Figure 11 1 SD MMC Controller Connectivity Slave Interface Master Interface MPU Subsystem Card Bus I O Pins FIFO Buffer Control Synchronizer Storage FIF...

Page 682: ...a Block CRC Command Response Block Read Operation Multiple Block Read Operation Data Stop Operation From Host to Card From Card to Host Data from Card to Host Stop Command Stops Data Transfer The following figure illustrates an example of a command token sent by the host in a multiple block write operation Figure 11 3 Multiple Block Write Operation Command Response sdmmc_cclk_out sdmmc_cmd sdmmc_d...

Page 683: ...lkdiv Clock enable clkena Clock source clksrc Timeout tmout Card type ctype The hardware resets the start_cmd bit after the CIU accepts the command If a host write to any of these registers is attempted during this locked time the write is ignored and the hardware lock write error bit hle is set to 1 in the raw interrupt status register rintsts Additionally if the interrupt is enabled and not mask...

Page 684: ... Receive FIFO buffer data request Transmit FIFO buffer data request Data transfer over Command done Response error The int_enable bit of the ctrl register is set to 0 on power on and the intmask register bits are set to 0x0000000 which masks all the interrupts Interrupt Setting and Clearing The Receive FIFO Data Request and Transmit FIFO Data Request interrupts are set by level sensitive interrupt...

Page 685: ...l memory space of the system memory and consists of complete or partial data The buffer status is maintained in the descriptor Data chaining refers to data that spans multiple data buffers However a single descriptor cannot span multiple data buffers A single descriptor is used for both reception and transmission The base address of the list is written into the descriptor list base address registe...

Page 686: ...riptor Fields on page 11 8 Refer to this table for information about each of the bits of the descriptor Internal DMA Controller Descriptor Fields The DES0 field in the internal DMA controller descriptor contains control and status information Table 11 4 Internal DMA Controller DES0 Descriptor Field Description Name Bits When set to 1 this bit indicates that the descriptor is owned by the internal ...

Page 687: ...ond buffer address When this bit is set to 1 BS2 DES1 25 13 must be all zeros Second Address Chained CH 4 When set to 1 this bit indicates that this descriptor contains the first buffer of the data If the size of the first buffer is 0 next descriptor contains the beginning of the data First Descriptor FS 3 When set to 1 this bit indicates that the buffers pointed to by this descriptor are the last...

Page 688: ...r 1 BAP1 31 0 The DES3 descriptor field contains the address pointer to the next descriptor if the present descriptor is not the last descriptor in a chained descriptor structure or the second buffer address for a dual buffer structure Table 11 7 Internal DMA Controller DES3 Descriptor Field Description Name Bits These bits indicate the physical address of the second buffer when the dual buffer st...

Page 689: ...tains all the bits that might cause an interrupt The internal DMA controller interrupt enable register idinten contains an enable bit for each of the events that can cause an interrupt to occur There are two summary interrupts the normal interrupt summary bit nis and the abnormal interrupt summary bit ais in the idsts register The nis bit results from a logical OR of the transmit interrupt ti and ...

Page 690: ... controller goes to idle state after setting the ri bit or the ti bit of the idsts register Depending on the descriptor structure dual buffer or chained the appropriate starting address of descriptor is loaded If it is the second data buffer of dual buffer descriptor the descriptor is not fetched again Abort During Internal DMA Transfer If the host issues an SD SDIO STOP_TRANSMISSION command CMD12...

Page 691: ...ur bytes For example if the bytcnt register 13 the number of bytes indicated in the descriptor must be rounded up to 16 because the length field must always be a multiple of four bytes PBL and Watermark Levels This table shows legal PBL and FIFO buffer watermark values for internal DMA controller data transfer operations Table 11 8 PBL and Watermark Levels TX RX FIFO Buffer Watermark Value PBL Num...

Page 692: ...d as if it were a new data transfer command When issuing SD SDIO card reset commands GO_IDLE_STATE GO_INACTIVE_STATE or CMD52_reset while a card data transfer is in progress the software must set the stop abort command bit stop_abort_cmd in the cmd register to 1 so that the controller can stop the data transfer after issuing the card reset command If the card clock is stopped because the FIFO buff...

Page 693: ...ommand from BIU When the BIU sends a new command to the CIU the start_cmd bit is set to 1 in the cmd register Internally generated send_auto_stop When the data path ends the SD SDIO STOP command request is loaded Interrupt request IRQ response with relative card address RCA 0x000 When the command path is waiting for an IRQ response from the MMC and a send irq response request is signaled by the BI...

Page 694: ...it is set to 1 a 136 bit long response is received if it is set to 0 a 48 bit short response is received 4 check_response_crc If this bit is set to 1 the command path compares CRC 7 received in the response with the internally generated CRC 7 If the two do not match the response CRC error is signaled to the BIU that is the rcrc bit is set to 1 in the rintsts register Send Response to BIU If the re...

Page 695: ...the CCS Polling the CCS CE ATA card devices generate the CCS to notify the host controller of the normal ATA command completion or ATA command termination After receiving the response from the card the command path state machine performs the functions illustrated in the following figure according to cmd register bit values Figure 11 7 CE ATA Command Path State Machine Response End Bit wait_tncc Tr...

Page 696: ...ttern on the CMD line The host can send the CCSD command while waiting for the CCS or after a CCS timeout happens After sending the CCSD pattern the controller sets the cmd bit in the rintsts register and also generates an interrupt to the host if the Command Done interrupt is not masked Within the CIU block if the send_ccsd bit in the ctrl register is set to 1 on the same clock cycle as CCS is sa...

Page 697: ...r or response CRC error If a response is not received from the card because of a response timeout data is not transmitted Depending upon the value of the transfer mode bit transfer_mode in the cmd register the data transmit state machine puts data on the card data bus in a stream or in blocks Figure 11 8 Data Transmit State Machine Data Tx Idle load_new_cmd data_expected Write Data Block Transfer ...

Page 698: ...not equal to the value of the block_size register The data transmit state machine sends data in blocks where the number of bytes in a block equals the block size including the internally generated CRC 16 value If the ctype register is set to 1 bit 4 bit or 8 bit data transfer the data is transmitted on 1 4 or 8 data lines respectively and CRC 16 is separately generated and transmitted on 1 4 or 8 ...

Page 699: ... Data Block Read Wait Stream Data Read A stream read data transfer occurs if the transfer_mode bit in the cmd register is set to 1 at which time the data path receives data from the card and writes it to the FIFO buffer If the FIFO buffer becomes full the card clock stops and restarts once the FIFO buffer is no longer full An open ended stream read data transfer occurs if the bytcnt register is se...

Page 700: ...d register is set to 1 the SD SDIO STOP command is internally generated when the last data block is transferred where no extra bytes are transferred from the card The end bit of the STOP command might not exactly match the end bit of the last data block If the requested block size for data transfers to cards is less than 4 16 or 32 bytes for 1 bit 4 bit or 8 bit data transfer modes respectively th...

Page 701: ...aded in the command path after all data blocks are transmitted Otherwise the STOP command is loaded in the command path so that the end bit of the STOP command is sent after the end bit of the CRC status is received Precaution for host software during auto stop When an AUTO_STOP command is issued the host software must not issue a new command to the controller until the AUTO_STOP command is sent b...

Page 702: ...block No 0 Multiple block read Open ended multiple block No 0 Multiple block write Pre defined multiple block No 0 Multiple block write Non Data Transfer Commands that Use Data Path Some SD SDIO non data transfer commands commands other than read and write commands also use the data path 32 The condition under which the transfer mode is set to block transfer and byte_count is equal to block size i...

Page 703: ...ter Setup Stuff bits Stuff bits Stuff bits Stuff bits 32 bit write protect data address Stuff bits blksiz Register Setup 8 4 64 Num_ bytes 33 4 16 bytcnt Register Setup 8 4 64 Num_ bytes 33 4 16 Clock Control Block The clock control block provides different clock frequencies required for SD MMC CE ATA cards The clock control block has one clock divider which is used to generate different card cloc...

Page 704: ...r the following conditions the card clock is stopped or disabled Clock can be disabled by writing to the clkena register When low power mode is selected and the card is idle for at least eight clock cycles FIFO buffer is full data path cannot accept more data from the card and data transfer is incomplete to avoid FIFO buffer overflow FIFO buffer is empty data path cannot transmit more data to the ...

Page 705: ...ead data transfer if the all bit data line does not have a start bit the data path signals a data SBE to the BIU and waits for a data timeout after which it signals that the data transfer is done Data CRC error during a read data block transfer if the CRC 16 received does not match with the internally generated CRC 16 the data path signals a data CRC error to the BIU and continues with the data tr...

Page 706: ...ese phase shifters provide up to eight phases shift which include 0 45 90 135 180 225 270 and 315 degrees The sdmmc_sample_clk clock can be driven by the output from the phase shifter The selections of phase shift degree and sdmmc_sample_clk source are done in the system manager For information about setting the phase shift and selecting the source of the sdmmc_sample_clk clock refer to the Clock ...

Page 707: ...er to the card Out 1 sdmmc_cclk_out Card command In Out 1 sdmmc_cmd External device power enable Out 1 sdmmc_pwren Card data In Out 8 sdmmc_data SD MMC Controller Programming Model Initialization After the power and clock to the controller are stable the controller active low reset is asserted The reset sequence initializes the registers FIFO buffer pointers DMA interface controls and state machin...

Page 708: ...y resetting the appropriate bits to 0 in the intmask register 4 Set the int_enable bit of the ctrl register to 1 Altera recommends that you write 0xFFFFFFFF to the rintsts register to clear any pending interrupts before setting the int_enable bit to 1 Note 5 Discover the card stack according to the card type For discovery you must restrict the clock frequency to 400 kHz in accordance with SD MMC C...

Page 709: ... do not need to be changed with every SD MMC CE ATA command Set them to a typical value according to the SD MMC CE ATA specifications Related Information Clock Setup on page 11 34 Refer to this section for information on setting the clock source assignments Enumerated Card Stack on page 11 31 Refer to this section for information on discovering the card stack according to the card type Enumerated ...

Page 710: ...pecifications Part 1 Physical Layer Simplified Specification Version 2 00 If no response is received proceed to step e c Send the SD_SEND_OP_COND ACMD41 command with the following arguments Bit 31 0x0 reserved bits Bit 30 0x1 high capacity status Bit 29 25 0x0 reserved bits Bit 24 0x1 S18R supports voltage switching for 1 8V Bit 23 0 supported voltage range d If a response is received to the previ...

Page 711: ...he card is a CE ATA 1 0 card device or an MMC card device by sending the RW_REG command If a response is received and the response data contains the CE ATA signature the card is a CE ATA 1 0 card device Otherwise the card is an MMC card device 5 At this point the software has determined the card type as SD SDHC SDIO or SDIO COMBO Now it must enumerate the card stack according to the type that has ...

Page 712: ...meters do not change until any ongoing data transfer is complete start_cmd Initiates the command 5 Wait until the start_cmd and update_clk_regs_only bits change to 0 There is no interrupt when the clock modification completes The controller does not set the command_done bit in the rintsts register upon command completion The controller might signal a hardware lock error if it already has another c...

Page 713: ...the ctrl register to 1 first and then resetting the rintsts register to 0 using another write to clear any resultant interrupt Enabling FIFO Buffer ECC To protect the FIFO buffer data with ECC you must enable the ECC feature before performing any operations with the SD MMC controller Perform the following steps to enable the FIFO buffer ECC feature 1 Verify there are no commands committed to the c...

Page 714: ...there is a hardware lock error 5 Wait for command execution to complete After receiving either a response from a card or response timeout the controller sets the command_done bit in the rintsts register to 1 Software can either poll for this bit or respond to a generated interrupt if enabled 6 Check if the response timeout boot acknowledge received bar rcrc or re bit is set to 1 Software can eithe...

Page 715: ...to 1 unless the current command is to query status or stop data transfer when transfer is in progress 1 wait_prvdata_complete 1 if the response includes a valid CRC and the software is required to crosscheck the response CRC bits 0 otherwise 1 or 0 check_response_crc Data Transfer Commands Data transfer commands transfer data between the memory card and the controller To issue a data command the c...

Page 716: ... the FIFO buffer 3 Receive FIFO data request bit rxdr The FIFO buffer threshold for receiving data is reached software is expected to read data from the FIFO buffer 4 hto The FIFO buffer is empty during transmission or is full during reception Unless software corrects this condition by writing data for empty condition or reading data for full condition the controller cannot continue with data tran...

Page 717: ... bus the Command Done interrupt is generated 6 Software must check for data error interrupts reported in the dcrc bds sbe and ebe bits of the rintsts register If required software can terminate the data transfer by sending an SD SDIO STOP command 7 Software must check for host timeout conditions in the rintsts register Receive FIFO buffer data request Data starvation from host the host is not read...

Page 718: ... Does not need to update clock parameters 0 update_clk_regs_only Data command 1 data_expected For one card 1 card_number Block transfer 0 transfer_mode 1 for a card reset command such as the SD SDIO GO_IDLE_STATE command 0 otherwise 0 send_initialization 1 for a command to stop data transfer such as the SD SDIO STOP_TRANSMISSION command 0 otherwise 0 stop_abort_cmd Refer to Auto Stop for informati...

Page 719: ...ftware should write data continuously until the FIFO buffer is full 5 Write the cmd register with the parameters listed in cmd Register Settings for Single Block and Multiple Block Write For SD and MMC cards use the SD SDIO WRITE_BLOCK CMD24 command for a single block write and the WRITE_MULTIPLE_BLOCK CMD25 command for a multiple block writes For SDIO cards use the IO_RW_EXTENDED command for both...

Page 720: ... Write Default Comment Value Parameter This bit resets itself to 0 after the command is committed accepted by the BIU 1 start_cmd Choose the value based on speed mode being used 1 or 0 use_hold_reg Does not need to update clock parameters 0 update_clk_regs_only Data command 1 data_expected For one card 1 card_number Block transfer 0 transfer_mode Can be 1 but only for card reset commands such as S...

Page 721: ...m write requires the same steps as the block write mentioned in Single Block or Multiple Block Write except for the following bits in the cmd register transfer_mode 0x1 for stream transfer cmd_index 11 SD SDIO CMD11 Related Information Single Block or Multiple Block Read on page 11 38 Refer to this section for more information about a stream read Single Block or Multiple Block Write on page 11 41 ...

Page 722: ...mation refer to Non Data Transfer Commands Related Information Non Data Transfer Commands on page 11 35 Refer to this section for information on the STOP_TRANSMISSION command ABORT The ABORT command can only be used with SDIO cards To abort the function that is transferring data program the ABORT function number in the ASx 2 0 bits at address 0x06 of the card common control register CCCR in the ca...

Page 723: ...DIO ABORT Command Table 11 21 cmdarg Register Settings for SD SDIO ABORT Command Value Contents Bits 1 R W flag 31 0 for access to the CCCR in the card device Function number 30 28 1 if needed to read after write RAW flag 27 Don t care 26 0x06 Register address 25 9 Don t care 8 Function number to abort Write data 7 0 Internal DMA Controller Operations For better performance you can use the interna...

Page 724: ...ection for information about the Internal DMA Controller Transmission Sequences Internal DMA Controller Reception Sequences on page 11 47 Refer to this section for information about the Internal DMA Controller Reception Sequences Internal DMA Controller Transmission Sequences To use the internal DMA controller to transmit data perform the following steps 1 The host sets up the Descriptor fields DE...

Page 725: ...he internal DMA controller waits for the CD bit in the rintsts register to be set to 1 with no errors from the BIU This condition indicates that a transfer can be done 7 The internal DMA controller engine waits for a DMA interface request from the BIU The BIU divides each transfer into smaller chunks Each chunk is an internal request to the DMA This request is generated based on the receive thresh...

Page 726: ...y polling until the dto bit is set to 1 in the rintsts register To determine the number of pending bytes to transfer read the transferred CIU card byte count tcbcnt register of the controller Subtract this value from the total transfer size You use this number to resume the transfer properly Resume To resume the data transfer perform the following steps 1 Check that the card is not in a transfer s...

Page 727: ... 0 The function has no data for the transfer If the data transfer is a read the controller waits for data After the data timeout period it issues a data timeout error Related Information www sdcard org To learn more about how SD technology works visit the SD Association website Single Block or Multiple Block Read on page 11 38 Refer to this section for more information about writing to the cmd reg...

Page 728: ...he RW_REG or CMD39 command By default the MMC block size is 512 bytes indicated by bits 1 0 of the srcControl register inside the CE ATA card device The host can negotiate the use of a 1 KB or 4 KB MMC block sizes The card indicates MMC block sizes that it can support through the srcCapabilities register in the MMC the host reads this register to negotiate the MMC block size Negotiation is complet...

Page 729: ...Register Settings for ATA Task File Transfer on page 11 51 Refer to this table for information on how to set these registers Register Settings for ATA Task File Transfer Table 11 23 cmdarg Register Settings for ATA Task File Transfer Comment Value Bit Set to 0 for read operation or set to 1 for write operation 1 or 0 31 Reserved bits set to 0 by host processor 0 30 24 Starting register address for...

Page 730: ...e Bit Reserved bits set to 0 0 31 16 For accessing entire task file 16 8 bit registers Block size of 16 bytes 16 15 0 block_size Table 11 26 bytcnt Register Settings for ATA Task File Transfer Comment Value Bit For accessing entire task file 16 8 bit registers Byte count value of 16 is used with the block size set to 16 16 31 0 ATA Payload Transfer Using the RW_MULTIPLE_BLOCK RW_BLK Command This c...

Page 731: ...0 Table 11 28 cmd Register Settings for ATA Payload Transfer Comment Value Bits 1 start_cmd CCS is expected Set to 1 for the RW_BLK command if interrupts are enabled in CE ATA card device the nIEN bit is set to 0 in the ATA control register 1 ccs_expected Set to 1 for a RW_BLK or RW_REG read command 0 or 1 read_ceata_device No clock parameters update command 0 update_clk_regs_only 0 card_num No in...

Page 732: ...block_size 31 0 CE ATA CCS This section describes disabling the CCS recovery after CCS timeout and recovery after I O read transmission delay NACIO timeout Disabling the CCS While waiting for the CCS for an outstanding RW_BLK command the host can disable the CCS by sending a CCSD command Send a CCSD command the controller sends the CCSD command to the CE ATA card device if the send_ccsd bit is set...

Page 733: ...following steps to recover from the timeout If the CCS is expected from the CE ATA card device that is the ccs_expected bit is set to 1 in the cmd register follow the steps in Recovery after CCS Timeout If the CCS is not expected from the CE ATA card device perform the following steps 1 Send an external STOP command 2 Terminate the data transfer between the controller and CE ATA card device Relate...

Page 734: ...mand for the data transfer The WRITE DMA EXT Command The WRITE DMA EXT command writes a number of logical blocks of data to the card device using the Data Out data transfer protocol The host uses a RW_REG command to issue the ATA command and the RW_BLK command for the data transfer The STANDBY IMMEDIATE Command This ATA command causes the card device to immediately enter the most aggressive power ...

Page 735: ...mdarg register settings Bit 31 set to 1 Bits 7 2 set to 4 All other bits set to 0 Task file settings Command field of the ATA task file set to 0xEA Reserved fields of the task file set to 0 bytcnt register and block_size field of the blksiz register set to 16 Card Read Threshold When an application needs to perform a single or multiple block read command the application must set the cardthrctl reg...

Page 736: ... the block size of the transfer the host must ensure that the receive FIFO buffer never overflows during the read transfer Overflow can cause the card clock from the controller to stop The controller is not able to guarantee that the card clock does not stop during a read transfer If the cardrdthreshold field of the cardthrctl register and the rx_wmark and dw_dma_multiple_transaction_size fields o...

Page 737: ...size field in the fifoth register to the number of transfers that make up a DMA transaction For example size 1 means 4 bytes are moved The possible values for the size are 1 4 8 16 32 64 128 and 256 transfers Select the size so that the value block size 4 is evenly divided by the size 5 Set the rx_wmark field in the fifoth register to the size 1 For example if your block size is 512 bytes legal va...

Page 738: ...g types of errors Response and data timeout errors For response time outs the host software can retry the command For data time outs the controller has not received the data start bit from the card so software can either retry the whole data transfer again or retry from a specified block onwards By reading the contents of the tcbcnt register later the software can decide how many bytes remain to b...

Page 739: ... appropriate error code is sent to the Error Register Error on the ATA card device If the device interrupt bit of the CE ATA card the nIEN bit in the ATA control register is set to 0 the CCS is sent to the host If the device interrupt bit is set to 1 the card device completes the entire data unit count if the host controller does not abort the ongoing transfer During a multiple block data transfer...

Page 740: ...it is set to 1 in the EXT_CSD register of the eMMC card The BOOT_SIZE_MULT and BOOT_BUS_WIDTH values in the EXT_CSD register to be used during the boot process 2 The software sets the following bits Sets masks for interrupts by setting the appropriate bits to 0 in the intmask register Sets the global int_enable bit of the ctrl register to 1 Other bits in the ctrl register must be set to 0 Altera r...

Page 741: ...acknowledge pattern is expected from the card device expect_boot_ack set to 0 proceed to step 12 11 This step handles the case where a start acknowledge pattern is expected expect_boot_ack was set to 1 in step 9 a If the Boot ACK Received interrupt is not received from the controller within 50 ms of initiating the command step 9 the software driver must set the following cmd register fields start_...

Page 742: ...ttern 0b010 or an EBE occurs The controller automatically aborts the boot process by pulling the CMD line high The controller generates a Command Done interrupt The controller does not generate a Boot ACK Received interrupt The application aborts the boot transfer e In internal DMA controller mode If the software driver creates more descriptors than required by the received boot data the extra des...

Page 743: ...ra descriptors are not closed by the controller If the software driver creates fewer descriptors than required by the received boot data the controller generates a Descriptor Unavailable interrupt and does not transfer any further data to system memory The boot operation for eMMC card devices is complete Related Information Clock Setup on page 11 34 Refer to this section for information on how to ...

Page 744: ...umerated Card Stack on page 11 31 Refer to this section for more information on discovering removable MMC cards www jedec org Alternative Boot Operation for eMMC Card Devices on page 11 67 Refer to this section for information about alternative boot operation steps Alternative Boot Operation The alternative boot operation differs from the previous boot operation in that software uses the SD SDIO G...

Page 745: ...tive boot operation the BOOT_INFO bit is set to 1 in the eMMC card The BOOT_SIZE_MULT and BOOT_BUS_WIDTH values in the card device to use during the boot process 2 The software sets the following bits Sets masks for interrupts by resetting the appropriate bits to 0 in the intmask register Sets the int_enable bit of the ctrl register to 1 Other bits in the ctrl register must be set to 0 Altera reco...

Page 746: ...t_boot_ack to 0 card_number 0 data_expected 1 cmd_index 0 Set the remainder of cmd register bits to 0 12 If no start acknowledge pattern is expected from the card device expect_boot_ack set to 0 jump to step 15 13 Wait for the Command Done interrupt 14 This step handles the case where a start acknowledge pattern is expected expect_boot_ack was set to 1 in step 11 a If the Boot ACK Received interru...

Page 747: ... an EBE occurs The controller does not generate a Boot ACK Received interrupt The controller detects Boot Data Start and generates a Boot Data Start interrupt The controller continues to receive boot data The application must abort the boot process after receiving a Boot Data Start interrupt g In internal DMA controller mode If the software driver creates more descriptors than required by the rece...

Page 748: ...creates more descriptors than required by the received boot data the extra descriptors are not closed by the controller If the software driver creates fewer descriptors than required by the received boot data the controller generates a Descriptor Unavailable interrupt and does not transfer any further data to system memory The alternative boot operation for eMMC card devices is complete Related In...

Page 749: ...e 11 31 Refer to this section for more information on discovering removable MMC cards www jedec org For more information refer to Access to Boot Partition in JEDEC Standard No JESD84 A43 available on the JEDEC website Alternative Boot Operation for eMMC Card Devices on page 11 67 Refer to this section for information about alternative boot operation steps Voltage Switches This section describes th...

Page 750: ...oller Address Map and Register Definitions The address map and register definitions reside in the hps html file that accompanies this handbook volume 1 To view the module description and base address a Click the link provided below to open the Address Map Information for Cyclone V SoC HPS file b Scroll to and click the sdmmc link 2 To then view the register and field descriptions scroll to and cli...

Page 751: ...organized programming information Added information about ECCs Added pin listing Updated clocks section 1 1 November 2012 Initial release 1 0 January 2012 Altera Corporation SD MMC Controller Send Feedback 11 73 Document Revision History cv_54011 2013 12 30 ...

Page 752: ...ace XIP flash devices ISO 9001 2008 Registered 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holder...

Page 753: ...nnect Validates incoming accesses Performs byte or half word reordering Performs write protection Forwards transfer requests to direct and indirect controller Direct access controller provides memory mapped slaves direct access to the flash memory Indirect access controller provides higher performance access to the flash memory through local buffering and software transfer requests Software trigge...

Page 754: ...half word and word accesses are permitted For write accesses only incrementing bursts are supported and only of sizes 1 4 8 and 16 transfers For read accesses all burst types and sizes are supported Register Slave Interface The quad SPI flash controller uses the register slave interface to configure the quad SPI controller through the quad SPI configuration registers and to access flash memory und...

Page 755: ...s data from the flash memory places the data into the SRAM and transfers the data to an external master through the data slave interface The indirect read operations are controlled by the following registers Indirect read transfer register indrd Indirect read transfer watermark register indrdwater Indirect read transfer start address register indrdstaddr Indirect read transfer number bytes registe...

Page 756: ...pt is generated even when the actual SRAM fill level has not risen above the watermark If the address of the read access is outside the range of the indirect trigger address one of the following actions occurs When direct access mode is enabled the read uses direct access mode When direct access mode is disabled the slave returns an error back to the requesting master You can cancel an indirect op...

Page 757: ...ect access mode When direct access mode is disabled the slave returns an error back to the requesting master You can cancel an indirect operation by setting the cancel indirect write bit cancel of the indwr register to 1 For more information refer to the Indirect Write Operation with DMA Disabled section Related Information Indirect Write Operation with DMA Disabled on page 12 15 Consecutive Reads...

Page 758: ...m fill level in bytes at which the DMA peripheral request controller can issue the DMA request The higher this number is the more data that must be buffered in SRAM before the external DMA moves the data When the SRAM fill level passes the watermark level the transfer watermark reached interrupt is generated For example consider the following conditions The total amount of data to be read using in...

Page 759: ...egisters or written to the flash command write data lower flashcmdwrdatalo and flash command write data upper flashcmdwrdataup registers per command Commands issued through the STIG have a higher priority than all other read accesses and therefore interrupt any read commands being requested by the direct or indirect controllers However the STIG does not interrupt a write sequence that may have bee...

Page 760: ...n operate from a reset state the opcode registers reset to opcodes compatible with single I O flash devices The quad SPI flash controller uses the instruction transfer width field instwidth of the devrd register to set the instruction transfer width for both reads and writes There is no instwidth field in the devwr register If instruction type is set to dual or quad mode the address transfer width...

Page 761: ...and fast program QCFP XIP Mode The quad SPI controller supports XIP mode if the flash devices support XIP mode Depending on the flash device XIP mode puts the flash device in read only mode reducing command overhead The quad SPI controller must instruct the flash device to enter XIP mode by sending the mode bits When the enter XIP mode on next read bit enterxipnextrd of the cfg register is set to ...

Page 762: ...he current access sequentially follows the address of the previous access The direction of the current access read or write is the same as previous access The size of the current access byte half word or word is the same as previous access When the access is detected as nonsequential the sequential access to the flash device is terminated and a new sequential access begins Altera recommends access...

Page 763: ...ndirect operations are already in the queue Indirect read reject A write to a protected area was attempted and rejected Protected area write attempt An illegal data slave access has been detected Data slave wrapping bursts and the use of split and retry accesses can cause this interrupt It is usually an indicator that soft masters in the FPGA fabric are attempting to access the HPS in an unsupport...

Page 764: ...s depending on whether the device is used in single dual or quad operation mode Table 12 3 lists the I O pin use of the quad SPI controller interface signals for each operation mode Table 12 4 Interface Signals Function Direction Mode Signal Data output 0 Output Single data 0 Data I O 0 Bidirectional Dual or quad Data input 0 Input Single data 1 Data I O 1 Bidirectional Dual or quad Active low wri...

Page 765: ...l4_main_clk clock is running at 400 MHz 2 5 ns period specify a value of at least 16 to the clock delay for chip select deassert field nss of the delay register 7 Update the remapaddr register as needed This register only affects direct access mode 8 Set up and enable the write protection registers wrprot lowwrprot and uppwrprot when write protection is required 9 Enable required interrupts though...

Page 766: ...irect read access by setting the start field of the indrd register to 1 8 Either use the indirect complete interrupt to determine when the indirect read operation has completed or poll the completion status of the indirect read operation through the ind_ops_done_status field of the indrd register Related Information Setting Up the Quad SPI Flash Controller on page 12 14 Indirect Write Operation wi...

Page 767: ...n 7 Start the indirect write access by setting the start field of the indirwr register to 1 8 Either use the indirect complete interrupt to determine when the indirect write operation has completed or poll the completion status of the indirect write operation through the ind_ops_done_status field of the indwr register Related Information Indirect Write Operation on page 12 5 Setting Up the Quad SP...

Page 768: ...irect access controller and indirect access controller to ensure no new read or write accesses are sent to the flash device 3 Set the XIP mode bits in the modebit register to 0x20 4 Enable the quad SPI controller s XIP mode by setting the enterxipnextrd bit of the cfg register to 1 5 Re enable the direct access controller and if required the indirect access controller Spansion Quad SPI Flash Devic...

Page 769: ...ister then follow the steps in the Entering XIP Mode section Software must be aware of the mode bit requirements of the device because XIP mode entry and exit varies by device Related Information Entering XIP Mode on page 12 16 Quad SPI Flash Controller Address Map and Register Definitions The address map and register definitions reside in the Address Map Information for Cyclone V SoC HPS file tha...

Page 770: ...m and system integration functional descrip tion programming model and address map and register definitions sections 1 1 May 2012 Initial release 1 0 January 2012 Altera Corporation Quad SPI Flash Controller Send Feedback 12 19 Document Revision History cv_54012 2013 12 30 ...

Page 771: ...01 2008 Registered 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera...

Page 772: ...cessor unit MPU subsystem or other masters to write the FPGA configuration image to the FPGA control block CB when configuring the FPGA portion of the SoC device The general purpose I O and boot handshaking input interfaces connect to the FPGA fabric The FPGA manager also connects to the FPGA CB signals to monitor and control the FPGA portion of the device The FPGA manager consists of the followin...

Page 773: ... boot from the primary boot flash device In this case the boot ROM code checks these two handshaking signals to determine if it should use the boot code hosted in the FPGA memory as the next stage in the boot process There is no interrupt support for this block Monitor The monitor block is an instance of the Synopsys DesignWare GPIO IP DW_apb_gpio which is a separate instance of the IP that compri...

Page 774: ...cdratio and configuration data width bit cfgwdth in the control register ctrl to match the MSEL pins The cdratio field and cfgwdth bit must be set before the start of configuration The FPGA manager connects to the configuration logic in the FPGA portion of the device using a mode similar to how external logic for example MAX II or an intelligent host configures the FPGA in fast passive parallel FP...

Page 775: ...se 2 Reset phase 3 Configuration phase 4 Initialization phase 5 User mode Related Information Configuration Design Security and Remote System Upgrades For more information about configuring the FPGA through the HPS refer to the Configuration Design Security and Remote System Upgrade appendix in the Cyclone V Device Handbook Volume 1 36 Other MSEL values are allowed when the FPGA is configured from...

Page 776: ...ation data to the FPGA by writing data to the write data register data in the FPGA manager module configuration data address map Software polls the CONF_DONE pin by reading the gpio_instatus register to determine if the FPGA configuration is successful When configuration is successful software sets the axicfgen bit of the ctrl register to 0 The FPGA user I O pins are still tri stated in this phase...

Page 777: ...ase The internal oscillator is disabled in user mode but is enabled as soon as the nCONFIG pin is driven low Related Information Configuration Design Security and Remote System Upgrades For more information about configuring the FPGA through the HPS refer to the Configuration Design Security and Remote System Upgrade appendix in the Cyclone V Device Handbook Volume 1 Booting and Configuration For ...

Page 778: ...e instance fpgamgrregs fpgamgrdata To then view the register and field descriptions scroll to and click the register names The register addresses are offsets relative to the base address of each module instance Related Information Introduction to Cyclone V Hard Processor System HPS on page 1 1 Cyclone V SoC HPS Address Map and Register Definitions Document Revision History Table 13 2 Document Revi...

Page 779: ... DMA security settings when the HPS exits from reset Provides boot source and clock source information that can be read during the boot process Provides the capability to enable disable an interface of signals to the FPGA Routes parity failure interrupts from the L1 caches to the Global Interrupt Controller Sends error correction code ECC enable signals to all HPS modules with ECC protected RAM Pr...

Page 780: ...use System Manager FPGA FPGA Fabric Control Block L4 Peripheral Bus osc1_clk The system manager consists of the following blocks CSRs Provide memory mapped access to control signals for the following HPS modules EMACs Debug core SD MMC controller NAND controller USB controllers DMA controller L3 Interconnect Route ECC and parity interrupts to the MPU Store status information received from other HP...

Page 781: ...n the Cyclone V Device Handbook Volume 3 Booting and Configuration Introduction on page 30 1 For boot and clock source values refer to the Booting and Configuration appendix Additional Module Control Each module in the HPS has its own CSRs providing access to the internal state of the module The system manager CSRs provide access to additional module state information enabling additional control a...

Page 782: ...register l3master to control these selections These bits define the cache attributes for the master transactions of the DMA engine in the NAND controller Register bits should be accessed only when the master interface is guaranteed to be in an inactive state Note Related Information NAND Flash Controller on page 10 1 EMAC The system manager allows software to select either emac_ptp_clk from the Cl...

Page 783: ...timer built into the MPU subsystem is automatically paused when its associated CPU enters debug mode Related Information Watchdog Timer on page 24 1 Boot ROM Code Registers in the system manager control whether the boot ROM code configures the pin multiplexing for boot pins after a warm reset Set the warm reset configure pin multiplex for boot pins bit warmrstcfg pinmux of the boot ROM code regist...

Page 784: ...t execution Contains the expected CRC of the region in the on chip RAM Expected CRC crc All the registers in the above table must be written by software prior to the warm reset occurring The number of wait states applied to the boot ROM s read operation is determined by the wait state bit waitstate of the ctrl register After the boot process software might require reading the code in the boot ROM ...

Page 785: ...nto the MPU L2 ECC memories for testing purposes Set the bits in the appropriate memory enable register to inject errors For example to inject a single bit EEC error set the injs bit of the mpu_ctrl_l2_ecc register The system manager can also inject parity failures into the parity protected RAM in the MPU L2 to test the parity failure interrupt handler Set the bits of the parity fail injection reg...

Page 786: ...he link below to open the file To view the module description and base address scroll to and click the link for the following module instance sysmgr To then view the register and field descriptions scroll to and click the register names The register addresses are offsets relative to the base address of each module instance Related Information Introduction to the Hard Processor System The base addr...

Page 787: ...Changes Version Date Initial release 1 0 January 2012 Altera Corporation System Manager Send Feedback 14 9 Document Revision History cv_54014 2013 12 30 ...

Page 788: ...ture Specification which you can download from the ARM info center website Features of the Scan Manager Drives all the I O scan chains for HPS I O banks Allows the HPS to access the FPGA JTAG TAP controller ISO 9001 2008 Registered 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and...

Page 789: ... 1 IOCSR 1 I O Bank 6 I O Bank 7A Scan Chain 2 IOCSR 2 Scan Chain 0 IOCSR 0 I O Bank 7B I O Bank 7C I O Bank 7E I O Bank 7D Register Slave Interface CONFIG_IO Mode HPS I O Pins 1 fpgajtagen select Not all devices contain all the banks depicted Note The processor accesses the scan manager through the register slave interface connected to the level 4 L4 peripheral bus Scan Manager Altera Corporation...

Page 790: ...se Input PORTCONNECTED 7 0 Tied to 0x8F so all connected ports are always considered powered on The PSTA register does not contain a useful value so there is no reason for software to access it Software does not need to monitor the status of ports 0 3 because they are always on For port 7 software can read the mode field of the stat register in the FPGA manager to determine the FPGA power status I...

Page 791: ...on of this chapter The I O scan chains do not use the JTAG protocol The scan manager uses the JTAG AP as a parallel to serial converter for the I O scan chains The I O scan chains are connected only to the serial output data TDI JTAG signal and serial clock TCK JTAG signal Note The HPS I O pins are divided into six banks Each I O bank is either a vertical VIO or horizontal HIO I O based on its loc...

Page 792: ...ads the active bit of stat register to determine the scan manager state Alternatively when the FPGA JTAG TAP controller receives the CONFIG_IO JTAG instruction the control block enters CONFIG_IO mode When the control block is in CONFIG_IO mode the controller can override the scan manager JTAG AP and configure the HPS I O pins The CONFIG_IO instruction configures all configurable I O pins in the So...

Page 793: ...can manager TCK signals are de asserted Note Altera recommends resetting the FPGA JTAG TAP controller using the scan manager s nTRST signal after the scan manager is connected to the controller Related Information Scan Manager Address Map and Register Definitions on page 15 8 System Manager on page 14 1 JTAG AP FIFO Buffer Access and Byte Command Protocol The JTAG AP contains FIFO buffers for byte...

Page 794: ...e other clock routes to the HPS I O scan chains with a frequency of sp i_m_clk 2 and runs at a maximum frequency of 100 MHz The spi_m_clk can potentially run faster than the scan manager supports so that SPI masters can support 60 Mbps rates When the SPI master is running faster than what is supported by the scan manager the scan manager cannot be used and must be held in reset Note Related Inform...

Page 795: ...ter and field descriptions scroll to and click the register names The register addresses are offsets relative to the base address of each module instance JTAG AP Register Name Cross Reference Table To improve clarity regarding how Altera uses the JTAG AP the ARM register names are changed in the SoC device The following table cross references the ARM and Altera names Table 15 4 JTAG AP Register Na...

Page 796: ...Table 15 5 Document Revision History Changes Version Date Minor formatting issues 2013 12 30 December 2013 Added JTAG AP descriptions 1 2 November 2012 Added block diagram and system integration functional descrip tion and address map and register definitions sections 1 1 May 2012 Initial release 1 0 January 2012 Altera Corporation Scan Manager Send Feedback 15 9 Document Revision History cv_54015...

Page 797: ... write AXI instructions through the respective instruction queues The DMAC also contains a multi FIFO MFIFO data buffer that stores data that it reads or writes during a DMA transfer The DMAC provides 11 interrupt outputs to enable efficient communication of events to the MPU subsystem The peripheral request interfaces support the connection of DMA capable peripherals to enable memory to periphera...

Page 798: ...ides a flexible method of specifying the DMA operations This architecture provides greater flexibility than the fixed capabilities of a Linked List Item LLI based DMA controller Supports multiple transfer types Memory to memory Memory to peripheral Peripheral to memory Scatter gather Supports up to eight DMA channels Supports up to eight outstanding AXI read and eight outstanding AXI write transac...

Page 799: ...ic and all the interfaces The DMA controller accesses the level 3 L3 main switch with its 64 bit AXI master interface The DMA controller provides the following slave interfaces Non secure slave interface Secure slave interface You can use these slave interfaces to access the registers that control the functionality of the DMA controller The DMA controller implements TrustZone secure technology wit...

Page 800: ... cache miss occurs the pipeline stalls until the first line fill is complete Note When a DMA channel thread executes a load or store instruction the DMAC adds the instruction to the relevant read or write queue The DMAC uses these queues as an instruction storage buffer prior to it issuing the instructions on the AXI The DMAC also contains an MFIFO data buffer in which it stores data that it reads...

Page 801: ...can transition to the Faulting completing Faulting or Killing After the DMAC exits from reset it sets all DMA channel threads to the Stopped state and DMA manager thread moves to the Stopped state The following sections describe the Thread Operating states Stopped The thread has an invalid PC Program Counter and it is not fetching instructions Depending on the thread type you can cause the thread ...

Page 802: ...read executes an undefined or invalid instruction An AXI error occurs during an instruction fetch For a DMA channel thread when a watchdog timeout abort occurs Completing When a DMA channel thread executes DMAEND Cache Miss The thread is stalled and the DMAC is performing a cache line fill After it completes the cache fill the thread returns to the Executing state Updating PC The DMAC is calculati...

Page 803: ...er is 64 by 512 bits providing 4096 bytes of memory The buffer provides error checking and correction ECC capability The ECC block is integrated around a memory wrapper and provides the following features Output to notify the system manager when single bit correctable errors are detected and corrected Output to notify the system manager when double bit uncorrectable errors are detected Provision f...

Page 804: ... Usage on page 16 18 Describes how the security state of the irq x signals affects how the DMAC executes the DMAWFE and DMASEV instructions How to Set the Security State for a Peripheral Request Interface The DMAC provides the signals to enable you to assign each peripheral request interface to a security state The boot_periph_ns 31 0 signals connect to the system manager Before taking the DMA out...

Page 805: ...wise the DMAC ignores the instruction You can use the secure or non secure slave interface to start or restart a DMA channel when the DMAC is in the Non secure state Before you can issue instructions using the debug instruction registers or the DBGCMD register you must read the DBGSTATUS register to ensure that debug is idle otherwise the DMAC ignores the instructions Note The DMAC immediately pro...

Page 806: ...the Peripheral Request Interface DMAC Peripheral drvalid drtype 1 0 drlast daready davalid datype 1 0 drready Peripheral Request Interface The peripheral indicates the following on the request bus Request a single transfer Request a burst transfer Acknowledge a flush request The peripheral indicates the DMAC when it issues the last request of the DMA transfer sequence The DMAC can indicate the fol...

Page 807: ...RX Synopsys 28 UART 0 TX Synopsys 12 I2 C 2 TX EMAC Synopsys 29 UART 0 RX Synopsys 13 I2 C 2 RX EMAC Synopsys 30 UART 1 TX Synopsys 14 I2 C 3 TX EMAC Synopsys 31 UART 1 RX Synopsys 15 I2 C 3 RX EMAC Request Acceptance Capability The DMAC can accept one active request for each peripheral request interface An active request exists when the DMAC has not started the requested AXI data transfers Periph...

Page 808: ...equest_last flags DMALD DMAST DMALPEND When these instructions use the optional B S suffix then the DMAC executes a DMANOP if the request_type flag does not match DMALDP B S DMASTP B S The DMAC executes a DMANOP if the request_type x flag does not match the B S DMALPEND When the nf bit is 0 the DMAC executes a DMANOP if the request_last flag is set Use the DMALDB DMALDPB DMASTB and DMASTPB instruc...

Page 809: ...est FIFO buffer is a single request type the DMAC removes the entry from the FIFO buffer and continues program execution Burst If the head entry in the request FIFO buffer is a burst request type the DMAC pops the entry from the FIFO buffer and continues program execution Program the DMALDP instruction when you require the DMAC to send an acknowledgement to the peripheral when it completes the AXI...

Page 810: ...resource When the DMAC executes a DMAWFE instruction for the same event interrupt resource then it clears the event Interrupt The DMAC sets the irq event_num signal high where event_num is the number of the specified event resource To clear the interrupt you must write to the INTCLR register Using an Event to Restart DMA Channels When you program the INTEN register to generate an event you can use...

Page 811: ... register Executing DMAWFE does not clear an interrupt Note If you use the DMASEV instruction to notify a microprocessor when the DMAC completes a DMALD or DMAST instruction then you should insert a memory barrier instruction before the DMASEV Otherwise the DMAC might signal an interrupt before the AXI transfers complete The following program shows the example of Memory Barrier Instruction DMALD D...

Page 812: ...th an operand that is invalid for the configuration of the DMAC When the DMAC signals a precise abort the instruction that triggers the abort is not executed Instead the DMAC executes a DMANOP Note The DMAC signals an imprecise abort under the following conditions The DMAC receives an ERROR response on the AXI master interface when it performs a data load The DMAC receives an ERROR response on the...

Page 813: ... recover from an abort You must use an external agent such as a microprocessor to terminate a thread when an abort occurs The following figure shows the operating states for the DMA channel and DMA manager threads after an abort occurs Figure 16 4 Abort Process DMA Channel Thread Thread Moves to the Stopped State Executing Program Thread Has an Abort Occurred yes no Active AXI Transactions Complet...

Page 814: ...ovides the cause of the abort Reading the status of the FSRC register to determine if a DMA channel is Faulting In the Faulting state the FSRC register provides the cause of the abort To enable a thread in the Faulting state to move to the Stopped state the external agent must Program the DBGINST0 register with the encoding for the DMAKILL instruction Write to the DBGCMD register If the aborted th...

Page 815: ... a DMA channel thread and instead it Executes an NOP Sets the FSRD register Sets the dmago_err bit in the FTRD register Moves the DMA manager to the Faulting state If ns 1 The DMAC starts a DMA channel thread in the Non secure state and programs the CNS bit to be non secure DMAWFE The DMAC uses the status of the corresponding INS bit in the CR3 register to control whether it waits for the event If...

Page 816: ...ontinues execution of the thread irrespective of the security state of the corresponding PNS bit in the CR4 register DMALDP and DMASTP The DMAC sends a message to the peripheral to communicate that data transfer is complete irrespective of the security state of the corresponding PNS bit in the CR4 register DMAFLUSHP The DMAC clears the state of the peripheral and sends a message to the peripheral ...

Page 817: ... creates the event interrupt DMAWFP The DMAC uses the status of the corresponding PNS bit in the CR4 register to control if it waits for the peripheral to signal a request If PNS 0 The peripheral is in the Secure state The DMAC Executes an NOP Sets the appropriate bit in the FSRC register that corresponds to the DMA channel number Sets the ch_periph_err bit in the FTRn register Moves the DMA chann...

Page 818: ...DMA Channel Arbitration The DMAC uses a round robin scheme to serve the active DMA channels To ensure that the DMAC continues to serve the DMA manager it always serves the DMA manager prior to serving the next DMA channel You cannot alter the arbitration process of the DMAC DMA Channel Prioritization The DMAC responds to all active DMA channels with equal priority You cannot increase the priority ...

Page 819: ...C does not support fixed unaligned bursts If you program the following conditions the DMAC treats this as a programming error Unaligned read src_inc field is 0 in the CCRn register The SARn register contains an address that is not aligned to the size of data that the src_burst_size field contains Unaligned write dst_inc field is 0 in the CCRn register The DARn register contains an address that is ...

Page 820: ...escribe the register fields that might have a detrimental impact on a data transfer Updates that affect the destination address If you use a DMAMOV instruction to update the DARn register or CCRn register part way through a DMA cycle then this might cause a discontinuity in the destination data stream A discontinuity occurs if you change any of the following endian_swap_size field dst_inc bit dst_...

Page 821: ...y of the following occur It executes a DMAST DMASTP or DMASTZ It reaches a barrier that is it executes DMARMB or DMAWMB It waits that is it executes DMAWFP or DMAWFE It terminates normally that is it executes DMAEND It aborts for any reason including DMAKILL The MFIFO buffer resource usage of a DMA channel program is measured in MFIFO buffer entries and rises and falls as the program proceeds The ...

Page 822: ...peripheral request interfaces dma_periph_if_rst_n 7 0 Related Information Reset Manager on page 3 1 DMA Controller Programming Model Instruction Syntax Conventions The following conventions are used in assembler syntax prototype lines and their subfields Any item bracketed by and is mandatory A description of the item and of how it is encoded in the instruction is supplied by subsequent text Any i...

Page 823: ...ILL on page 16 31 Yes Yes Kill DMAKILL DMALD S B on page 16 32 Yes No Load DMALD DMALDP S B on page 16 32 Yes No Load and Notify Peripheral DMALDP DMALP on page 16 33 Yes No Loop DMALP DMALPEND S B on page 16 34 Yes No Loop End DMALPEND DMALPFE on page 16 36 Yes No Loop Forever DMALPFE DMAMOV on page 16 36 Yes No Move DMAMOV DMANOP on page 16 37 Yes Yes No Operation DMANOP DMARMB on page 16 37 Yes...

Page 824: ...ther SAR SARn register and sets ra to 0 DAR DARn register and sets ra to 1 16 bit immediate The immediate value to be added to the address_register Operation You can only use this instruction in a DMA channel thread DMAADNH Add Negative Halfword adds an immediate negative 16 bit value to the SARn register or DARn register for the DMA channel thread This enables the DMAC to support two dimensional ...

Page 825: ...fectively subtracting 16 from the DAR Note Operation You can only use this instruction in a DMA channel thread DMAEND End signals to the DMAC that the DMA sequence is complete After all DMA transfers are complete for the DMA channel the DMAC moves the channel to the Stopped state It also flushes data from the MFIFO buffer and invalidates all cache entries for the thread Figure 16 7 DMAEND Instruct...

Page 826: ...am counter 2 Sets its security state 3 Updates it to the Executing state If a DMA channel is not in the Stopped state when the DMA manager executes DMAGO then the DMAC does not execute DMAGO but instead it executes DMANOP Note Figure 16 9 DMAGO Instruction Encoding 0 7 6 5 4 3 2 1 0 15 14 13 12 11 10 8 cn 2 0 0 0 0 16 47 imm 31 0 0 0 0 0 0 0 1 1 ns Assembler syntax DMAGO channel_number 32 bit_imme...

Page 827: ...pe the DMAC performs the following steps DMA Manager Thread 1 Invalidates all cache entries for the DMA manager 2 Moves the DMA manager to the Stopped state DMA Channel Thread 1 Moves the DMA channel to the Killing state 2 Waits for AXI transactions with an ID equal to the DMA channel number to complete 3 Invalidates all cache entries for the DMA channel 4 Remove all entries in the MFIFO buffer fo...

Page 828: ...channel control registers request_type Burst The DMAC performs a DMANOP instruction The DMAC increments the channel PC to the next instruction No state change occurs B If B is present the assembler sets bs to 1 and x to 1 The instruction is conditional on the state of the request_type flag request_type Single The DMAC performs a DMANOP instruction The DMAC increments the channel PC to the next ins...

Page 829: ...e DMAC performs a DMANOP request_type Burst The DMAC performs a load using a burst DMA transfer peripheral 5 bit immediate value 0 31 The DMAC sets the value of the request_type flag when it executes a DMAWFP instruction Note Operation You can only use this instruction in a DMA channel thread Execution of the instruction is conditional on the state of the request_type flag matching that of the ins...

Page 830: ...D S B instructs the DMAC to read the value of the loop counter register If a loop counter register returns Zero The DMAC executes a DMANOP and therefore exits the loop Nonzero The DMAC decrements the value in the loop counter register and updates the thread PC to contain the address of the first instruction in the program loop that is the instruction that follows the DMALP DMALPFE The loop has an ...

Page 831: ... the same way as for DMALPFE the DMAC uses the state of the request_last flag to control when it exits the loop Note The DMAC sets the value of the Note request_type flag when it executes a DMAWFP instruction request_last flag to 1 when the corresponding peripheral issues the last request command through the peripheral request interface To correctly assign the additional bits in the DMALPEND instr...

Page 832: ...of the loop Note Assembler syntax DMALPFE Related Information DMALPEND S B on page 16 34 DMAMOV Move instructs the DMAC to move a 32 bit immediate into the following registers source address registers destination address registers channel control registers Figure 16 15 DMAMOV Instruction Encoding 0 7 6 5 4 3 2 1 0 15 14 13 12 11 10 8 rd 2 0 0 0 0 0 16 47 imm 31 0 0 0 1 1 1 1 1 1 0 Assembler syntax...

Page 833: ...nment purposes Figure 16 16 DMANOP Instruction Encoding 0 7 6 5 4 3 2 1 0 0 0 0 0 0 1 1 Assembler syntax DMANOP Operation You can use the instruction with the DMA manager thread and the DMA channel thread DMARMB Read Memory Barrier forces the DMA channel to wait until all of the executed DMALD instructions for that channel have been issued on the AXI master interface and have completed This enable...

Page 834: ...number that is not available Note Operation You can use the instruction with the DMA manager thread and the DMA channel thread Related Information Using Events and Interrupts on page 16 14 Using an Event to Restart DMA Channels on page 16 14 DMAST S B Store instructs the DMAC to transfer data from the FIFO buffer to the location that the destination address registers specifies using AXI transactio...

Page 835: ...ou can only use this instruction in a DMA channel thread If you specify the S or B operand execution of the instruction is conditional on the state of the request_type flag matching that of the instruction The DMAC only commences the burst when the MFIFO buffer contains all of the data necessary to complete the burst transfer Related Information DMAWFP on page 16 41 DMASTP S B Store and notify Per...

Page 836: ...commences the burst when the MFIFO buffer contains all of the data necessary to complete the burst transfer Related Information DMAWFP on page 16 41 DMASTZ Store Zero instructs the DMAC to store zeros using AXI transactions that the destination address registers and channel control registers specify If the dst_inc bit in the channel control registers is set to incrementing the DMAC updates the des...

Page 837: ...formation Using Events and Interrupts on page 16 14 DMAWFP Wait For Peripheral instructs the DMAC to halt execution of the thread until the specified peripheral signals a DMA request for that DMA channel Figure 16 23 DMAWFP Instruction Encoding p 7 6 5 4 3 2 1 0 15 8 peripheral 4 0 10 11 0 0 9 0 1 0 0 0 0 1 bs Assembler syntax DMAWFP peripheral single burst periph where peripheral 5 bit immediate ...

Page 838: ... been issued on the AXI master interface and have completed This permits read after write sequences to the same address location with no hazards Figure 16 24 DMAWMB Instruction Encoding 1 7 6 5 4 3 2 1 0 1 0 0 1 0 0 0 Assembler syntax DMAWMB Operation You can only use this instruction in a DMA channel thread Assembler Directives The assembler provides several additional commands DCD Assembler dire...

Page 839: ...te DMALPFE Assembler directive to insert a repetitive loop Syntax DMALPFE Enables the assembler to clear the nf bit that is present in DMALPEND S B DMAMOV CCR Assembler directive that enables you to program the channel control registers using the specified format Syntax DMAMOV CCR SB 1 16 SS 8 16 32 64 128 SA I F SP imm3 SC imm4 DB 1 16 DS 8 16 32 64 128 DA I F DP imm3 DC imm4 ES 8 16 32 64 128 Ta...

Page 840: ...s 0x103 and writes to address 0x205 All byte manipulations occur when data enters the MFIFO buffer as a result of an AXI read due to a DMALD instruction so that the DMAC does not need to manipulate the data when it removes it from the MFIFO buffer as a result of an AXI write due to a DMAST instruction Therefore the storage and packing of the data in the MFIFO buffer is determined by the destinatio...

Page 841: ...ovide several example DMAC programs together with illustrations of the MFIFO buffer usage These sections show MFIFO buffer usage in the following ways A graph of the number of MFIFO buffer entries versus time A diagram of the byte lane manipulation that the DMAC performs when data enters the MFIFO buffer Note The numbers 0 and 7 in the MFIFO buffer diagrams indicate the byte lanes in the MFIFO buf...

Page 842: ...DB4 DS64 DMAMOV SAR 0x1000 DMAMOV DAR 0x4000 DMALP 16 DMALD shown as a in the figure below DMALD shown as b in the figure below DMALD shown as c in the figure below DMALD shown as d in the figure below DMAST shown as e in the figure below DMALPEND DMAEND Figure 16 26 Aligned Asymmetric Program with Multiple Loads Each DMALD requires one entry and each DMAST removes four entries Data from 4x DMALD ...

Page 843: ... DMAST This example has a static requirement of zero MFIFO buffer entries and a dynamic requirement of four MFIFO buffer entries Unaligned Transfers Aligned Source Address to Unaligned Destination Address In the following program the source address is aligned with the AXI data bus width but the destination address is unaligned The destination address is not aligned to the destination burst size so...

Page 844: ...tatic requirement of one MFIFO buffer entry and a dynamic requirement of four MFIFO buffer entries Unaligned Source Address to Aligned Destination Address In this program the source address is unaligned with the AXI data bus width but the destination address is aligned The source address is not aligned to the source burst size so the first DMALD instruction reads in less data than the DMAST Theref...

Page 845: ...bytes into an MFIFO buffer entry that the DMAC has already allocated to this channel Note This example has a static requirement of four MFIFO buffer entries and a dynamic requirement of four MFIFO buffer entries Unaligned Source Address to Aligned Destination Address with Excess Initial Load This program is an alternative to that described in Unaligned Source Address to Aligned Destination Address...

Page 846: ... f f e e e e Data for last DMAST a a a a a a a a c The DMALD shown as f does not increase the MFIFO buffer usage because it loads four bytes into an MFIFO buffer entry that the DMAC has already allocated to this channel Note This example has a static requirement of one MFIFO buffer entry and a dynamic requirement of four MFIFO buffer entries Related Information Unaligned Source Address to Aligned ...

Page 847: ...d the destination address is fixed DMAMOV CCR SB2 SS64 DB4 DS32 DAF DMAMOV SAR 0x1000 DMAMOV DAR 0x4000 DMALP 16 DMALD shown as a in the figure below DMAST shown as b in the figure below DMALPEND DMAEND Figure 16 32 Fixed Destination with Aligned Address Each DMALD in the program loads two 64 bit data transfers into the MFIFO buffer Because the destination address is a 32 bit fixed address then th...

Page 848: ...ions Figure 16 33 DMAC Summary Register Map 0x000 Configuration Debug AXI and Loop Counter Status DMA Channel Thread Status Control Component ID 0x100 0x13C 0x05C 0xD00 0xD0C 0xE14 0xFE0 0x400 0x4FC 0xE00 0xFFF DMA Controller Altera Corporation Send Feedback cv_54016 DMA Controller Registers 16 52 2013 12 30 ...

Page 849: ...efinitions The address map and register definitions reside in the hps html file that accompanies this handbook volume Click the link below to open the file To view the module description and base address scroll to and click the following links for the module instance dmanonsecure dmasecure To view the register and field descriptions scroll to and click the register names The register addresses are...

Page 850: ...uanta pause frame on flow control input deassertion Optional forwarding of received pause control frames to the user Packet bursting and frame extension in 1000 Mbps half duplex IEEE 802 3x flow control in full duplex Back pressure support for half duplex IEEE 1588 2002 and IEEE 1588 2008 precision networked clock synchronization IEEE 802 3 az version D2 0 for Energy Efficient Ethernet EEE IEEE 80...

Page 851: ...ked list chained descriptor chaining Descriptors can each transfer up to 8 KB of data Management Interface 32 bit host interface to CSR set Comprehensive status reporting for normal operation and transfers with errors Configurable interrupt options for different operational conditions Per frame transmit receive complete interrupt control Separate status returned for transmission and reception pack...

Page 852: ... In Out EMAC Port Transmit Clock This signal provides the transmit clock for RGMII 125 25 2 5 MHz in 1G 100M 10Mbps All PHY transmit signals generated by the EMAC are synchronous to this clock 1 In clk_tx_i PHY Transmit Data This is a group of eight transmit data signals driven by the MAC Unused bits in the RGMII interface configura tion are tied to low RGMII Bits 3 0 provide the RGMII transmit da...

Page 853: ...dity of the data is qualified with phy_rxdv_i Synchronous to clk_rx_i clk_rx_180_i 8 In phy_rxd_i PHY Receive Data Valid This signal is driven by PHY RGMII This is the receive control signal used to qualify the data received on phy_rxd This signal is sampled on both edges of the clock Synchronous to clk_rx_i clk_rx_180_i 1 In phy_rxdv_i Receive clock reset output 1 Out rst_clk_rx_n_o PHY Interface...

Page 854: ...hich PHY interface is selected GMII All eight bits provide the GMII transmit data byte For the lower speed MII operation only the low 4 bits are used The validity of the data is qualified with phy_txen_o and phy_txer_o Synchronous to phy_ clk_tx_o RGMII Bits 3 0 provide the RGMII transmit data The data bus changes with both rising and falling edges of the transmit clock clk_tx_o The validity of th...

Page 855: ...HY For RGMII the clock frequency is 125 25 2 5 MHz in 1 G 100 M and 10 Mbps modes For GMII the clock frequency is 125 MHz 1 In phy_clk_rx_i PHY Receive Data This is a bundle of eight data signals received from the PHY It has multiple functions depending on which PHY interface is selected as listed below GMII All 8 bits provide the GMII receive data byte The validity of the data is qualified with p...

Page 856: ...k_rx_i This signal is not used in RGMII mode 1 In phy_rxer_i Receive clock reset output 1 Out rst_clk_rx_n_o PHY Carrier Sense This signal valid only in the GMII MII mode is asserted by the PHY when either the transmit or receive medium is not idle The PHY de asserts this signal when both transmit and receive medium are idle This signal is not synchronous to any clock 1 In phy_crs_i PHY Collision ...

Page 857: ...This signal is asserted whenever valid data is driven on the gmii_mdo_o signal The active state of this signal is high 1 Out gmii_mdo_o_e Management Data Clock The EMAC provides timing reference for the gmii_mdi_i and gmii_mdo_o signals on MII through this aperiodic clock The maximum frequency of this clock is 2 5 MHz This clock is generated from the application clock through a clock divider 1 Out...

Page 858: ...vice port to the system memory The controller uses descriptors to efficiently move data from source to destination with minimal host intervention The EMAC also contains FIFO buffer memory to buffer and regulate the Ethernet frames between the application system memory and the EMAC controller On transmit the Ethernet frames read into the transmit FIFO buffer 1024 x 42 bits and eventually trigger th...

Page 859: ...erts an interrupt signal The host needs to reset the EMAC with a hard or soft reset to restart the DMA to recover from this condition The EMAC supports up to 16 outstanding transactions on the interface Buffering outstanding transactions smooths out back pressure behavior This is important when resource contention bottlenecks arise under high system load conditions Cache Control Interface The syst...

Page 860: ...ng inherent precision resolution and stability to synchronize It is frequently used in automation systems where a collection of communicating machines such as robots must be synchronized and hence operate over a common time base The PTP is transported over UDP IP The system or network is classified into Master and Slave nodes for distributing the timing and clock information The following figure s...

Page 861: ...exact time t4 at which it enters its system 6 The master sends the t4 information to the slave in the delay_resp message 7 The slave uses the four values of t1 t2 t3 and t4 to synchronize its local timing reference to the master s timing reference Most of the PTP implementation is done in the software above the UDP layer However the hardware support is required to capture the exact time when speci...

Page 862: ...rom the FPGA Used as PTP clock reference for each EMAC when the FPGA has implemented timestamp capture interface Common for all three EMACs 1 In f2h_emac_ptp_ref_clk Pulse Per Second This signal is asserted based on the PPS mode selected in the Register 459 PPS Control Register Otherwise this pulse signal is asserted every time the seconds counter is incremented Synchronous to f2h_emac_f2hptp_ref_...

Page 863: ...s maintain linear time and does not introduce drastic changes or a large jitter in the reference time between PTP sync message intervals In this method an accumulator sums up the contents of the Timestamp_Addend register as shown in the figure below The arithmetic carry that the accumulator generates is used as a pulse to increment the system time counter The accumulator and the addend are 32 bit ...

Page 864: ...0 232 FreqDivisionRatio If MasterToSlaveDelay is initially assumed to be the same for consecutive sync messages the algorithm described below must be applied After a few sync cycles frequency lock occurs The slave clock can then determine a precise MasterToSlaveDelay value and re synchronize with the master using the new value The algorithm is as follows At time MasterSyncTime n the master sends t...

Page 865: ...received on the PHY interface The DMA returns the timestamp to the software in the corresponding receive descriptor The timestamp is written only to the last receive descriptor Timestamp Error Margin According to the IEEE 1588 specifications a timestamp must be captured at the SFD of the transmitted and received frames at the PHY interface Because the PHY interface receive and transmit clocks are ...

Page 866: ... is 18 75 MHz 24 GMII clocks 4 for a jam pattern sent just after SFD because of collision 12 IFG 8 preamble 42 1000 Mbps half duplex operation Related Information IEEE Standards Association website For more information on the IEEE standards refer to the IEEE Standards Association website IEEE 1588 2008 Advanced Timestamps In addition to the basic timestamp features mentioned in IEEE 1588 2002 Time...

Page 867: ... supports the following reference timing source features defined in the IEEE 1588 2008 standard 48 bit seconds Field Fixed pulse per second output Flexible pulse per second output Auxiliary snapshots timestamps with external events Transmit Path Functions The advanced timestamp feature is supported through the descriptors format Receive Path Functions The MAC processes the received frames to ident...

Page 868: ...rking Group website www ieee802 org 3 Related Information IEEE 802 3az Energy Efficient Ethernet LPI Timers Two timers internal to the EMAC are associated with LPI mode LPI Link Status LS Timer LPI TW Timer The LPI LS timer counts in ms the time expired since the link status is up This timer is cleared every time the link goes down and is incremented when the link is up again and the terminal coun...

Page 869: ...A value of 0 selects Bit 0 of the selected register and a value of 111111 binary selects Bit 63 of the Hash Table register If the corresponding bit is set to one the unicast frame is said to have passed the hash filter otherwise the frame has failed the hash filter Multicast Destination Address Filter The MAC can be programmed to pass all multicast frames In Perfect Filtering mode the multicast ad...

Page 870: ...gged frames VLAN Hash Filtering with a 16 Bit Hash Table The MAC provides VLAN hash filtering with a 16 bit hash table The MAC also supports the inverse matching of the VLAN frames In inverse matching mode when the VLAN tag of a frame matches the perfect or hash filter the packet should be dropped If the VLAN perfect and VLAN hash match are enabled a frame is considered as matched if either the VL...

Page 871: ... Table 17 6 Ethernet MAC Controller Clocks Notes Functional Usage Nominal Frequency Name If supplied from clock interface clock is emac0_clk or emac1_clk Reference Clock to the EMAC 250 Mhz clk_ref_i Auto negotiates speed down to 10 100 Mbps 125 25 2 5 MHz clk_tx_i All PHY signals received by the MAC are synchronous to this clock PHY provides this reference to MAC clk_rx_i Clock Gating for EEE For...

Page 872: ...e transmit Buffer in the Host memory Descriptors that reside in the Host memory act as pointers to these buffers There are two descriptor lists one for reception and one for transmission The base address of each list is written into Register 3 Receive Descriptor List Address Register and Register 4 Transmit Descriptor List Address Register respectively A descriptor list is forward linked either im...

Page 873: ...iptor structure during RTL configuration The control bits in the descriptor structure are assigned so that the application can use an 8 KB buffer All descriptions refer to the default descriptor structure Note Related Information Descriptors on page 17 36 Detailed bit map of the descriptor structure Ethernet MAC Address Map and Register Definitions on page 17 58 Information about Control and Statu...

Page 874: ...ame when it is less than the configured burst length The DMA indicates the start address and the number of transfers required to the master interface When the interface is configured for fixed length burst then it transfers data using the best combination of INCR4 8 or 16 and SINGLE transactions Otherwise no fixed length burst it transfers data using INCR undefined length and SINGLE transactions T...

Page 875: ...ES0 then the descriptor s corresponding buffer s are full and the amount of valid data in a buffer is accurately indicated by its buffer size field minus the data buffer pointer offset when the FS bit of that descriptor is set The offset is zero when the data buffer pointer is aligned to the data bus width If a descriptor is marked as last then the buffer may not be full as indicated by the buffer...

Page 876: ...tches the next descriptor Repeat step 3 step 4 and step 5 until the end of Ethernet frame data is transferred to the MTL 7 When frame transmission is complete if IEEE 1588 timestamping was enabled for the frame as indicated in the transmit status the timestamp value obtained from MTL is written to the transmit descriptor TDES2 and TDES3 that contains the end of frame buffer The status information ...

Page 877: ...criptor no Wait for Tx Status Related Information TX DMA Operation Default Non OSF Mode on page 17 26 TX DMA Operation OSF Mode While in the Run state the transmit process can simultaneously acquire two frames without closing the Status descriptor of the first if Bit 2 OSF in Register 6 Operation Mode Register is set As the transmit process finishes transferring the first frame it immediately poll...

Page 878: ... a status bit The DMA then writes the status with a cleared Own bit to the corresponding TDES0 thus closing the descriptor If timestamping was not enabled for the previous frame the DMA does not alter the contents of TDES2 and TDES3 6 If enabled the transmit interrupt is set the DMA fetches the next descriptor then proceeds to step 3 when Status is normal If the previous transmission status shows ...

Page 879: ...o Error no Write Status Word to Previous Frame s TDES0 Previous Frame Status Available yes yes Transmit Frame Processing The transmit DMA expects that the data buffers contain complete Ethernet frames excluding preamble pad bytes and FCS fields The DA SA and Type Len fields contain valid data If the transmit descriptor indicates that the MAC must disable CRC or PAD insertion the buffer must have c...

Page 880: ...transmit error because of underflow is detected The appropriate Transmit Descriptor 0 TDES0 bit is set If the DMA goes into SUSPEND state because of the first condition then both Bit 16 Normal Interrupt Summary and Bit 2 Transmit Buffer Unavailable of Register 5 Status Register are set If the second condition occur both Bit 15 Abnormal Interrupt Summary and Bit 5 Transmit Underflow of Register 5 S...

Page 881: ...ed and the Last Segment bit set 8 The receive engine checks the latest descriptor s Own bit If the host owns the descriptor Own bit is 0 the Bit 7 Receive Buffer Unavailable of Register 5 Status Register is set and the DMA receive engine enters the Suspended state Step 9 If the DMA owns the descriptor the engine returns to step 4 and awaits the next frame 9 Before the receive engine enters the Sus...

Page 882: ...nd New Frame Available yes no Flush Disabled yes no Close RDES0 As Intermediate Descriptor Set Descriptor Error Fetch Next Descriptor Error no Own Bit Set For Next Descriptor no If software has enabled timestamping through CSR when a valid timestamp value is not available for the frame for example because the receive FIFO buffer was full before the timestamp could be written to it the DMA writes a...

Page 883: ... buffer If the frame is contained in a single descriptor both Last Descriptor RDES 8 and First Descriptor RDES 9 are set The DMA fetches the next descriptor sets the Last Descriptor RDES 8 bit and releases the RDES0 status bits in the previous frame descriptor Then the DMA sets the Bit 6 Receive Interrupt of Register 5 Status Register The same process repeats unless the DMA encounters a descriptor...

Page 884: ...rupt of Register 5 Status Register and the driver begins reading Register 5 Status Register Next Bit 7 Receive Buffer Unavailable of Register 5 Status Register occurs The driver clears the receive interrupt Even then the sbd_intr_o signal is not de asserted because of the active or pending Receive Buffer Unavailable interrupt Bits 7 0 Interrupt Timer of Register 9 Receive Interrupt Watchdog Timer ...

Page 885: ...ion and RDES1 The transmit descriptor stores the timestamp in TDES6 and TDES7 when you select the advanced timestamp This receive descriptor structure is also used for storing the extended status RDES4 and timestamp RDES6 and RDES7 when advanced timestamp IPC Full Checksum Offload Engine or Layer 3 and Layer 4 filter feature is selected You can select one of the following options for descriptor st...

Page 886: ...iptor size When this control bit is reset the TDES4 TDES7 descriptor space is not valid Note Figure 17 11 Transmit Descriptor Fields Format 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TDES0 O W N Ctrl 30 26 T T S E Ctrl 24 18 T T S S Status 16 7 Ctrl Status 6 3 Status 2 0 TDES1 Ctrl 31 29 Buffer 2 Byte Count 28 16 RES Buffer 1 Byte Count 12 0 0 1 3 s s e r...

Page 887: ...been set This avoids a possible race condition between fetching a descriptor and the driver setting an ownership bit 31 IC Interrupt on Completion When set this bit sets the Transmit Interrupt Register 5 0 after the present frame has been transmitted 30 LS Last Segment When set this bit indicates that the buffer contains the last segment of the frame When this bit is set the TBS1 or TBS2 field in ...

Page 888: ...econd address in the descriptor is the Next descriptor address rather than the second buffer address When TDES0 20 is set TBS2 TDES1 28 16 is a don t care value TDES0 21 takes precedence over TDES0 20 20 Reserved 19 18 TTSS Transmit Timestamp Status This field is used as a status bit to indicate that a timestamp was captured for the described transmit frame When this bit is set TDES2 and TDES3 hav...

Page 889: ...set this bit indicates that MAC transmitter detected an error in the TCP UDP or ICMP IP datagram payload The transmitter checks the payload length received in the IPv4 or IPv6 header against the actual number of TCP UDP or ICMP packet bytes received from the application and issues an error status in case of a mismatch 12 LC Loss of Carrier When set this bit indicates that a loss of carrier occurre...

Page 890: ...Register 0 MAC Configuration Register is set high 2 UF Underflow Error When set this bit indicates that the MAC aborted the frame because the data arrived late from the Host memory Underflow Error indicates that the DMA encountered an empty transmit buffer while transmitting the frame The transmission process enters the Suspended state and sets both Transmit Underflow Register 5 5 and Transmit Int...

Page 891: ...e corresponding transmit frame This field has the timestamp only if the Last Segment bit LS in the descriptor is set and Timestamp status TTSS bit is set 31 09 Table 17 13 Transmit Descriptor 7 TDES7 Description Bit TTSH Transmit Frame Timestamp High This field is updated by DMA with the most significant 32 bits of the timestamp captured for the corresponding receive frame This field has the times...

Page 892: ...D T 0 1 3 h g i H p m a t s e m i T t i m s n a r T 7 S E D T Receive Descriptor Field 0 RDES0 Table 17 14 Receive Descriptor Field 0 RDES0 Description Bit OWN Own Bit When set this bit indicates that the descriptor is owned by the DMA of the EMAC When this bit is reset this bit indicates that the descriptor is owned by the Host The DMA clears this bit either when it completes the frame reception ...

Page 893: ...s field is valid only when the Last Descriptor RDES0 8 is set 15 DE Descriptor Error When set this bit indicates a frame truncation caused by a frame that does not fit within the current descriptor buffers and that the DMA does not own the Next descriptor The frame is truncated This field is valid only when the Last Descriptor RDES0 8 is set 14 SAF Source Address Filter Fail When set this bit indi...

Page 894: ...IPv4 Header checksum calculated by the EMAC did not match the received checksum bytes Otherwise this bit when set indicates the Giant frame Status Giant frames are larger than 1 518 byte or 1 522 byte for VLAN or 2 000 byte when Bit 27 2KPE of MAC Configuration register is set normal frames and larger than 9 018 byte 9 022 byte for VLAN frame when Jumbo frame processing is enabled 7 LC Late Collis...

Page 895: ...formation Receive Descriptor Field 4 RDES4 on page 17 48 Receive Descriptor Field 6 RDES6 on page 17 51 Receive Descriptor Field 7 RDES7 on page 17 52 Receive Descriptor Field 1 RDES1 Table 17 15 Receive Descriptor Field 1 RDES1 Description Bit DIC Disable Interrupt on Completion When set this bit prevents setting the Status Register s RI bit CSR5 6 for the received frame ending in the buffer indi...

Page 896: ...efer to Buffer Size Calculations 12 0 Related Information Buffer Size Calculations on page 17 26 Receive Descriptor Field 2 RDES2 on page 17 47 Receive Descriptor Field 3 RDES3 on page 17 48 Receive Descriptor Fields RDES2 and RDES3 Receive Descriptor Field 2 RDES2 Table 17 16 Receive Descriptor Field 2 RDES2 Description Bit Buffer 1 Address Pointer These bits indicate the physical address of Buff...

Page 897: ...o store the start of frame The DMA ignores RDES3 1 0 if the address pointer is to a buffer where the middle or last part of the frame is stored 31 0 Related Information Receive Descriptor Field 1 RDES1 on page 17 46 Receive Descriptor Field 4 RDES4 The extended status is written only when there is status related to IPC or timestamp available The availability of extended status is indicated by Bit ...

Page 898: ...lds are bypassed All enabled filter fields match When more than one filter matches this bit gives the layer 3 filter status of filter indicated by Bits 27 26 24 Reserved 23 15 Timestamp Dropped When set this bit indicates that the timestamp was captured for this frame but got dropped in the MTL RX FIFO buffer because of overflow 14 PTP Version When set this bit indicates that the received PTP mess...

Page 899: ...acket This bit is updated only when Bit 10 IPC of Register 0 MAC Configuration Register is set 6 IP Checksum Bypassed When set this bit indicates that the checksum offload engine is bypassed 5 IP Payload Error When set this bit indicates that the 16 bit IP payload checksum that is the TCP UDP or ICMP checksum that the EMAC calculated does not match the corresponding checksum field in the received ...

Page 900: ...imestamp The availability of the snapshot of the timestamp in RDES6 and RDES7 is indicated by Bit 7 in the RDES0 descriptor Related Information Receive Descriptor Field 0 RDES0 on page 17 43 Receive Descriptor Field 6 RDES6 Table 17 19 Receive Descriptor Field 6 RDES6 Description Bit RTSL Receive Frame Timestamp Low This field is updated by DMA with the least significant 32 bits of the timestamp c...

Page 901: ...xt steps and check this register again as mentioned in 12 on page 1 53 before triggering the DMA operations Note 4 Program the following fields to initialize the Bus Mode Register by setting values in DMA Register 0 Bus Mode Register Mixed Burst and AAL Fixed burst or undefined burst Burst length values and burst mode values Descriptor Length only valid if Ring Mode is used TX and RX DMA Arbitrati...

Page 902: ...ialization operations can be performed after DMA initialization If the MAC initialization is done before the DMA is set up then enable the MAC receiver last step below only after the DMA is active Otherwise received frames fill the RX FIFO buffer and overflow 1 Program the EMAC Register 4 GMII Address Register for controlling the management cycles for external PHY For example Physical Layer Addres...

Page 903: ...ceive 2 Set appropriate values for the descriptors ensuring that transmit and receive descriptors are owned by the DMA to resume the transmission and reception of data 3 If the descriptors are not owned by the DMA or no descriptor is available the DMA goes into SUSPEND state The transmission or reception can be resumed by freeing the descriptors and issuing a poll demand by writing 0 into the TX R...

Page 904: ...s of the PHY chip by using the MDIO interface and update Bit 17 PLS of Register 12 LPI Control and Status Register accordingly This update should be done whenever the link status in the PHY chip changes 5 Set Bit 16 LPIEN of Register 12 LPI Control and Status Register to make the MAC enter the LPI state The MAC enters the LPI mode after completing the transmission in progress and sets Bit 0 TLPIEN...

Page 905: ...can gate off the CSR clock If the MAC RX is not in the LPI mode when you gate off the CSR clock the events on the MAC receiver do not get reported or updated in the CSR For restoring the CSR clock switch on the CSR clock when the MAC has to come out of the TX LPI mode After the CSR clock is resumed reset Bit 16 LPIEN of Register 12 LPI Control and Status Register to bring the MAC out of the LPI mo...

Page 906: ...se Train immediately commands 6 Program the stop value in the Target Time registers register 455 and 456 Ensure that Bit 31 TSTRBUSY of Register 456 Target Time Nanoseconds Register is reset before programming the Target Time registers register 455 and 456 again 7 Program the PPSCMD field bit 3 0 of Register 459 PPS Control Register to 0100 This stops the train of pulses on PPS signal output after...

Page 907: ...tions scroll to and click the register names The register addresses are offsets relative to the base address of each module instance Related Information Introduction to Cyclone V Hard Processor System HPS on page 1 1 Cyclone V SoC HPS Address Map and Register Definitions Document Revision History Table 17 21 Document Revision History Changes Version Date Minor updates 2013 12 30 December 2013 Expa...

Page 908: ...k adapters Hard drives Generic hubs Portions 2013 Synopsys Inc Used with permission All rights reserved Synopsys DesignWare are registered trademarks of Synopsys Inc All documentation is provided as is and without any warranty Synopsys expressly disclaims any and all warranties express implied or otherwise including the implied warranties of merchantability fitness for a particular purpose and non...

Page 909: ... only high speed and full speed are supported Note Supports all USB transaction types Control transfers Bulk transfers Isochronous transfers Interrupts Supports automatic ping capability Supports Session Request Protocol SRP and Host Negotiation Protocol HNP Supports suspend resume and remote wake Supports up to 16 host channels In host mode when the number of device endpoints is greater than the ...

Page 910: ...ation for endpoints for small FIFO buffers and flexible efficient use of RAM that can be dynamically sized by software Ability to change an endpoint s FIFO memory size during transfers Clock gating support during USB suspend and session off modes PHY clock gating support System clock gating support Data FIFO RAM clock gating support Local buffering with error correction code ECC support The USB OT...

Page 911: ...ers for receive and transmit data packets on the USB link Through the system manager the USB OTG controller has control to use and test error correction codes ECCs in the SPRAM Through the system manager the USB OTG controller can also control the behavior of the master interface to the L3 interconnect The USB OTG controller connects to the external USB transceiver through a ULPI PHY interface Thi...

Page 912: ...ties of the master interface are controlled through the USB L3 Master HPROT Register l3master in the system manager These bits provide access information to the L3 interconnect including whether or not transactions are cacheable bufferable or privileged Bits in the l3master register can be updated only when the master interface is guaranteed to be in an inactive state Note Slave Interface The slav...

Page 913: ...plemented for each IN endpoint In host mode a single FIFO buffer stores data for all periodic isochronous and interrupt OUT endpoints and a single FIFO buffer is used for nonperiodic control and bulk OUT endpoints Host and device mode share a single receive data FIFO buffer SPRAM An SPRAM implements the data FIFO buffers for host and device modes The size of the FIFO buffers can be programmed dyna...

Page 914: ...MAC performs the following steps 1 Builds the token packet 2 Sends the packet to the device For OUT or SETUP transactions the MAC also performs the following steps 1 Reads the data from the transmit FIFO buffer 2 Assembles the data packet 3 Sends the packet to the device 4 Waits for a response The response from the device causes the MAC to send a status update to the AIU For IN or PING transaction...

Page 915: ...keup and Power Control To reduce power the USB OTG controller supports a power down mode In power down mode the controller and the PHY can shut down their clocks The controller supports wakeup on the detection of the following events Resume Remote wakeup Session request protocol New session start PHY Interface Unit The USB OTG controller supports synchronous SDR data transmission to a ULPI PHY The...

Page 916: ...t is released No special handling is required on the clocks Functional Usage Frequency Clock Signal Drives the master and slave interfaces DMA controller and internal FIFO buffers 60 200 MHz usb_mp_clk ULPI reference clock for usb0 from external ULPI PHY I O pin 60 MHz usb0_ulpi_clk ULPI reference clock for usb1 from external ULPI PHY I O pin 60 MHz usb1_ulpi_clk Resets The USB OTG controller can ...

Page 917: ... Reset Register grstctl in the Global Registers globgrp group of the USB OTG controller Software resets are useful in the following situations A PHY selection bit is changed by software Resetting the USB OTG controller is part of clean up to ensure that the PHY can operate with the new configuration or clock During software development and debugging Interrupts Table 18 4 USB OTG Interrupt Conditio...

Page 918: ...ailure to write an isochronous OUT packet to the RX FIFO buffer The RX FIFO buffer does not have enough space to accommodate the maximum packet size for the isochronous OUT endpoint Device mode Enumeration has completed Common modes Connector ID change Common modes Mode mismatch Software accesses registers belonging to an incorrect mode Common modes Nonperiodic TX FIFO buffer is empty Common modes...

Page 919: ...ndeterminate data Out of range write transactions are ignored Note Related Information USB OTG Controller Address Map and Register Definitions on page 18 15 The directfifo memory space is described in the controller address map Host Operation Host Initialization After power up the USB port is in its default mode No VBUS is applied to the USB cable The following process sets up the USB OTG controll...

Page 920: ...he requests in the following order at the beginning of each frame or microframe 1 Periodic request queue including isochronous and interrupt transactions 2 Nonperiodic request queue bulk or control transfers The host schedules transactions for each enabled channel in round robin fashion When the host controller completes the transfer for a channel the controller updates the DMA descriptor status i...

Page 921: ... data packet ID PID and the validity of the received data The DMA controller reads the data out of the FIFO buffer as the data are received If a FIFO buffer overflow condition occurs the controller responds to the OUT packet with a NAK and internally rewinds the pointers For IN endpoints the controller uses dedicated transmit buffers for each endpoint The application does not need to predict the o...

Page 922: ...m the controller 2 Retrieves the packet from the receive buffer Because the control transfer is governed by USB protocol the controller always responds with an ACK handshake USB OTG Controller Address Map and Register Definitions The address map and register definitions reside in the hps html file that accompanies this handbook volume To view the module description and base address click the hps h...

Page 923: ...bed software initializa tion in host and device modes Described software operation in host and device modes Simplified features list Simplified hardware descrip tion 1 2 November 2012 Added information about ECCs 1 1 June 2012 Initial release 1 0 January 2012 USB 2 0 OTG Controller Altera Corporation Send Feedback cv_54018 Document Revision History 18 16 2013 12 30 ...

Page 924: ... interface integrated with HPS DMA controller SPI master supports rxd sample delay Transmit and receive FIFO buffers are 256 words deep SPI master supports up to four slave selects Programmable master serial bit rate Programmable data item size of 4 to 16 bits SPI Block Diagram and System Integration The SPI supports data bus widths of 32 bits ISO 9001 2008 Registered 2013 Altera Corporation All r...

Page 925: ...RQ DMA Controller Clock Pre Scale The functional groupings of the main interfaces to the SPI block are as follows System bus interface DMA peripheral request interface Interrupt interface SPI interface Functional Description of the SPI Controller Protocol Details and Standards Compliance This chapter describes the functional operation of the SPI controller The host processor accesses data control ...

Page 926: ...lect which protocol is used The serial protocols supported by the SPI controller allow for serial slaves to be selected or addressed using hardware Serial slaves are selected under the control of dedicated hardware select lines The number of select lines generated from the serial master is equal to the number of serial slaves present on the bus The serial master device asserts the select line of t...

Page 927: ...be derived from the equation below where SPI clock is spi_m_clk for the master SPI modules and l4_main_clk for the slave SPI modules Fsclk_out F SPI clock SCKDV SCKDV is a bit field in the register BAUDR holding any even value in the range 2 to 65 534 If SCKDV is 0 then sclk_out is disabled The following equation describes the frequency ratio restrictions between the bit rate clock sclk_out and th...

Page 928: ...hen the number of entries in the FIFO buffer is less than or equal to the FIFO buffer threshold value The threshold value set through the register TXFTLR determines the level of FIFO buffer entries at which an interrupt is generated The threshold value allows you to provide early indication to the processor that the transmit FIFO buffer is nearly empty A Transmit FIFO Overflow Interrupt is generat...

Page 929: ...bove interrupt requests after masking To mask this interrupt signal you must mask all other SPI interrupt requests Transmit FIFO Overflow Transmit FIFO Empty Receive FIFO Full Receive FIFO Underflow and Receive FIFO Overflow interrupts can all be masked independently using the Interrupt Mask Register IMR Transfer Modes When transferring data on the serial bus the SPI controller operates one of sev...

Page 930: ...er initiates and controls all serial transfers with serial slave peripheral devices The serial bit rate clock generated and controlled by the SPI controller is driven out on the sclk_out line When the SPI controller is disabled no serial transfers can occur and sclk_out is held in inactive state as defined by the serial protocol under which it operates Related Information SPI Block Diagram on page...

Page 931: ...t set when the data are written into the transmit FIFO buffer This bit gets set only when the target slave has been selected and the transfer is underway After writing data into the Note transmit FIFO buffer the shift logic does not begin the serial transfer until a positive edge of the sclk_out signal is present The delay in waiting for this positive edge depends on the baud rate of the serial tr...

Page 932: ...he opcode and or address into the transmit FIFO buffer when a serial slave EEPROM is selected The opcode and address are transmitted to the EEPROM device after which read data is received from the EEPROM device and stored in the receive FIFO buffer The end of the serial transfer is controlled by the NDF field in the control register 1 CTRLR1 EEPROM read mode is not supported when the SPI controlle...

Page 933: ...are propagated from the serial slave on one edge of the serial clock line and sampled on the opposite edge When the SPI serial slave is not selected it must not interfere with data transfers between the serial master and other serial slave devices When the serial slave is not selected its txd output is buffered resulting in a high impedance drive onto the SPI master rxd line The buffers shown in t...

Page 934: ...ata frame is resent on txd For continuous data transfers you must ensure that the transmit FIFO buffer does not become empty before all the data have been transmitted The transmit FIFO threshold level register TXFTLR can be used to early interrupt Transmit FIFO Empty Interrupt the processor indicating that the transmit FIFO buffer is nearly empty When a DMA Controller is used the DMA transmit data...

Page 935: ...gth Data transmission begins on the falling edge of the slave select signal The first data bit is captured by the master and slave peripherals on the first edge of the serial clock therefore valid data must be present on the txd and rxd lines prior to the first serial clock edge The slave select signal takes effect only when used as slave SPI For master SPI the data transmission begins as soon as ...

Page 936: ... transfers transfer mode field 9 8 of the Control Register 0 3 opcode and or EEPROM address are written into the transmit FIFO buffer During transmission of these control frames received data is not captured by the SPI master After the control frames have been transmitted receive data from the EEPROM is stored in the receive FIFO buffer Related Information Transfer Modes on page 19 6 Texas Instrum...

Page 937: ... word for the next transfer following immediately after the LSB of the current data word The only modification needed to perform a continuous nonsequential transfer is to write more control words into the transmit FIFO buffer During sequential continuous transfers only one control word is transmitted from the SPI master The transfer is started in the same manner as with nonsequential read operatio...

Page 938: ...tion of the data word is controlled by the MDD bit field bit 1 MWCR register When MDD 0 this indicates that the SPI serial slave is to receive data from the external serial master Immediately after the control word is transmitted the serial master begins to drive the data frame onto the SPI slave rxd line Data are propagated on the falling edge of the serial clock and captured on the rising edge T...

Page 939: ...oller are byte addressable The maximum width of the control or status register in the SPI controller is 16 bits Therefore all read and write operations to the SPI control and status registers require only one access Data Register Access The data register DR within the SPI controller is 16 bits wide in order to remain consistent with the maximum serial transfer size data frame A write operation to ...

Page 940: ...ection describes the programming model for the SPI controller based on the following master and slave transfers Master SPI and SSP Serial Transfers Master Microwire Serial Transfers Slave SPI and SSP Serial Transfers Slave Microwire Serial Transfers Software Control for Slave Selection Altera Corporation SPI Controller Send Feedback 19 17 SPI Programming Model cv_54019 2013 12 30 ...

Page 941: ...transmit FIFO If the receive FIFO makes the request read data from the receive FIFO TMOD 01 TMOD 10 Read Rx FIFO Interrupt Service Routine Wait for Master to Select Slave To complete an SPI or SSP serial transfer from the SPI master follow these steps 1 If the SPI master is enabled disable it by writing 0 to the SSI Enable register SSIENR 2 Set up the SPI master control registers for the transfer ...

Page 942: ...ble the target slave for selection If a slave is enabled here the transfer begins as soon as one valid data entry is present in the transmit FIFO buffer If no slaves are enabled prior to writing to the Data Register DR the transfer does not begin until a slave is enabled 3 Enable the SPI master by writing 1 to the SSIENR register 4 Write data for transmission to the target slave into the transmit ...

Page 943: ...ata to Tx FIFO Transfer in Progress Interrupt yes no Busy yes no If the master receives data the user only needs to write control frames into the TX FIFO Transfer begins when the first control word is present in the transmit FIFO and a slave is enabled If the transmit FIFO makes the request and all data has not been sent write data to the transmit FIFO If the receive FIFO makes the request read da...

Page 944: ...aves are enabled prior to writing to the DR register the transfer does not begin until a slave is enabled 3 Enable the SPI master by writing 1 to the SSIENR register 4 If the SPI master transmits data write the control and data words into the transmit FIFO buffer write DR If the SPI master receives data write the control word or words into the transmit FIFO buffer If no slaves were enabled in the ...

Page 945: ...ENR Slave SPI and SSP Serial Transfers Figure 19 13 Slave SPI or SSP Serial Transfer Software Flow Idle Disable SPI Configure Slave by Writing CTRLR0 CTRLR1 TXFTLR RXFTLR MWCR IMR Enable SPI Write Data to Tx FIFO Transfer in Progress Interrupt yes no Busy yes no If the transmit FIFO makes the request and all data has not been sent write data to the transmit FIFO If the receive FIFO makes the reque...

Page 946: ...e FIFO full interrupt request is made read the receive FIFO buffer read DR 7 The transfer ends when the serial master removes the select input to the SPI slave When the transfer is completed the BUSY status is reset to 0 8 If the transfer mode is not transmit only TMOD 01 read the receive FIFO buffer until empty 9 Disable the SPI slave by writing 0 to SSIENR Slave Microwire Serial Transfers For SP...

Page 947: ... information about the DMA operation refer to the ARM DMA chapter Related Information DMA Controller on page 16 1 For details about the DMA controller refer to the DMA Controller chapter Transmit FIFO Buffer Underflow During SPI serial transfers transmit FIFO buffer requests are made to the DMA Controller whenever the number of entries in the transmit FIFO buffer is less or equal to the value in D...

Page 948: ...st transactions in the DMA block transfer is 5 But the watermark level DMATDLR is quite low Therefore the probability of transmit underflow is high where the SPI serial transmit line needs to transmit data but there is no data left in the transmit FIFO buffer This occurs because the DMA has not had time to service the DMA request before the FIFO buffer becomes empty Case 2 DMATDLR 192 Transmit FIF...

Page 949: ...not overflowed at the completion of the burst transaction Therefore for optimal operation DMA burst length should be set at the FIFO buffer level that triggers a transmit DMA request that is DMA burst length FIFO_DEPTH DMATDLR Adhering to this equation reduces the number of DMA bursts needed for block transfer and this in turn improves bus utilization The transmit FIFO buffer will not be full at t...

Page 950: ...ived one data item or more on the serial receive line during the burst Note Figure 19 16 Receive FIFO Buffer DMARDLR 1 DMA Controller Transmit FIFO Watermark Level Data In Data Out Empty Full Receive FIFO Buffer SPI Controller Address Map and Register Definitions The address map and register definitions reside in hps html file that accompanies this handbook volume Click the link to open the file T...

Page 951: ...ng updates 2013 12 30 December 2013 Minor updates 1 2 November 2012 Added programming model address map and register definitions clocks and reset sections 1 1 May 2012 Initial release 1 0 January 2012 SPI Controller Altera Corporation Send Feedback cv_54019 Document Revision History 19 28 2013 12 30 ...

Page 952: ...rade Paragraphs marked with the dagger symbol are Synopsys Proprietary Used with permission Features of the I 2 C Controller The I2 C controller has the following features Maximum clock speed of up to 400 Kbps One of the following I2 C operations A master in an I2 C system and programmed only as a master A slave in an I2 C system and programmed only as a slave 7 or 10 bit addressing Mixed read and...

Page 953: ...s Register Block Slave Interface L4 Peripheral Bus The I2 C controller consists of the following modules and interfaces Slave interface for control and status register CSR accesses and DMA transfers allowing a master to access the CSRs and the DMA to read or write data directly Two FIFO buffers for transmit and receive data which hold the Rx FIFO and Tx FIFO buffer register banks and controllers a...

Page 954: ...slave only communicating with one or more I2 C masters The master is responsible for generating the clock and controlling the transfer of data The slave is responsible for either transmitting or receiving data to from the master The acknowledgement of data is sent by the device that is receiving data which can be either a master or a slave As mentioned previously the I2 C protocol also allows mult...

Page 955: ...een supplied to it This stalls the I2 C bus until read data is provided to the slave I2 C controller or the I2 C controller slave is disabled by writing a 0 to IC_ENABLE register Combined Formats The I2 C controller supports mixed read and write combined format transactions in both 7 bit and 10 bit addressing modes The I2 C controller does not support mixed address and mixed address format that is...

Page 956: ...an incorrect SDA or SCL timing relationship Addressing Slave Protocol 7 Bit Address Format During the 7 bit address format the first seven bits bits 7 1 of the first byte set the slave address and the LSB bit bit 0 is the R W bit as shown in the following figure When bit 0 R W is set to 0 the master writes to the slave When bit 0 R W is set to 1 the master reads from the slave Figure 20 4 7 Bit Ad...

Page 957: ...0000 1XX Reserved X 1111 1XX 10 bit slave addressing X 1111 0XX Note to Table 1 X indicates do not care Related Information START BYTE Transfer Protocol on page 20 8 Transmitting and Receiving Protocol The master can initiate data transmission and reception to or from the bus acting as either a master transmitter or master receiver A slave responds to requests from the master to either transmit da...

Page 958: ... that this is the last byte The slave transmitter relinquishes the SDA line after detecting the No Acknowledge NACK bit so that the master can issue a STOP condition When a master does not want to relinquish the bus with a STOP condition the master can issue a RESTART condition This is identical to a START condition except it occurs after the ACK pulse Operating in master mode the I2 C controller ...

Page 959: ...t used on the bus 4 No slave sets the ACK signal to 0 5 Master generates a RESTART R condition A hardware receiver does not respond to the START BYTE because it is a reserved address and resets after the RESTART condition is generated Multiple Master Arbitration The I2 C controller bus protocol allows multiple masters to reside on the same bus If there are two masters on the same I2 C bus there is...

Page 960: ...id only during the high period of SCL clock Clock synchronization is performed using the wired AND connection to the SCL signal When the master transitions the SCL clock to 0 the master starts counting the low time of the SCL clock and transitions the SCL clock signal to 1 at the beginning of the next clock period However if another master is holding the SCL line to 0 then the master goes into a H...

Page 961: ...ount registers is 8 while the minimum value allowed for the SCL high count registers is 6 The minimum value of 8 for the low count registers is due to the time required for the I2 C controller to drive SDA after a negative edge of SCL The minimum value of 6 for the high count register is due to the time required for the I2 C controller to sample SDA during the high period of SCL The I2 C controlle...

Page 962: ...s for 400 kbps 120 ns for 3 4Mbs bus loading 100pF 320 ns for 3 4Mbs bus loading 400pF OSCFREQ l4_sp_clk clock frequency Hz For example OSCFREQ 100 MHz I2Cmode fast 400 kbps MIN_SCL_HIGHtime 600 ns MIN_SCL_LOWtime 1300 ns IC_HCNT ceil 600 ns 100 MHz IC_HCNTSCL PERIOD 60 IC_LCNT ceil 1300 ns 100 MHz IC_LCNTSCL PERIOD 130 Actual MIN_SCL_HIGHtime 60 1 100 MHz 600 ns Actual MIN_SCL_LOWtime 130 1 100 M...

Page 963: ...ion DMA Controller on page 16 1 For details about the DMA burst length microcode setup refer to the DMA controller chapter of the Cyclone V Device Handbook Volume 3 Clocks Each I2 C controller is connected to the l4_sp_clk clock which clocks transfers in standard and fast mode The clock input is driven by the clock manager Related Information Clock Manager on page 2 1 For more information refer to...

Page 964: ...2C controller should be set to operate only as an I2 C master or as an I2 C slave never both simultaneously Ensure that bit 6 IC_SLAVE_DISABLE and 0 IC_MASTER_MODE of the IC_CON register are never set to 0 and 1 respectively Note Slave Mode Operation Initial Configuration To use the I2 C controller as a slave perform the following steps 1 Disable the I2 C controller by writing a 0 to bit 0 of the ...

Page 965: ...the I2 C controller can handle For example for 400 Kbps the timing interval is 25 us The value of 10 is recommended here because this is approximately the amount of time required for a single byte of data transferred on the I2 C bus Note 4 If there is any data remaining in the TX FIFO before receiving the read request the I2 C controller asserts a TX_ABRT interrupt bit 6 of the IC_RAW_INTR_STAT re...

Page 966: ...than 0 then it is recommended that the CPU does periodic reads of the IC_STATUS register Reads of the IC_STATUS register with bit 3 RFNE set at 1 must then be treated by software as the equivalent of the RX_FULL interrupt being asserted 5 Software may read the byte from the IC_DATA_CMD register bits 7 0 6 The other master device may hold the I2 C bus by issuing a RESTART condition or release the b...

Page 967: ...e TX FIFO are cleared at that time Master Mode Operation Initial Configuration For master mode operation the target address and address format can be changed dynamically without having to disable the I2 C controller This feature is only applicable when the I2 C controller is acting as a master because the slave requires the component to be disabled before any changes can be made to the address To ...

Page 968: ...he highest I2 C transfer speed used in the system and supported by the I2 C controller For example if the highest I2 C transfer mode is 400 Kbps then ti2c_poll is 25 us 2 Define a maximum time out parameter MAX_T_POLL_COUNT such that if any repeated polling operation exceeds this maximum value an error is reported 3 Execute a blocking thread process function that prevents any further I2 C master t...

Page 969: ... to stall the transfer by holding the SCL line low To prevent this condition you must set the watermark level correctly Related Information DMA Controller on page 16 1 For details about the DMA burst length microcode setup refer to the DMA controller chapter of the Cyclone V Device Handbook Volume 3 Transmit Watermark Level Consider the example where the assumption is made DMA burst length FIFO_DE...

Page 970: ... the watermark level IC_ DMA_TDLR is high Therefore the probability of I2 C transmit underflow is low because the DMA controller has plenty of time to service the destination burst transaction request before the I2 C transmit FIFO becomes empty Thus the second case has a lower probability of underflow at the expense of more burst transactions per block This provides a potentially greater amount of...

Page 971: ...ow To prevent this condition the user must set the watermark level correctly Receive Watermark Level Similar to choosing the transmit watermark level described earlier the receive watermark level IC_ DMA_RDLR 1 should be set to minimize the probability of overflow as shown in the Receive FIFO Buffer diagram It is a trade off between the number of DMA burst transactions required per block versus th...

Page 972: ...and click the register names The register addresses are offsets relative to the base address of each module instance Related Information Introduction to Cyclone V Hard Processor System HPS on page 1 1 For more information refer to Introduction to the Hard Processor System hps html For more information refer to the hps html chapter of the Cyclone V handbook Document Revision History Table 20 5 Docu...

Page 973: ...mming model address map and register definitions clocks reset and interface pins sections 1 1 May 2012 Initial release 1 0 January 2012 I2C Controller Altera Corporation Send Feedback cv_54020 Document Revision History 20 22 2013 12 30 ...

Page 974: ...n Automatic flow control mode per 16750 standard Internal loopback mode support 128 bit transmit and receive FIFO buffer depth FIFO buffer status registers FIFO buffer access mode for FIFO buffer testing enables write of receive FIFO buffer by master and read of transmit FIFO buffer by master Shadow registers reduce software overhead and provide programmable reset Transmitter holding register empt...

Page 975: ...oller supports transfer rates of 95 baud to 6 25 Mbaud This supports communication with all known 16550 devices The baud rate is controlled by programming the interrupt enable or divisor latch high IER_DLH and receive buffer transmit holding or divisor latch low RBR_THR_DLL registers Baud clock generator Converts parallel data written to the UART into serial data and adds all additional bits as sp...

Page 976: ...buffer access mode is enabled with the FIFO access register FAR Once enabled the control portions of the transmit and receive FIFO buffers are reset and the FIFO buffers are treated as empty When FIFO buffer access mode is enabled you can write data to the transmit FIFO buffer as normal however no serial transmission occurs in this mode and no data leaves the FIFO buffer You can read back the data...

Page 977: ...the character T is received because rts_n is not detected prior to the next character entering the sending UART transmitter Figure 21 2 Automatic RTS Timing sin rts_n rx_fifo_read start character T stop start character T 1 stop 1 2 3 T T 1 Automatic CTS mode Automatic CTS mode becomes active when the following conditions occur AFCE MCR AFCE bit is set FIFO buffers are enabled through FIFO buffer c...

Page 978: ...on refer to the Reset Manager chapter Interrupts The assertion of the UART interrupt output signal occurs when one of the following interrupt types are enabled and active Table 21 2 Interrupt Types and Priority Priority Interrupt Type Highest Receiver line status Second Received data available Second Character timeout indication Third Transmit holding register empty You can enable the interrupt ty...

Page 979: ... the transmit FIFO buffer is empty to indicating that the FIFO buffer is full This change allows software to fill the FIFO buffer for each transmit sequence by polling LSR THRE before writing another character This directs the UART to fill the transmit FIFO buffer whenever an interrupt occurs and there is data to transmit instead of waiting until the FIFO buffer is completely empty Waiting until t...

Page 980: ...nsfers The FIFO buffer depth FIFO_DEPTH for both the RX and TX buffers in the UART controller is 128 entries Related Information DMA Controller on page 16 1 For more information refer to this DMA Controller chapter Transmit FIFO Underflow During UART serial transfers transmit FIFO requests are made to the DMA controller whenever the number of entries in the transmit FIFO is less than or equal to t...

Page 981: ...mark level of IIR_FCR TET 16 DMA burst length FIFO_DEPTH decoded watermark level of IIR_FCR TET 112 UART transmit FIFO_DEPTH 128 Block transaction size R 448 Figure 21 6 Transmit FIFO Watermark Level 16 Data In Decoded watermark level of IIR_FCR TET 16 FIFO_DEPTH IIR_FCR TET 112 FIFO_DEPTH 128 Transmit FIFO Watermark Level Data Out Empty Full Transmit FIFO Buffer DMA Controller The number of burst...

Page 982: ...ition to an acceptable level In practice this is a function of the ratio of the rate at which the UART transmits data to the rate at which the DMA can respond to destination burst requests Transmit FIFO Overflow Setting the DMA burst length to a value greater than the watermark level that triggers the DMA request might cause overflow when there is not enough space in the transmit FIFO to service t...

Page 983: ...an cause underflow where there is not enough data to service the source burst request Therefore the following equation must be adhered to avoid underflow DMA burst length decoded watermark level of IIR_FCR RT 1 If the number of data items in the receive FIFO is equal to the source burst length at the time of the burst request is made the receive FIFO may be emptied but not underflowed at the compl...

Page 984: ...PS on page 1 1 For more information refer to the Introduction to the Hard Processor System chapter of the Cyclone V Device Handbook Volume 3 hps html For more information refer to hps html Document Revision History Table 21 3 Document Revision History Changes Version Date Minor formatting updates 2013 12 30 December 2013 Minor updates 1 2 November 2012 Added programming model address map and regis...

Page 985: ...orts up to 62 I O pins GPIO Interface Block Diagram and System Integration The figure below shows a block diagram of the GPIO interface The following table shows a pin table of the GPIO interface ISO 9001 2008 Registered 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered...

Page 986: ...s that are less than one period of the external debouncing clock gpio_db_clk When input interrupt signals are debounced using the gpio_db_clk debounce clock the signals must be active for a minimum of two cycles of the debounce clock to guarantee that they are registered Any input pulse widths less than a debounce clock period are filtered out If the input signal pulse width is between one and two...

Page 987: ...nal before the debounce capability is enabled Under software control the direction of the external I O pad is controlled by a write to the gpio_swportx_ddr register When configured as input mode reading gpio_ext_porta would read the values on the signal of the external I O pad When configured as output mode the data written to the gpio_swporta_dr register drives the output buffer of the I O pad Th...

Page 988: ...ocument Revision History Table 22 2 Document Revision History Changes Version Date Minor formatting updates Updated GPIO interface block diagram and GPIO interface pin table 2013 12 30 December 2013 Minor updates 1 2 November 2012 Added programming model section 1 1 May 2012 Initial release 1 0 January 2012 General Purpose I O Interface Altera Corporation Send Feedback cv_54022 Document Revision H...

Page 989: ...orts user defined count mode Timer Block Diagram and System Integration Each timer includes a slave interface for control and status register CSR access a register block and a programmable 32 bit down counter that generates interrupts on reaching zero The timer operates on a single clock domain driven by the clock manager ISO 9001 2008 Registered 2013 Altera Corporation All rights reserved ALTERA ...

Page 990: ...pt Decrements from the user defined count value loaded from the timer1 load count register timer1loadcount Reloads the user defined count upon reaching zero The initial value for the timer that is the value from which it counts down is loaded into the timer by the timer1loadcount register The following events can cause a timer to load the initial count from the timer1loadcount register Timer is en...

Page 991: ...k the interrupt In both the free running and user defined count modes of operation the timer generates an interrupt signal when the timer count reaches zero and the interrupt mask bit of the control register is high If the timer interrupt is set then it is cleared when the timer is disabled Timer Programming Model Initialization To initialize the timer perform the following steps 1 Initialize the ...

Page 992: ...er Free running mode timer loads the maximum value 0xFFFFFFFF The timer max count value allows for a maximum amount of time to reprogram or disable the timer before another interrupt occurs Use this mode if you want a single timed interrupt Enable this mode by writing a 0 to the timer1_mode bit of the timer1controlreg register Servicing Interrupts Clearing the Interrupt An active timer interrupt c...

Page 993: ...s of each module instance Related Information Introduction to Cyclone V Hard Processor System HPS on page 1 1 For more information refer to the Introduction to the Hard Processor System chapter hps html For more information refer to this hps html chapter of the Cyclone V Device Handbook Document Revision History Table 23 2 Document Revision History Changes Version Date Minor formatting upates 2013...

Page 994: ...eout range Timer counts down from a preset value to zero then performs one of the following user configurable operations Generates a system reset Generates an interrupt restarts the timer and if the timer is not cleared before a second timeout occurs generates a system reset Dual programmable timeout period used when the time to wait after the first start is different than that required for subseq...

Page 995: ...tle endian down counter that decrements by one on each clock cycle The watchdog timer supports 16 fixed timeout period values and software chooses which timeout periods are desired A timeout period is 2n osc1_clk clock periods where n is an integer from 16 to 31 inclusive If the counter reaches zero the watchdog timer has timed out indicating an unrecoverable error has occurred and a system reset ...

Page 996: ...ystem manager pauses the watchdog timer while debugging When pause mode is disabled the watchdog timer runs even while debugging When the system manager exits reset the watchdog pausing feature is enabled for both CPUs by default Related Information Pausing a Watchdog Timer on page 24 4 Watchdog Timer Clocks Each watchdog timer is connected to the osc1_clk clock so that timer operation is not depe...

Page 997: ...e watchdog timer control register wdt_cr 2 To generate an interrupt and restart the timer when a timeout occurs write 1 to the rmod field of the wdt_cr register If a restart occurs at the same time the watchdog counter reaches zero a system reset is not generated Related Information Watchdog Timer Counter on page 24 2 Enabling and Initially Starting a Watchdog Timer 1 To enable and start a watchdo...

Page 998: ...T_CRR Counter 0 Counter 0 and WDT_CR RMOD 1 Counter 0 Counter 0 and WDT_CR RMOD 0 Software Reads WDT_EOI or Writes 0x76 to WDT_CRR Counter 0 Software Sets Initial and Restart Timeout Periods WDT_TORR Sets Output Response Mode WDT_CR RMOD and Enables the Timer WDT_CR WDT_EN System Reset Timer Disabled If the counter reaches zero the state changes based on the value of the output response mode setti...

Page 999: ...ule description and base address scroll to and click the link for either of the following module instances l4wd0 l4wd1 To then view the register and field descriptions scroll to and click the register names The register addresses are offsets relative to the base address of each module instance Related Information Introduction to Cyclone V Hard Processor System HPS on page 1 1 For more information ...

Page 1000: ...bsite ISO 9001 2008 Registered 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described a...

Page 1001: ...rotocol functions Message handler State machine that controls the data transfer between the message RAM and CAN core Handles acceptance filtering and the interrupt generation Message RAM Storage for up to 128 messages objects Single bit error correction and double bit error detection Message RAM interface Two separate interfaces IF1 and IF2 Register block Control and status registers CSR for modul...

Page 1002: ...re handled through the IF1 and IF2 message interface registers The following table shows the structure of a message object where the first row contains the message object control flags the second row contains the message object masks and the third row is the CAN message Table 25 1 Message Object Structure EoB TxRqst RmtEn RxIE TxIE IntPnd MsgLst NewDat MsgVal MDir MXtd Msk 28 0 UMask Data 7 7 0 Da...

Page 1003: ...sor has lost a message MsgLst is valid only in message objects with the message direction bit Dir set to receive Interrupt Pending IntPnd 0 This message object is not the source of an interrupt 1 This message object is the source of an interrupt The interrupt identifier field in the CAN interrupt register CIR points to this message object if there is no other interrupt source with higher priority ...

Page 1004: ...ive or is a remote frame with message direction set to 1 transmit The received message identifier matches the message identifier ID 28 0 of the message object The received identifier extension bit matches the identifier extension bit Xtd of the message object 1 Use mask Msk 28 0 MXtd and MDir for acceptance filtering if the respective mask bits are set up for acceptance filtering For an incoming m...

Page 1005: ...d frames can be stored only in message objects with Xtd is set to 1 standard frames in message objects with Xtd is set to 0 If a received message data frame or remote frame matches more than one valid message object it is stored to the object with the lowest message number Message Identifier ID 28 0 on page 25 6 Extended Frame Identifier Xtd on page 25 6 Message Direction Dir on page 25 6 Data Len...

Page 1006: ...d mask fields of the message object IFx mask register IFxMSK Message buffer Provides access to the ID Dir Xtd and MsgVal arbitration fields of the message object IFx arbitration register IFxARB Provides access to the DLC EoB TxRqst RmtEn RxIE TxIE UMask IntPnd MsgLst and NewDat fields of the message object IFx message control register IFxMCTR Provides access to data bytes 0 3 of the message object...

Page 1007: ...troller is able to receive valid data frames and valid remote frames but it holds the CAN_TXD pin high sending no data to the CAN bus The silent mode can be used to analyze the traffic on a CAN bus without affecting it by the transmission of dominant bits acknowledge bits error frames In ISO 11898 1 the silent mode is called the bus monitoring mode Figure 25 2 CAN Core in Silent Mode CAN Controlle...

Page 1008: ...rface The slave interface supports 32 bit accesses only This interface does not support error responses Note Clocks The CAN controller operates on the l4_sp_clk and can_clk clock inputs The l4_sp_clk clock is used by the L4 slave interface and the can_clk is used to operate the CAN core The can_clk clock must be programmed to be at least eight times the CAN bus interface speed For example for a CA...

Page 1009: ...hronized to both clock domains and applied to the appropriate logic within the CAN controllers Related Information Reset Manager on page 3 1 For more information refer to the Reset Manager chapter of the Cyclone V Device Handbook Volume 3 Interrupts Each CAN controller generates two interrupt signals One signal indicates error and status interrupts and the other signal indicates message object int...

Page 1010: ...to 96 Interrupt pending C register MOIPC 97 to 128 Interrupt pending D register MOIPD The MOIPX register allows software to quickly detect which message object group has a pending interrupt CAN Controller Programming Model Software Initialization The software initialization is started by setting the Init bit in the CAN control register CCTRL to 1 While the Init bit is 1 messages are not transferre...

Page 1011: ...handler guarantees data consistency when the host processor accesses the message object at the same time the message is being transferred to or from RAM Messages to be transmitted are updated by the host processor If a permanent message object arbitration and control bits set up during configuration are unchanged for multiple CAN transfers exists for the message only the data bytes need to be upda...

Page 1012: ...ata7 7 0 TxRqst NewDat MsgLst IntPnd Message Object Reconfiguration for Frame Transmission To configure a message object to transmit data frames set the Dir field to 1 and either set UMask to 0 or set RmtEn to 1 Before changing any of the following configuration and control bits you must set MsgVal to 0 Dir RxIE TxIE RmtEn EoB UMask Msk 28 0 MXtd MDir The following fields of a message object can b...

Page 1013: ...S on page 1 1 The base addresses of all modules are also listed in the Introduction to the Hard Processor System chapter in the Cyclone V Device Handbook Volume 3 hps html For more information refer to this hps html chapter of the Cyclone V Device Handbook Document Revision History Table 25 4 Document Revision History Changes Version Date Minor formatting updates 2013 12 30 December 2013 Minor upd...

Page 1014: ...l architectures and features The chapters that describe these features can be found on the Cyclone V documentation page Clock manager Reset manager Interconnect HPS FPGA AXI Bridge Cortex A9 Microprocessor Unit Subsystem CoreSight Debug and Trace SDRAM Controller Subsystem On Chip RAM and boot block ROM NAND Flash Controller SD MMC Controller Quad SPI Flash Controller FPGA Manager Block Diagram an...

Page 1015: ...ontains links to documentation that describes all features and peripherals in detail Cyclone V Device Datasheet For a description of the HPS and its integration into the system on a chip SoC Document Revision History Table 26 1 Document Revision History Changes Version Date 2013 12 30 December 2013 Maintenance release 1 0 June 2012 Preliminary draft 0 1 May 2012 Introduction to the HPS Component A...

Page 1016: ..._even ts Enables interfaces that perform the following functions Notify the FPGA fabric that the microprocessor unit MPU is in standby mode Wake up an MPCore processor from a wait for event WFE state Enable MPU standby and event signals ISO 9001 2008 Registered 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are tradem...

Page 1017: ...face h2f_tpiu h2f_tpiu_clock_in Enables an interface between the trace port interface unit TPIU and logic in the FPGA The TPIU is a bridge between on chip trace sources and a trace port 1 Enable FPGA Trace Port Interface Unit Boot and Clock Selection Interfaces This section describes parameters in the Boot and Clock Selection group in the FPGA Interfaces tab Table 27 2 Boot and Clock Selection Par...

Page 1018: ...bits Lightweight HPS to FPGA interface width The Altera Address Span Extender To facilitate accessing these slaves from a memory mapped master with a smaller address width you can use the Altera Address Span Extender Related Information Using the Address Span Extender Component on page 27 10 Address span extender details FPGA to HPS SDRAM Interface This section describes parameters in the FPGA to ...

Page 1019: ...Parameters Parameter Description Parameter Name Port name auto assigned as shown inTable 27 5 table below Name Interface type AXI 3 Avalon MM Bidirectional Avalon MM Write only Avalon MM Read only Type 32 64 128 or 256 Width Table 27 5 FPGA to HPS SDRAM Port and Interface Names Interface Name Port Name f2h_sdram0_data f2h_sdram0 f2h_sdram1_data f2h_sdram1 f2h_sdram2_data f2h_sdram2 f2h_sdram3_data...

Page 1020: ...more information about the reset interfaces refer to Functional Description of the Reset Manager in the Reset Manager chapter in the Cyclone V Device Handbook Volume 3 DMA Peripheral Request This section describes parameters in the DMA Peripheral Request group on the FPGA Interfaces tab You can enable each direct memory access DMA controller peripheral request ID individually Each request ID enabl...

Page 1021: ...TPIU Enabling the TPIU exposes trace signals to the device pins Refer to the CoreSight Debug and Trace for more information NAND Flash Controller on page 10 1 SD MMC Controller on page 11 1 Secure Digital MultiMediaCard SD MMC Controller chapter in the Cyclone V Device Handbook Volume 3 Quad SPI Flash Controller on page 12 1 Quad serial peripheral interface SPI Flash Controller chapter in the Cycl...

Page 1022: ...u enable a user clock you must manually enter its maximum frequency for timing analysis The TimeQuest Timing Analyzer has no other information about how software running on the HPS configures the phase locked loop PLL outputs Each possible clock including clocks that are available from peripherals has its own parameter for describing the clock frequency User Clock Parameters The frequencies that y...

Page 1023: ...e 27 8 PLL Reference Clock Parameters Clock Interface Name Parameter Description Parameter Name f2h_periph_ref_clock Enable the interface for FPGA fabric to supply reference clock to HPS peripheral PLL Enable FPGA to HPS peripheral PLL reference clock f2h_sdram_ref_clock Enable the interface for FPGA fabric to supply reference clock to HPS SDRAM PLL Enable FPGA to HPS SDRAM PLL reference clock Rel...

Page 1024: ... analysis Note The HPS memory controller cannot be bonded with a memory controller on the FPGA portion of the device For detailed information about SDRAM controller parameters refer to the following chapters Related Information Selecting PLL Output Frequency and Phase on page 27 9 Implementing and Parameterizing Memory IP The Implementing and Parameterizing Memory IP chapter in the External Memory...

Page 1025: ...address span extender between a soft logic master and an FPGA to HPS bridge or FPGA to HPS SDRAM interface This component reduces the number of address bits required for a master to address a memory mapped slave interface located in the HPS Figure 27 1 Address Span Extender Components Two address span extender components used in a system with the HPS M M M S M S M 4 GB 4 GB 4 GB 1 GB 512 MB 512 MB...

Page 1026: ...Interface Handbook Note You do not need to specify pin assignments other than memory assignments When you configure pin multiplexing as described in Configuring Peripheral Pin Multiplexing you implicitly make pin assignments for all HPS peripherals Each peripheral is routed exclusively to the pins you specify HPS I O signals are exported to the top level of the Qsys design with information enablin...

Page 1027: ... Maintenance release 2013 12 30 December 2013 Added debug interfaces Added boot options Corrected slave address width Corrected SDRAM interface widths Added TPIU peripheral Added sdc file generation Added tcl script for memory assignments 1 1 November 2012 Initial release 1 0 June 2012 Preliminary draft 0 1 May 2012 Instantiating the HPS Component Altera Corporation Send Feedback cv_54027 Document...

Page 1028: ... AMBA Advanced eXtensible Interface AXI protocol timing refer to the AMBA AXI Protocol Specification v1 0 which you can download from the ARM info center website ISO 9001 2008 Registered 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark O...

Page 1029: ...rough the use of soft logic adaptors The Qsys system integration tool automatically generates adaptor logic to connect AXI to Avalon MM interfaces This interface has an address width of 32 bits To access existing Avalon MM AXI masters you can use the Altera Address Span Extender Related Information Clocks on page 28 5 Features of the AXI Bridges For more information refer to the HPS FPGA AXI Bridg...

Page 1030: ...bric such as connecting to Avalon MM interfaces can be supported through the use of soft logic adaptors The Qsys system integration tool automatically generates adaptor logic to connect AXI to Avalon MM interfaces Each AXI bridge accepts a clock input from the FPGA fabric and performs clock domain crossing internally The exposed AXI interface operates on the same clock domain as the clock supplied...

Page 1031: ...llowing ways AXI 3 or Avalon MM protocol Number of interfaces Data width of interfaces The FPGA to HPS SDRAM interface supports six command ports allowing up to six Avalon MM interfaces or three bidirectional AXI interfaces Each command port is available either to implement a read or write command port for AXI or to form part of an Avalon MM interface You can use a mix of Avalon MM and AXI interfa...

Page 1032: ...A to HPS bridge The FPGA to HPS and HPS to FPGA interfaces are synchronized to clocksgenerated in the FPGA fabric These interfaces can be asynchronous to one another The SDRAM controller s multiport front end MPFE transfers the data between the FPGA and HPS clock domains f2h_axi_clock AXI slave clock for FPGA to HPS bridge generated in FPGA fabric h2f_axi_clock AXI master clock for HPS to FPGA bri...

Page 1033: ...llow soft logic in the FPGA fabric to reset the HPS f2h_cold_reset_req FPGA to HPS cold reset request f2h_warm_reset_req FPGA to HPS warm reset request f2h_dbg_reset_req FPGA to HPS debug reset request Debug and Trace Interfaces Trace Port Interface Unit The TPIU is a bridge between on chip trace sources and a trace port h2f_tpiu h2f_tpiu_clock_in FPGA System Trace Macrocell Events Interface The s...

Page 1034: ...eral request interface 1 f2h_dma_req2 FPGA DMA controller peripheral request interface 2 f2h_dma_req3 FPGA DMA controller peripheral request interface 3 f2h_dma_req4 FPGA DMA controller peripheral request interface 4 f2h_dma_req5 FPGA DMA controller peripheral request interface 5 f2h_dma_req6 FPGA DMA controller peripheral request interface 6 f2h_dma_req7 FPGA DMA controller peripheral request int...

Page 1035: ...the wait for interrupt WFI state h2f_mpu_gp General purpose interface The MPU provides signals to indicate when it is in a standby state These signals are available to custom hardware designs in the FPGA fabric Related Information Cortex A9 MPCore on page 6 4 For more information refer to Cortex A9 MPU Subsystem FPGA to HPS Interrupts You can configure the HPS component to provide 64 general purpo...

Page 1036: ...pdated HPS to FPGA reset interface names Updated HPS external reset source interface names Removed DMA peripheral interface clocks Referred to Altera Address Span Extender 1 1 November 2012 Initial release 1 0 June 2012 Preliminary draft 0 1 May 2012 Altera Corporation HPS Component Interfaces Send Feedback 28 9 Document Revision History cv_54028 2013 12 30 ...

Page 1037: ...r unit MPU general purpose I O interface MPU standby and event interface Interrupts interface Direct memory access DMA controller peripheral request interface Debug Advanced Peripheral Bus APB interface System Trace Macrocell STM hardware event FPGA cross trigger interface FPGA trace port interface ISO 9001 2008 Registered 2013 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY M...

Page 1038: ...alon Verification IP Suite User Guide For information about the BFM API Mentor Verification IP Altera Edition User Guide For information about the BFM API Clock and Reset Interfaces Related Information Memory Mapped Interfaces on page 28 2 Clock Interface Qsys generates the clock source BFM for each clock output interface from the HPS component For HPS to FPGA user clocks specify the BFM clock rat...

Page 1039: ...n f2h_cold_reset_ req f2h_cold_reset_ req get_f2h_dbg_rst_req_n f2h_debug_reset_ req f2h_debug_ reset_req get_f2h_warm_rst_req_n f2h_warm_reset_ req f2h_warm_reset_ req set_h2f_pending_rst_req_n get_f2h_pending_rst_ack_n h2f_warm_reset_ handshake h2f_warm_reset_ handshake Table 29 3 HPS Reset Output Interface Simulation Model The Altera reset source BFM application programming interface applies to...

Page 1040: ...D Width You control and monitor the AXI slave BFM by using the BFM API Related Information Memory Mapped Interfaces on page 28 2 Mentor Verification IP Altera Edition User Guide HPS to FPGA AXI Master Interface The HPS to FPGA AXI master interface h2f_axi_master is connected to a Mentor Graphics AXI master BFM for simulation Qsys configures the BFM as shown in the following table The BFM clock inp...

Page 1041: ...based on the HPS implementation and provides cycle level accuracy reflecting the true bandwidth and latency of the interface However the model does not have the detailed configuration provided by the HPS software and hence does not reflect any inter port scheduling that might occur under contention on the real hardware when different priorities or weights are used Related Information Functional De...

Page 1042: ...tions is the same as with the general Avalon conduit BFM Post Fit Simulation API Function Names RTL Simulation API Function Names BFM Instance Name Interface Name get_ eventi set_ evento set_ standbywfe set_ standbywfi get_h2f_mpu_eventi set_h2f_mpu_evento set_h2f_mpu_standbywfe set_h2f_mpu_standbywfi h2f_mpu_events h2f_mpu_ events FPGA to HPS Interrupts Interface The FPGA to HPS interrupts interf...

Page 1043: ..._apb_PSLVERR set_h2f_dbg_apb_PWDATA set_h2f_dbg_apb_PWRITE h2f_debug_apb h2f_debug_ apb get_ PCLKEN get_DBG_ APB_ DISABLE get_h2f_dbg_apb_PCLKEN get_h2f_dbg_apb_DBG_APB_ DISABLE h2f_debug_apb_ sideband h2f_debug_ apb_sideband FPGA to HPS System Trace Macrocell STM Hardware Event Interface The FPGA to HPS STM hardware event interface is connected to an Altera conduit BFM for simulation The followin...

Page 1044: ... trace port interface is connected to an Altera conduit BFM for simulation The following table lists the name of each interface along with API function names for each type of simulation You can monitor the interface state changes or set the interface by using the API functions listed Table 29 14 HPS to FPGA Trace Port Interface Simulation Model Post Fit Simulation API Function Names RTL Simulation...

Page 1045: ... get_f2h_dma_req2_req get_f2h_dma_req2_ single set_f2h_dma_req2_ack f2h_dma_ req2 f2h_dma_req2 get_channel3_req get_channel3_ single set_channel3_xx_ ack get_f2h_dma_req3_req get_f2h_dma_req3_ single set_f2h_dma_req3_ack f2h_dma_ req3 f2h_dma_req3 get_channel4_req get_channel4_ single set_channel4_xx_ ack get_f2h_dma_req4_req get_f2h_dma_req4_ single set_f2h_dma_req4_ack f2h_dma_ req4 f2h_dma_req4...

Page 1046: ...ng Altera Designs chapter in volume 3 of the Quartus II Handbook Specifying HPS Simulation Model in Qsys The following steps outline how to set up the HPS component for simulation 1 Add the HPS component from the Qsys Component Library 2 Configure the component based on your application needs by selecting or deselecting the HPS FPGA interfaces 3 Connect the appropriate HPS interfaces to other comp...

Page 1047: ...bywfi f2h_dma_req0 1 Input req0_req 1 Input req0_single 1 Output req0_ack f2h_dma_req1 1 Input req1_req 1 Input req1_single 1 Output req1_ack f2h_dma_req2 1 Input req2_req 1 Input req2_single 1 Output req2_ack f2h_dma_req3 1 Input req3_req 1 Input req3_single 1 Output req3_ack f2h_dma_req4 1 Input req4_req Altera Corporation HPS Simulation Support Send Feedback 29 11 HPS Conduit Interfaces cv_5403...

Page 1048: ...dma_req7 1 Input req7_req 1 Input req7_single 1 Output req7_ack h2f_debug_apb 18 Input paddr 1 Input paddr_31 1 Input penable 32 Output prdata 1 Output pready 1 Input psel 1 Output pslverr 32 Input pwdata 1 Input pwrite h2f_debug_apb_sideband 1 Output pclken 1 Output dbg_apb_disable f2h_stm_hw_events HPS Simulation Support Altera Corporation Send Feedback cv_54030 HPS Conduit Interfaces 29 12 2013...

Page 1049: ...pport the VHDL simulation environment Note For post fit simulation perform the following steps Turn on the Create HDL design files for synthesis option Turn on the Create block symbol file bsf option Click Generate Related Information Instantiating the HPS Component on page 27 1 Creating a System with Qsys For more information about Qsys simulation refer to Simulating a Qsys System in the Creating...

Page 1050: ...PS post fit simulation After successful Qsys generation perform the following steps 1 Add the Qsys generated synthesis file set to your Quartus II project by performing the following steps In the Quartus II software click Settings in the Assignments menu In the Settings your Qsys system name dialog box on the Files tab browse to your project directory your Qsys system name synthesis and select you...

Page 1051: ...ctory Library verbosity_pkg sv avalon_mm_pkg sv avalon_utilities_pkg sv Avalon Verification IP lib Altera Verification IP Library altera_avalon_clock_source sv AvalonVerificationIP altera_avalon_clock_source Avalon Clock Source BFM altera_avalon_reset_source sv Avalon Verifica tion IP altera_avalon_reset_source Avalon Reset Source BFM altera_avalon_mm_slave_bfm sv AvalonVerificationIP altera_avalo...

Page 1052: ...is the instance name of the design under test that you instantiated in your test bench that consists of the HPS component HPS is the HPS component instance name that you use in your Qsys system interface is the instance name for a specific FPGA to HPS or HPS to FPGA interface This name can be found in the fpga_interfaces sv file located in project directory Qsys design name synthesis submodules sp...

Page 1053: ...ory Table 29 19 Document Revision History Changes Version Date Maintenance release 2013 12 30 December 2013 Added debug APB STM hardware event FPGA cross trigger FPGA trace port interfaces Added support for post fit simulation Updated some API function names Removed DMA peripheral clock 1 1 November 2012 Initial release 1 0 June 2012 Preliminary draft 0 1 May 2012 Altera Corporation HPS Simulation...

Page 1054: ... FPGA configuration ends when the configuration image has been fully loaded and the FPGA enters user mode The FPGA configuration image is provided by users and is typically stored in non volatile flash based memory The FPGA CB can obtain a configuration image from the HPS through the FPGA manager or from any of the sources supported by the Cyclone V FPGAs family The following three figures illustr...

Page 1055: ...r by accessing an external interface depending on your design and implementation Figure A 2 FPGA Configures First FPGA Portion HPS Portion Boot ROM HPS to FPGA Bridge PCIe Passive Serial Passive Parallel Boot Configuration Sources Active Serial Active Serial x4 FPGA Fabric MPU Altera SoC Device The following figure shows that the HPS boots first through one of its non FPGA fabric boot sources and ...

Page 1056: ...aware of the preloader and not aware of any potential subsequent software stages The figure below illustrates the typical boot flow However there may be more or less software stages in the user software than shown and the roles of the software stages may vary Figure A 4 Typical Boot Flow Reset Boot ROM Preloader Boot Loader Operating System Application User Software Boot Process Overview Reset The...

Page 1057: ... memory with external transceiver 0x4 3 3 V SD MMC flash memory with internal transceiver 0x5 1 8 V SPI or quad SPI flash memory 0x6 3 3 V SPI or quad SPI flash memory 0x7 Note If the BOOTSEL value is set 0x1 to Boot from FPGA then the CLKSEL values are ignored PLLs are bypassed so that OSC1 drives all the clocks For indirect execution from flash memory boot sources the boot ROM code loads the pre...

Page 1058: ...LKSEL value Configures I O elements and pin multiplexing based on the BOOTSEL value Initializes the flash controller to default settings When booting from flash memory the boot ROM code uses the top 4 KB of the on chip RAM as data workspace This area is reserved for the boot ROM code after a reset until the boot ROM code passes software control to preloader This limits the maximum size of the prel...

Page 1059: ...t ROM code attempts to load the first preloader image from flash memory to on chip RAM and pass control to the preloader If the image is invalid the boot ROM code attempts to load up to three subsequent images from flash memory If there is still no valid image found after the subsequent loads the boot ROM code checks the FPGA portion of the device for a fallback image Warm boot from on chip RAM ha...

Page 1060: ...s a workspace for the boot ROM data and stack The preloader can use this 4 KB region for its stack and data for example after the boot ROM code passes control to the preloader This 4 KB region is overwritten by the boot ROM code on a subsequent reset The following figure shows the preloader image layout in the on chip RAM after being loaded from the boot ROM Figure A 6 Preloader Image Layout Spare...

Page 1061: ...Shared Memory The shared memory contains information that the boot ROM code passes to the preloader The boot ROM code passes the location of shared memory to the preloader in register r0 as described in HPS State on Entry to the Preloader on page 30 11 The shared memory contains the following information Common contains non flash specific settings used by the boot ROM code Saved hardware register ...

Page 1062: ...CLKSEL value used Indicates the BOOTSEL value used by the boot ROM code Typically this value is the value read from the bootsel field of the bootinfo register in the romcodegrp group in the system manager BOOTSEL value used Indicates the number of the last page read from the flash device Last page Indicates the page size in bytes used by the flash device For NAND flash memory the boot ROM code rea...

Page 1063: ...sed to control the boot ROM code Control ctrl register in the romcodegrp group in the system manager Contains the magic value 0x49535756 when the preloader has reached a valid state initswstate register in the romcodegrp group in the system manager Indicates the card type 1 indicates SD card 0 indicates MMC is_sd_card Flash device specific SD MMC Indicates the addressing mode of card 1 indicates s...

Page 1064: ...ion cache is enabled Branch predictor is enabled Data cache is disabled MMU is disabled Floating point unit is enabled NEON vector unit is enabled Processor is in ARM secure supervisor mode The boot ROM code sets the ARM Cortex A9 MPCore registers to the following values r0 contains the pointer to the shared memory block which is used to pass information from the boot ROM code to the preloader The...

Page 1065: ...iplexing through the system manager Configure HPS clocks through the clock manager Initialize the flash controller NAND SD MMC or quad SPI that contains the next stage boot software Load the next stage boot software into the SDRAM and pass control to it Typical Preloader Boot Flow This section describes a typical software flow from the preloader entry point until the software passes control to the...

Page 1066: ...steps include reconfiguring or disabling the L4 watchdog 0 timer invalidating the instruction cache and branch predictor remapping the on chip RAM to the lowest memory region and setting up the data area Upon entering the preloader the L4 watchdog 0 timer is active The preloader can either disable reconfigure or leave the watchdog timer unchanged Once enabled after reset the watchdog timer cannot ...

Page 1067: ...ice or memory device For partial initialization SDRAM PLL configuration and SDRAM calibration is not necessary The preloader looks for a valid next stage boot image in the next stage boot device by checking the boot image validation data and checksum in the mirror image Once validated the preloader copies the next stage boot image from the next stage boot device to the SDRAM Before software passes...

Page 1068: ...r more information about the NAND flash memory refer to the NAND Flash Controller chapter in the Cyclone V Device Handbook Volume 3 NAND Flash Driver Features Supported in the Boot ROM Code Table A 3 NAND Flash Support Features Driver Support Feature Open NAND Flash Interface ONFI 1 0 raw NAND or electronic signature devices single layer cell SLC Device CS0 only Only CS0 is available to the HPS th...

Page 1069: ...ss of each image is based on the following formula Start address partition start address n 64 K where n is the image number Figure A 10 SD MMC Flash Image Layout Preloader Image 3 Preloader Image 2 Preloader Image 1 Preloader Image 0 Partition Type A2 Partition Size 64 KB x 4 Master Boot Record MBR 0x0 MBR Partition Size 512 Bytes The SD MMC controller supports two booting modes MBR partition mode...

Page 1070: ...s standard table cannot have more than four primary partitions or up to three primary partitions and one extended partition Each partition type is defined by the partition entry The boot images are stored in a primary partition with custom partition type 0xA2 The SD MMC flash driver does not support a file system so the boot images are located in partition A2 at fixed locations Table A 6 Partition...

Page 1071: ... field rx_wmark of the FIFO threshold watermark register fifoth 0x1 1 FIFO threshold RX watermark level The clock source register clksrc 0x0 0 Clock source The block size register blksiz 0x200 512 Block size The clock divider register clkdiv 0x10 2 16 32 32 Identification mode Clock divider The clock divider register clkdiv 0x00 Bypass Data transfer mode CLKSEL Pin Settings for the SD MMC Controll...

Page 1072: ... and Quad SPI Flash Devices The figure below shows the SPI and quad SPI flash image layout The preloader image is always located at offsets which are multiples of 64 KB The boot ROM code only supports QSPI devices with Mode Reset Command Common manufacturers for Mode Reset Command are Spansion and Winbond The first image is located at offset 0 and followed by subsequent images The start address of...

Page 1073: ...ay in master reference clocks for the length that the master mode chip select outputs are deasserted between words when the clock phase is zero The clock delay for chip select deactivation field btwn in the delay register 0x0 0 ns Delay in master reference clocks between one chip select being deactivated and the activation of another This delay ensures a quiet period between the selection of two d...

Page 1074: ...00 MHz max osc1_clk 2 100 MHz max osc1_clk 50 MHz max Controller clock qspi_clk 4 4 4 4 Controller baud rate divisor even numbers only READ_FAST READ_FAST READ READ Flash read instruc tion 1 dummy byte for READ_ FAST osc1_clk 16 400 MHz max osc1_clk 8 400 MHz max osc1_clk 8 400 MHz max osc1_clk 50 MHz max mpu_clk Locked Locked Locked Bypassed PLL modes SPI and Quad SPI Flash Delay Configuration Th...

Page 1075: ...iguring the FPGA in general refer to the Configuration Design Security and Remote System Upgrade appendix in the Cyclone V Device Handbook Volume 1 http www altera com literature hb cyclone v cv_54013 pdf For more information about configuring the FPGA through the HPS FPGA manager refer to the FPGA Manager chapter in the Cyclone V Device Handbook Volume 3 Full Configuration The HPS uses the FPGA m...

Page 1076: ...o_porta_eoi 9 Set the axicfgen bit of the ctrl register to 1 to enable sending configuration data to the FPGA 10 Write the configuration image to the configuration data register data in the FPGA manager module configuration data registers fpgamgrdata You can also choose to use a DMA controller to transfer the configuration image from a peripheral device to the FPGA manager 11 Use the fpgamgrregs m...

Page 1077: ... 12 30 December 2013 Expanded shared memory block table Added CLKSEL tables Additional minor updates 1 3 November 2012 Updated the HPS boot and FPGA configuration sections 1 2 June 2012 Updated the HPS boot section Added information about the flash devices used for HPS boot Added information about the FPGA configuration mode 1 1 May 2012 Initial release 1 0 January 2012 Booting and Configuration I...

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