Freescale Semiconductor MSC8144E, Справочное руководство

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DDR Controller (DDRC)
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor 1-19
1.8 DDR Controller (DDRC)
The DDR SDRAM interface is useful when the channel storage size is relatively big (as for a
modem) and also when more channels are required to supplement the internal memory. When the
MSC8144E device works with channel data stored in the DDR SDRAM, the DMA controller can
swap the data to and from the M2 memory, thus enabling the L1 DCache to fetch from M2
memory instead of accessing the DDR SDRAM memory directly. Fetch latency is thus reduced,
significantly improving the average clock cycles required per task. The M2 and M3 memories are
large enough to accommodate the number of channels processed by the DSP subsystems for a
variety of packet telephony and wireless transcoding application, such as basic G.711 voice
coding, G.729 or G.723 premium voice coding, AMR, and EFR. However, it is not large enough
for such memory-consuming applications as a V.90 modem, especially when high channel
densities are required. For these applications, the MSC8144E can interface with
JEDEC-compliant DDR1 or DDR2 SDRAM devices. A DDR SDRAM can be used not only as
an extension for the M2 and M3 memories but also to store code. In a typical application,
infrequently used code is either swapped into M2/M3 memory when needed or executed directly
from an external DDR SDRAM. The DDR SDRAM interface frequency is decoupled from the
DSP subsystem frequency, and it has a separate PLL to deliver the required frequency according
to the bandwidth requirements. It is 16/32 bits wide and can interface with up to two 16-bit wide
devices, or four 8-bit wide devices. It has a separate strobe per byte. Two logical banks (chip
select) are supported, each with logical programmable bank start and end addresses. A bank size
of up to 128 MB is supported. Programmable parameters allow for a variety of SDRAM
organizations and timings. Using data mask bits, the SDRAM controller enables partial write
operations to bytes in a word or words in a burst. Optional ECC protection is provided for the
DDR SDRAM data bus. Using ECC, the memory controller detects all two-bit errors and corrects
all single-bit errors within the 32-bit data bus. For ECC, an additional ECC DDR SDRAM device
is usually needed. Both the data DDR SDRAM and the ECC DDR SDRAM should have the
same CAS latency. There is page retention for up to four simultaneous open pages, and the
number of clocks for which the pages are kept open is programmable. Pages are replaced using a
pseudo-LRU replacement algorithm.