MSC8144E Reference Manual, Rev. 3
14-2
Freescale
Semiconductor
Direct Memory Access (DMA) Controller
14.1
Operating Modes
The DMA controller supports to modes of operation:
Functional mode. Each of the data transactions can be executed on each of the MBus
ports. The VCOP supports memory to memory data transfers.
Debug mode. The VCOP enters the debug by external debug request. Once the VCOP
enters the debug mode, it holds its requests to the MBus ports. The internal logic in the
VCOP masks the channels.
— MBus is in debug mode and each of its ports gracefully stops its transaction.
— Channel logic in debug mode. The arbitration mechanism masks all channels requests.
The last serviced channel gets is fully serviced.
14.2
Buffer Types
The DMA channel parameter RAM (PRAM) is accessible to the DMA controller and the port
interface and includes a parity mechanism. Each channel has one dedicated PRAM line. The
external BD is fetched into the PRAM the first time the channel wins during arbitration.
When a buffer is activated, the DMA controller generates a bus transaction with a maximum size
as described in the buffer descriptor BTSZ field and decrements BD_SIZE accordingly. The
address can increment or freeze. When BD_SIZE reaches zero, the channel takes one of the
following actions:
Shuts down (simple buffer)
Reinitializes itself (cyclic buffer)
Reinstalls its size (incremental buffer)
Switches to another buffer (chained-buffers)
Any combination of the preceding
Updates the multi-dimension parameters (multi dimension-buffers)
The sections that follow provide examples of several types of buffers. The BD_ATTR fields
listed for each example are only those that do not have zero values.
Содержание MSC8144E
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