Programming Model
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor
24-17
24.5.3 I
2
C Control Register (I2CCR)
Table 24-3 describes the I2CCR fields.
I2CCR
I
2
C Control Register
Offset 0x08
Bit
7
6
5
4
3
2
1
0
MEN
MIEN
MSTA
MTX
TXAK
RSTA
—
BCST
Type
R/W
R/W
W
R/W
R/W
W
R/W
R/W
Reset
0
0
0
0
0
0
0
0
Table 24-3. I2CCR Bit Descriptions
Name
Reset
Description
Settings
MEN
7
0
Module Enable
This bit controls the software reset of the I
2
C module. When
cleared, the interface is held in reset but the registers can still
be accessed. This bit must be set before any other control
register bits have any effect. All I
2
C registers for target
receive or initiator START can be initialized before setting
this bit.
0
The module is reset and
disabled.
1
The I
2
C module is enabled.
MIEN
6
0
Module Interrupt Enable
Enables/disables interrupts from the I
2
C module. Clearing
the bit does not clear any pending interrupts. When set, the
interrupt occurs only if I2CSR[MIF] is also set.
0
Interrupts are disabled.
1
Interrupts are enabled.
MSTA
5
0
Initiator/Target Mode START
Issues a STOP and changes to Target mode or a START
and changes to Initiator mode. It the initiator loses arbitration,
the bit is cleared without generating a STOP condition on the
bus.
0
Issues a STOP condition and
changes mode from initiator
to target.
1
Issues a START condition
and initiator mode is selected.
MTX
4
0
Transmit/Receive Mode Select
This bit selects the direction of the initiator and target
transfers. When configured as a target, this bit should be set
by software according to I2CSR[SRW]. In initiator mode, the
bit should be set according to the type of transfer required.
Therefore, for address cycles, this bit will always be high.
The MTX bit is cleared when the initiator loses arbitration.
0
Receive mode.
1
Transmit mode.
TXAK
3
0
Transfer Acknowledge
This bit specifies the value driven onto the SDA line during
acknowledge cycles for both initiator and target receivers.
The value of this bit only applies when the I
2
C module is
configured as a receiver, not a transmitter. It also does not
apply to address cycles; when the core is addressed as a
target, an acknowledge is always sent.
0
An acknowledge signal (SDA
low) is sent to the bus on the
9th clock after receiving one
byte of data.
1
No acknowledge signal
response is sent (SDA high).
RSTA
2
0
Repeat START
Setting this bit always generates a repeated START
condition on the bus and provides the core with the current
bus initiator. Attempting a repeated START at the wrong time
(or if the bus is owned by another initiator), results in loss of
arbitration.
0
No START condition
generated.
1
Generates repeat START
condition.
Содержание MSC8144E
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Страница 242: ...MSC8144E Reference Manual Rev 3 5 26 Freescale Semiconductor Reset ...
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