Freescale Semiconductor MSC8144E, Справочное руководство

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MSC8144E Reference Manual, Rev. 3
12-36 Freescale Semiconductor
DDR SDRAM Memory Controller
WRT
29–28
0 Write-to-Read Turn-Around
Specifies how many extra cycles to add between a write-to-read
turn-around. For 0 clock cycles, the DDR controller uses a fixed
number based on the read latency and write latency. A value
other than 0 adds extra cycles to this default calculation. By
default, the DDR controller determines the write-to-read
turn-around as WL – CL + BL/2 + 1. CL is the
CAS
latency
rounded down to the next integer, WL is the programmed write
latency, and BL is the burst length. (BL = 4 for all accesses)
00 0 clock cycles.
01 1 clock cycle.
10 2 clock cycles.
11 3 clock cycles.
RRT
27–26
0 Read-to-Read Turn-Around
Specifies how many extra cycles to add between reads to
different chip selects. By default, 3 cycles are required between
read commands to different chip selects.
If 00 is selected the DDR Controller will use a predefined value -
3 clocks for the turnaround, selecting a value other than 00 adds
extra cycles to this predefined value according to the selection 00 0 clock cycles.
01 1 clock cycle.
10 2 clock cycles.
11 3 clock cycles.
WWT
25–24
0 Write-to-Write Turn-Around
Specifies how many extra cycles to add between writes to
different chip selects. By default, 2 cycles are required between
write commands to different chip selects.
If 00 is selected the DDR Controller will use a predefined value -
2 clocks for the turnaround, selecting a value other than 00 adds
extra cycles to this predefined value according to the selection 00 0 clock cycles.
01 1 clock cycle.
10 2 clock cycles.
11 3 clock cycles.
—
23
0 Reserved. Write to zero for future compatibility.
ACT_PD_
EXIT
22–20
0b001 Active Power-Down Exit Timing (t
XARD
and t
XARDS
)
Specifies how many clock cycles to wait between exit from
active power-down and issuing a command. The default is one
clock cycle.
000 Reserved
001 1 clock cycle.
010 2 clock cycles.
011 3 clock cycles.
100 4 clock cycles.
101 5 clock cycles.
110 6 clock cycles.
111 7 clock cycles.
—
19
0 Reserved. Write to zero for future compatibility.
PRE_PD_
EXIT
18–16
0b001 Precharge Power-Down Exit Timing (t
xp
)
Specifies how many clock cycles to wait after exiting precharge
power-down before issuing any command.
The default is one clock cycle.
000 Reserved.
001 1 clock.
010 2 clock cycles.
011 3 clock cycles.
100 4 clock cycles.
101 5 clock cycles.
110 6 clock cycles.
111 7 clock cycles.
—
15–12
0 Reserved. Write to zero for future compatibility.
Table 12-19. TIMING_CFG_0 Field Descriptions (Continued)
Bit Reset Description Settings