MSC8144E Reference Manual, Rev. 3
4-8
Freescale
Semiconductor
Chip-Level Arbitration and Switching System (CLASS)
The associated AEIx bit in the CISR is set.
The address which was identified as illegal is stored in the associated CEARx and
CEEARx. These registers are locked until the associated AEIx bit in the CISR is cleared
either by a hardware reset or by writing 1 to this bit.
Note:
If the associated AEIx bit in the CISR is already set when the illegal address is
identified (due to a prior illegal address), then the new error address is not stored.
If the corresponding AEIEx bit in the CIER is set, an IRQ will be issued.
The CLASS does not initiate a transaction to any target. However, the CLASS will
continue normally on the initiator side until completion, and report the error. In case of a
read transaction, the CLASS delivers invalid data to the initiator.
If, at the time of the error transaction, there are open transactions that did not receive the
end-of-transaction, the expander module stalls all new transaction until all prior
transactions receive the end-of-transaction, close the error transaction, report the
end-of-transaction, report the error, and only then continue with subsequent transactions.
Any subsequent requests with a legal address are serviced normally.
Note:
The CLASS does not produce an error when a transaction starts inside a target address
window and finishes outside of the window. This situation must be avoided by the user.
If it occurs, the results are unpredictable.
The error interrupt is logically ORed with internal error interrupts. The internal error interrupts
are associated with each initiator. Thus, the CLASS error interrupt is asserted when at least one
internal interrupt is asserted.
Содержание MSC8144E
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Страница 86: ...MSC8144E Reference Manual Rev 3 1 38 Freescale Semiconductor Overview ...
Страница 167: ...OCE Event and JTAG Test Access Port Signals MSC8144E Reference Manual Rev 3 Freescale Semiconductor 3 59 ...
Страница 168: ...MSC8144E Reference Manual Rev 3 3 60 Freescale Semiconductor External Signals ...
Страница 242: ...MSC8144E Reference Manual Rev 3 5 26 Freescale Semiconductor Reset ...
Страница 314: ...MSC8144E Reference Manual Rev 3 8 24 Freescale Semiconductor General Configuration Registers ...
Страница 414: ...MSC8144E Reference Manual Rev 3 10 14 Freescale Semiconductor MSC8144E SC3400 DSP Subsystem ...
Страница 452: ...MSC8144E Reference Manual Rev 3 11 38 Freescale Semiconductor Internal Memory Subsystem ...
Страница 520: ...MSC8144E Reference Manual Rev 3 12 68 Freescale Semiconductor DDR SDRAM Memory Controller ...
Страница 884: ...MSC8144E Reference Manual Rev 3 17 44 Freescale Semiconductor RapidIO Interface Dedicated DMA Controller ...
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