DDR SDRAM Clocking and Interface Timing
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor
12-21
12.3.4.3 DDR Memory Controller Clock Stop Mode
To reduce the power dissipation, it is possible to shut down the clock to the DDR memory
controller. To shut down the memory controller the DDR_PWR[STOP] bit should be asserted.
Once this occurs, the DDR memory controller will end all the pending transactions to the
memory, new transactions will not be accepted, and will enter the clock stop mode. During the
clock stop period the DDR memory controller will not initiate refresh commands toward the
memory. To exit the stop mode, perform a chip reset.
Note:
Any transaction performed to the DDR memory controller by one of the cores or any
other peripheral that can access the DDR memory while in stop mode will not be
executed by the controller and the MSC8144E might get stuck. To prevent this stuck
condition it is possible to disable the DDR window within the CLASS by deasserting
REGISTER[bit] prior to requesting the stop mode.
12.3.5
DDR Data Beat Ordering
Transfers to and from memory are always performed in four-beat bursts (four beats = 16 or 8
bytes for 32 bits or 16 bits interface, accordingly)‘. For transfer sizes other than four beats, the
data transfers are still in four-beat bursts. If ECC is enabled and either the access is not
word-aligned or the size is not a multiple of a word, a full read-modify-write is performed for a
write to SDRAM. If ECC is disabled or the access is word-aligned with a size that is a multiple of
a word, the data masks MDM[0–5] can be used to prevent the writing of unwanted data to
SDRAM. The DDR memory controller also uses data masks to prevent all unintended full words
from writing to SDRAM. For example, if a write transaction with a size of one word (4 bytes) is
desired, then the second, third, and fourth beats of data are not written to SDRAM.
Table 12-9 lists the data beat sequencing to and from the DDR SDRAM and the data queues for
each of the possible transfer sizes with each of the possible starting double-word offsets. All
underlined double-word offsets are valid for the transaction.
Table 12-9. Memory Controller–Data Beat Ordering - for 32 bit interface
Transfer Size
Starting Word Offset
Word Sequence
1
to/from DRAM and Queues
1. All underlined word offsets are valid for the transaction.
1 word
0
1
2
3
0 - 1 - 2 - 3
1 - 2 - 3 - 0
2 - 3 - 0 - 1
3 - 0 - 1 - 2
2 words
0
1
2
0 - 1 - 2 - 3
1 - 2 - 3 - 0
2 - 3 - 0 - 1
3 words
0
1
0 - 1 - 2 - 3
1 - 2 - 3 - 0
4 words
0
0 - 1 - 2 - 3
4 words
1
2
3
1 - 2 - 3 - 0 - 0 - 1 - 2 - 3
2 - 3 - 0 - 1 - 0 - 1 - 2 - 3
3 - 0 - 1 - 2 - 0 - 1 - 2 - 3
Содержание MSC8144E
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