Freescale Semiconductor MSC8144E, Справочное руководство

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Memory Controller Programming Model
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor 12-41
CPO
27–23
0
MCAS
-to-Preamble Override
Defines the number of DRAM cycles between a read command
and the time the corresponding DQS preamble is valid for the
memory controller. For these decodings, read latency (RL) is
equal to the
CAS
latency plus the additive latency. For CPO
decodings other than 00000 and 11111, read latency is rounded
up to the next integer value.
00000 RL + 1
00001 Reserved
00010 RL
00011 RL + 1/4
00100 RL + 1/2
00101 RL + 3/4
00110 RL + 1
00111 RL + 5/4
01000 RL + 3/2
01001 RL + 7/4
01010 RL + 2
01011 RL + 9/4
01100 RL + 5/2
01101 RL + 11/4
01110 RL + 3
01111 RL + 13/4
10000 RL + 7/2
10001 RL + 15/4
10010 RL + 4
10011 RL + 17/4
10100 RL + 9/2
10101 RL + 19/4
10110–11110 Reserved
11111 Automatic
Calibration
(recommended)
—
22
0 Reserved. Write to zero for future compatibility.
WR_LAT
21–19
0 Write Latency
Note that the total write latency for DDR2 is equal to
ADD_LAT.
The Write Latency for DDR1 is 1.
This field must be programmed for proper operation of the DDR
Controller. 000 Reserved.
001 1 clock cycle.
010 2 clock cycles.
011 3 clock cycles.
...
111 7 clock cycles.
—
18–16
0 Reserved. Write to zero for future compatibility.
RD_TO_PRE
15–13
0 Read to Precharge ( t
RTP
)
For DDR2, with a non-zero ADD_LAT value, takes a minimum
of A t
RTP
cycles between read and precharge.
For DDR1 must be set to 010.
This field must be programmed for proper operation of the DDR
Controller.
000 Reserved.
001 1 clock cycle.
010 2 clock cycles.
011 3 clock cycles.
100 4 clock cycles.
101–111 Reserved
Table 12-21. TIMING_CFG_2 Bit Descriptions (Continued)
Bit Reset Description Settings