MSC8144E Reference Manual, Rev. 3
24-12
Freescale
Semiconductor
I
2
C
Enable the I
2
C by setting I2CCR to 0xA0.
Wait for a period that is equivalent to at least one SCL cycle. SCL does not toggle until the
dummy read executes.
Read the I2CDR.
Return the I
2
C module to target mode by setting I2CCR to 0x80.
Wait for a period that is equivalent to at least 9 SCL cycles and verify that the bus is
released.
24.4.7 Target Mode Interrupt Service Routine
In the target interrupt service routine, the module addressed as a target should be tested to check
if a calling of its own address has been received. If I2CSR[MAAS] = 1, software should set the
transmit/receive mode select bit (I2CCR[MTX]) according to the R/W command bit
(I2CSR[SRW]). Writing to I2CCR clears I2CSR[MAAS] automatically. The only time
I2CSR[MAAS] is read as set is from the interrupt handler at the end of that address cycle where
an address match occurred; interrupts resulting from subsequent data transfers will have
I2CSR[MAAS] = 0. A data transfer can then be initiated by writing to I2CDR for target transmits
or dummy reading from I2CDR in target-receive mode. The target drives SCL low between byte
transfers. SCL is released when the I2CDR is accessed in the required mode.
24.4.8 Target Transmitter and Received Acknowledge
In the target transmitter routine, the received acknowledge bit (I2CSR[RXAK]) must be tested
before sending the next byte of data. The initiator signals an end-of-data by not acknowledging
the data transfer from the target. When no acknowledge is received (I2CSR[RXAK] = 1), the
target transmitter interrupt routine must clear I2CCR[MTX] to switch the target from transmitter
to receiver mode. A dummy read of I2CDR then releases SCL so that the initiator can generate a
STOP condition. See Section 24.4.10, “Interrupt Service Routine Flowchart.”
24.4.9 Loss of Arbitration and Forcing of Target Mode
When an initiator loses arbitration the following conditions all occur—
I2CSR[MAL] is set
I2CCR[MSTA] is cleared (changing the initiator to target mode)
An interrupt occurs (if enabled) at the falling edge of the 9th clock of this transfer.
Thus, the target interrupt service routine should test I2CSR[MAL] first, and the software should
clear I2CSR[MAL] if it is set. See Section 24.2.5, for details.
Содержание MSC8144E
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Страница 86: ...MSC8144E Reference Manual Rev 3 1 38 Freescale Semiconductor Overview ...
Страница 167: ...OCE Event and JTAG Test Access Port Signals MSC8144E Reference Manual Rev 3 Freescale Semiconductor 3 59 ...
Страница 168: ...MSC8144E Reference Manual Rev 3 3 60 Freescale Semiconductor External Signals ...
Страница 242: ...MSC8144E Reference Manual Rev 3 5 26 Freescale Semiconductor Reset ...
Страница 314: ...MSC8144E Reference Manual Rev 3 8 24 Freescale Semiconductor General Configuration Registers ...
Страница 414: ...MSC8144E Reference Manual Rev 3 10 14 Freescale Semiconductor MSC8144E SC3400 DSP Subsystem ...
Страница 452: ...MSC8144E Reference Manual Rev 3 11 38 Freescale Semiconductor Internal Memory Subsystem ...
Страница 520: ...MSC8144E Reference Manual Rev 3 12 68 Freescale Semiconductor DDR SDRAM Memory Controller ...
Страница 884: ...MSC8144E Reference Manual Rev 3 17 44 Freescale Semiconductor RapidIO Interface Dedicated DMA Controller ...
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