Asynchronous Transfer Mode (ATM) Controller
MSC8144E Reference Manual, Rev. 3
Freescale Semiconductor
18-35
After initializing the registers, you must complete the following steps to bring the Ethernet
Controller into a functional state:
1.
To transmit Ethernet frames, build the TxBDs in memory, link them together as a ring,
and point to the ring. A minimum of two TxBDs per ring is required.
2.
To receive Ethernet frames, link the RxBDs together as a ring and point the
corresponding registers to them. Both transmit and receive can be gracefully stopped
after transmission and reception begins.
18.8
Asynchronous Transfer Mode (ATM) Controller
The MSC8144E uses UCC5 to support one ATM controller managed through the QUICC Engine
subsystem. UCC5 manages the data flow internally through its receive and transmit FIFOs. The
QUICC Engine subsystem performs frame control and manipulation using firmware executed by
the RISC engines according to the specified protocol requirements. External data flow is
managed using a separate, associated UTOPIA/POS bus controller (UPC) to a UTOPIA or POS
interface. The UPC can operate in master and slave modes.
The QUICC Engine subsystem supports the following ATM applications:
ATM line card controllers
ATM-to-WAN interworking (frame relay, T1/E1 circuit emulation)
Residential broadband network interface units (NIU) (ATM-to-Ethernet)
High-performance ATM network interface cards (NIC)
Bridges and routers with ATM interface
18.8.1
Background
Asynchronous transfer mode (ATM) was developed as an international standard to support
consistent, reliable, and uninterrupted data transmission world-wide. Data transmission is
performed asynchronously because the distance over which the transfer occurs prevents the use
of the same clock signal at both ends and even at points within the transfer network. Each
network consists of user end stations that transmit and receive the specified unit of transfer,
called a cell, using virtual connections. The original protocol used 8-bit data transfers and the cell
size was 53 bytes, which included 48 bytes of data and a 5 byte header. As technology has
Initialize the InitEnet parameter
CECDR
Initialize the Tx and Rx parameters of UCC1 ethernet.
CECR
Enable the Ethernet Controller MAC TX and RX
MACCFG1
Note:
See the QUICC Engine™ Block Reference Manual with Protocol Interworking (QEIWRM) for register addressing,
structure, and programming details.
Table 18-12.
Minimum Register Initialization
(Continued)
Initialization Step
Registers
Содержание MSC8144E
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