MSC8144E Reference Manual, Rev. 3
1-6
Freescale
Semiconductor
Overview
QUICC Engine
Subsystem
The QUICC Engine subsystem handles the Ethernet and ATM interfaces, thus offloading the cores
from handling those tasks. It includes the following:
•
Dual-RISC engine, with one instruction per clock, code execution from internal ROM or multi-port
RAM, 32-bit RISC architecture, up to sixteen internal software timers maintained in the multi-port
RAM, interface with the core processors through a 48-KB dual-port RAM and virtual DMA
channels for each interface controller, and ability to handle serial protocols and virtual DMA
•
Multi-initiator 48-KB multi-port RAM
•
48-KB instruction RAM (IRAM)
•
Serial DMA channel
•
Two full-duplex programmable communications controllers supporting two gigabit Ethernet
controllers (10/100/1000 Mbps operation)
•
One full-duplex programmable communications controller with a ATM controller for a 50 MHz,
16-bit UTOPIA interface supporting AAL0, AAL2, and AAL5 operation
•
Interrupt controller
•
Multiplexer and timers logic
•
Baud-rate generators
Two Ethernet
Controllers
10/100/1000
•
Five Ethernet physical interfaces:
– 10/100 Mbps MII (one controller only).
– 10/100 Mbps RMII (consortium standard).
– 10/100 Mbps SMII.
– Designed to comply with the SGMII protocol using a 4-pin SerDes interface at 1000 Mbps data
rate only.
– 10/100/1000 Mbps RGMII (full duplex only).
•
MAC-to-MAC connection in all modes.
•
Half- and full-duplex operations in 10/100 Mbps mode.
•
Half-duplex back-pressure (10/100 Mbps only).
•
Full-duplex operations in 1000 Mbps mode.
•
Full-duplex flow control feature (IEEE Std. 802.3x).
•
Receive flow control frames.
•
Detection of all erroneous frames as defined by IEEE® Std. 802.3-2002™.
•
Multi-buffer data structure.
•
Diagnostic modes: Internal and external loopback mode and echo mode.
•
Serial management interface MDC/MDIO.
•
Transmitter network management and diagnostics.
•
Receiver network management and diagnostics.
•
VLAN Support.
•
IEEE Std. 802.1p/Q™ QoS.
•
Eight Tx/Rx queues.
•
Queuing decision for IP/MAC/UDP filtering based on MAC destination addresses, IP destination
address, and UDP destination port.
•
Programmable maximum frame length.
•
Enhanced MIB statistics.
•
Optional shift of data buffer by two bytes for L3 header alignments.
•
Extended features.
– IP header checksum verification and calculation.
– Parsing of frame headers and adding a frame control block at the frame head, containing L3
and L4 information for CPU acceleration.
Table 1-1. MSC8144E Features (Continued)
Feature
Description
Содержание MSC8144E
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