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23
SPRUH82C – April 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Contents
34.3.4
User Case 4: Example of How to Program the USB DMA Controller
..................................
34.4
Registers
.................................................................................................................
34.4.1
Revision Identification Register (REVID)
...................................................................
34.4.2
Control Register (CTRLR)
....................................................................................
34.4.3
Status Register (STATR)
.....................................................................................
34.4.4
Emulation Register (EMUR)
.................................................................................
34.4.5
Mode Register (MODE)
......................................................................................
34.4.6
Auto Request Register (AUTOREQ)
.......................................................................
34.4.7
SRP Fix Time Register (SRPFIXTIME)
....................................................................
34.4.8
Teardown Register (TEARDOWN)
..........................................................................
34.4.9
USB Interrupt Source Register (INTSRCR)
...............................................................
34.4.10
USB Interrupt Source Set Register (INTSETR)
..........................................................
34.4.11
USB Interrupt Source Clear Register (INTCLRR)
.......................................................
34.4.12
USB Interrupt Mask Register (INTMSKR)
................................................................
34.4.13
USB Interrupt Mask Set Register (INTMSKSETR)
......................................................
34.4.14
USB Interrupt Mask Clear Register (INTMSKCLRR)
...................................................
34.4.15
USB Interrupt Source Masked Register (INTMASKEDR)
..............................................
34.4.16
USB End of Interrupt Register (EOIR)
....................................................................
34.4.17
Generic RNDIS EP1 Size Register (GENRNDISSZ1)
.................................................
34.4.18
Generic RNDIS EP2 Size Register (GENRNDISSZ2)
.................................................
34.4.19
Generic RNDIS EP3 Size Register (GENRNDISSZ3)
.................................................
34.4.20
Generic RNDIS EP4 Size Register (GENRNDISSZ4)
.................................................
34.4.21
Function Address Register (FADDR)
.....................................................................
34.4.22
Power Management Register (POWER)
.................................................................
34.4.23
Interrupt Register for Endpoint 0 Plus Transmit Endpoints 1 to 4 (INTRTX)
........................
34.4.24
Interrupt Register for Receive Endpoints 1 to 4 (INTRRX)
.............................................
34.4.25
Interrupt Enable Register for INTRTX (INTRTXE)
......................................................
34.4.26
Interrupt Enable Register for INTRRX (INTRRXE)
......................................................
34.4.27
Interrupt Register for Common USB Interrupts (INTRUSB)
............................................
34.4.28
Interrupt Enable Register for INTRUSB (INTRUSBE)
..................................................
34.4.29
Frame Number Register (FRAME)
........................................................................
34.4.30
Index Register for Selecting the Endpoint Status and Control Registers (INDEX)
..................
34.4.31
Register to Enable the USB 2.0 Test Modes (TESTMODE)
...........................................
34.4.32
Maximum Packet Size for Peripheral/Host Transmit Endpoint (TXMAXP)
...........................
34.4.33
Control Status Register for Endpoint 0 in Peripheral Mode (PERI_CSR0)
..........................
34.4.34
Control Status Register for Endpoint 0 in Host Mode (HOST_CSR0)
...............................
34.4.35
Control Status Register for Peripheral Transmit Endpoint (PERI_TXCSR)
..........................
34.4.36
Control Status Register for Host Transmit Endpoint (HOST_TXCSR)
...............................
34.4.37
Maximum Packet Size for Peripheral Host Receive Endpoint (RXMAXP)
...........................
34.4.38
Control Status Register for Peripheral Receive Endpoint (PERI_RXCSR)
..........................
34.4.39
Control Status Register for Host Receive Endpoint (HOST_RXCSR)
...............................
34.4.40
Count 0 Register (COUNT0)
...............................................................................
34.4.41
Receive Count Register (RXCOUNT)
.....................................................................
34.4.42
Type Register (Host mode only) (HOST_TYPE0)
......................................................
34.4.43
Transmit Type Register (Host mode only) (HOST_TXTYPE)
.........................................
34.4.44
NAKLimit0 Register (Host mode only) (HOST_NAKLIMIT0)
..........................................
34.4.45
Transmit Interval Register (Host mode only) (HOST_TXINTERVAL)
................................
34.4.46
Receive Type Register (Host mode only) (HOST_RXTYPE)
.........................................
34.4.47
Receive Interval Register (Host mode only) (HOST_RXINTERVAL)
................................
34.4.48
Configuration Data Register (CONFIGDATA)
...........................................................
34.4.49
Transmit and Receive FIFO Register for Endpoint 0 (FIFO0)
.........................................
34.4.50
Transmit and Receive FIFO Register for Endpoint 1 (FIFO1)
.........................................
34.4.51
Transmit and Receive FIFO Register for Endpoint 2 (FIFO2)
.........................................