Registers
1569
SPRUH82C – April 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Universal Parallel Port (uPP)
Table 32-20. uPP Interrupt Enable Set Register (UPIES) Field Descriptions (continued)
Bit
Field
Value
Description
2
ERRI
Interrupt Enable Set for Channel I Error. Reports interrupt enable for internal bus error condition on
DMA Channel I.
0
Read: Error interrupt is disabled. Write: no effect.
1
Read: Error interrupt is enabled. Write: enable ERR interrupt.
1
UORI
Interrupt Enable Set for Channel I Underrun/Overflow condition. Reports interrupt enable for underrun or
overflow condition on DMA Channel I.
0
Read: Underrun or overflow interrupt is disabled. Write: no effect.
1
Read: Underrun or overflow interrupt is enabled. Write: enable UOR interrupt.
0
DPEI
Interrupt Enable Set for Channel I Programming Error. Reports interrupt enable for programming error
condition on DMA Channel I.
0
Read: Programming error interrupt is disabled. Write: no effect.
1
Read: Programming error interrupt is enabled. Write: enable DPE interrupt.