Texas Instruments AM1808, Technical Reference Manual

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Use Cases
1359 SPRUH82C – April 2013 – Revised September 2016
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Serial ATA (SATA) Controller
Uint32 B1SecCntExp:8; //bits[15:8]
Uint32 HW1Rsv:16; //bits[31:16]
}D2HRegDW3;
typedef struct {
Uint32 W0Rsv; //bits[31:0]
}D2HRegDW4;
typedef struct {
D2HRegDW0 DW0;
D2HRegDW1 DW1;
D2HRegDW2 DW2;
D2HRegDW3 DW3;
D2HRegDW4 DW4;
}D2HRegFis;
//-----------D2H Reg FIS end Set Device Bits FIS-
// The Set Device Bit FIS definition does not contain the 2nd Word required
// for Native Command Queueing. This second word is the SACTVE register and
// the AHCI takes care of updating SACTIVE register at its location.
typedef struct {
Uint32 B0FisType:8;//bits[7:0]
Uint32 BYTE1:8; //bits[15:8]
Uint32 B2Status:8; //bits[23:16]
Uint32 B3Errror:8; //bits[31:24]
}SetDevBitsDW0;
typedef struct {
Uint32 W1Rsv; //bits[31:0]
}SetDevBitsDW1;
typedef struct {
SetDevBitsDW0 DW0;
SetDevBitsDW1 DW1;
}SetDevBitsFis;
//-----------Set Device Bits FIS end Unkonwn FIS-
typedef struct {
Uint32 UserDefined; //bits[31:0]
}UnknownDWx;
typedef struct {
UnknownDWx DW[16]; // 16 Words (Max 64 Bytes allowed)
}UnknownFis;
//-----------Unkonw FIS end----------------------
//-----------Receive Register FIS Structure------
typedef struct {
DMASetupFis DSFIS;
Uint32 Rsv1;
PIOSetupFis PSFIS;
Uint32 Rsv2[3];
D2HRegFis RFIS;
Uint32 Rsv3;
SetDevBitsFis SDBFIS;
UnknownFis UFIS;
}ReceiveFis;
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