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Architecture
1277
SPRUH82C – April 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Multimedia Card (MMC)/Secure Digital (SD) Card Controller
26.2.7 FIFO Operation During Card Write Operation
26.2.7.1 EDMA Writes
The FIFO controller manages the activities of accepting data from the CPU or EDMA and passing the data
to the MMC/SD controller. The FIFO controller issues EDMA write events as appropriate. Each time an
EDMA write event is issued, an EDMA write request interrupt generates. Data is written into the FIFO
through MMCDXR. Note that the EDMA access to MMCDXR is transparent.
provides details of the FIFO controller's operation. The CPU or EDMA controller writes data
into the FIFO. The FIFO passes the data to the MMC/SD controller which manages writing the data to the
card. When the number of bytes of data in the FIFO is less than the level set by the FIFOLEV bits in
MMCFIFOCTL, an EDMA write event is issued and new EDMA events are disabled. The FIFO controller
continues to transfer data to the MMC/SD controller while checking for the EDMA event to finish or for the
FIFO to become empty. Once the EDMA event finishes, new EDMA events are enabled. If the FIFO
becomes empty, the FIFO controller informs the MMC/SD controller.
Each time an EDMA write event generates, an interrupt (DXRDYINT) generates and the DXRDY bit in the
MMC status register 0 (MMCST0) is also set.
26.2.7.2 CPU Writes
The system CPU can also directly write the card data by writing the MMC data transmit register
(MMCDXR). The MMC/SD peripheral supports writes that are 1-, 2-, 3-, or 4-bytes wide, as shown in
The CPU makes use of the FIFO to transfer data to the card via the MMC/SD controller. The CPU writes
the data to be transferred into MMCDXR. As is the case with the EDMA driven transaction, when the
number of data in the FIFO is less than the level set by the FIFOLEV bits in MMCFIFOCTL, a DXRDYINT
interrupt generates and the DXRDY bit in the MMC status register 0 (MMCST0) is set to signify to the
CPU that space is available for new data.
NOTE:
When starting the write transaction, the CPU is responsible for getting the FIFO ready to
start transferring data by filling up the FIFO with data prior to invoking/posting the write
command to the card. Filling up the FIFO is a requirement since no interrupt/event generates
at the start of the write transfer.
26.2.8 Reset Considerations
The MMC/SD peripheral has two reset sources: hardware reset and software reset.
26.2.8.1 Software Reset Considerations
A software reset (such as a reset that the emulator generates) does not cause the MMC/SD controller
registers to alter. After a software reset, the MMC/SD controller continues to operate as it was configured
prior to the reset.
26.2.8.2 Hardware Reset Considerations
A hardware reset of the processor causes the MMC/SD controller registers to return to their default values
after reset.