Architecture
1203
SPRUH82C – April 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Multichannel Buffered Serial Port (McBSP)
25.2.5.3.7 Transmit Clock Selection: CLKXM
shows how the CLKXM bit in the pin control register (PCR) selects the transmit clock and
whether the CLKX pin is an input or output.
Table 25-4. Transmit Clock Selection
CLKXM Bit
in PCR
Source of Transmit Clock
CLKX Function
0
The external clock drives the CLKX input pin. CLKX is
inverted as determined by CLKXP before being used.
Input.
1
The sample rate generator clock (CLKG) drives the
transmit clock.
Output. CLKG is inverted as determined by CLKXP
before being driven out on CLKX.
25.2.5.3.8 Stopping Clocks
Two methods can be used to stop serial clocks between data transfers:
•
The SPI™ CLKSTP mode where clocks are stopped between single-element transfers. This mode is
not supported on this device.
•
The clocks are inputs to the McBSP (CLKXM or CLKRM = 0 in the pin control register (PCR)) and the
McBSP operates in non-SPI mode (the clocks can be stopped between data transfers). If the external
device stops the serial clock between data transfers, the McBSP interprets it as a slowed-down serial
clock. Ensure that there are no glitches on the CLK(R/X) lines as the McBSP may interpret them as
clock-edge transitions. Restarting the serial clock is equivalent to a normal clock transition after a slow
CLK(R/X) cycle. Note that just as in normal operations, transmit under flow (XEMPTY) may occur if the
DXR is not properly serviced at least three CLKX cycles before the next frame sync. Therefore, if the
serial clock is stopped before DXR is properly serviced, the external device needs to restart the clock
at least three CLKX cycles before the next frame sync to allow the DXR write to be properly
synchronized. See
for a graphical explanation on when DXR needs to be written to avoid
underflow.
25.2.5.4 Frame Sync Generation
Data frame synchronization is independently programmable for the receiver and the transmitter for all data
delay values. When the FRST bit in the serial port control register (SPCR) is set to 1 the frame generation
logic is activated to generate frame sync signals, provided that FSGM = 1 in the sample rate generator
register (SRGR). The frame sync programming options are:
•
A frame pulse with a programmable period between sync pulses and a programmable active width
specified in SRGR.
•
The transmitter can trigger its own frame sync signal that is generated by a DXR-to-XSR copy. This
causes a frame sync to occur on every DXR-to-XSR copy. The data delays can be programmed as
required. However, maximum packet frequency cannot be achieved in this method for data delays of 1
and 2.
•
Both the receiver and transmitter can independently select an external frame synchronization on the
FSR and FSX pins, respectively.
25.2.5.4.1 Frame Period (FPER) and Frame Width (FWID)
The FPER bits in the sample rate generator register (SRGR) are a 12-bit down-counter that can count
down the generated data clocks from 4095 to 0. FPER controls the period of active frame sync pulses.
The FWID bits in SRGR are an 8-bit down-counter. FWID controls the active width of the frame sync
pulse.
