Architecture
617
SPRUH82C – April 2013 – Revised September 2016
Copyright © 2013–2016, Texas Instruments Incorporated
Enhanced Direct Memory Access (EDMA3) Controller
It should be noted that back-to-back TRs are targeted to different end points even though the read return
data for the two TRs might get returned out of order (that is, read data for TR1 might come in before read
data for TR0), the transfer controller issues that the write commands are issued in order (that is, write
commands for TR0 will be issued before write commands for TR1).
17.2.11.2 Error Generation
Similar to the channel controller, the transfer controllers are capable of detecting and reporting several
error conditions. The TC errors are generated, under three main conditions:
•
BUSERR: The TC read or write controllers detect an error signaled by the source or destination
address. The additional details on the type of error is also recorded in the ERRDET register, which
indicates whether it is a read error (source address errors) or write error (destination address error).
•
MMRAERR: CPU accesses illegal/reserved addresses in the EDMA3CC/TC memory-map.
•
TRERR: A transfer request packet is detected to be violating the constant addressing mode transfer
rules (the source/destination addresses and source/destination indexes must be aligned to 32 bytes).
You can poll for the errors, as the status of the errors can be read from the ERRSTAT registers,
additionally if the error bits are enabled in the ERREN register, a bit set in the ERRSTAT will cause the
error condition to interrupt the CPU(s). You can decide to enable/disable either or all error types.
17.2.11.3 Debug Features
The DMA program register set, DMA source active register set, and the destination FIFO register set are
used to derive a brief history of TRs serviced through the transfer controller.
Additionally, the EDMA3TC status register (TCSTAT) has dedicated bit fields to indicate the ongoing
activity within different parts of the transfer controller:
•
The SRCACTV bit indicates whether the source active set is active.
•
The DSTACTV bit indicates the number of TRs resident in the destination register active set at a given
instance.
•
The PROGBUSY bit indicates whether a valid TR is present in the DMA program set.
If the TRs are in progression, caution must be used and you must realize that there is a chance that the
values read from the EDMA3TC status registers will be inconsistent since the EDMA3TC may change the
values of these registers due to ongoing activities.
It is recommended that you ensure no additional submission of TRs to the EDMA3TC in order to facilitate
ease of debug.
17.2.11.3.1 Destination FIFO Register Pointer
The destination FIFO register pointer is implemented as a circular buffer with the start pointer being
DFSTRTPTR and a buffer depth of usually 2 or 4. The EDMA3TC maintains two important status details in
TCSTAT that may be used during advanced debugging, if necessary. The DFSTRTPTR is a start pointer,
that is, the index to the head of the destination FIFO register. The DSTACTV is a counter for the number
of valid (occupied) entries. These registers may be used to get a brief history of transfers.
Examples of some register field values and their interpretation:
•
DFSTRTPTR = 0 and DSTACTV = 0 implies that no TRs are stored in the destination FIFO register.
•
DFSTRTPTR = 1 and DSTACTV = 2h implies that two TRs are present. The first pending TR is read
from the destination FIFO register entry 1 and the second pending TR is read from the destination
FIFO register entry 2.
•
DFSTRTPTR = 3h and DSTACTV = 2h implies that two TRs are present. The first pending TR is read
from the destination FIFO register entry 3 and the second pending TR is read from the destination
FIFO register entry 0.
