Texas Instruments AM1808, Technical Reference Manual

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Architecture
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924 SPRUH82C – April 2013 – Revised September 2016
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Copyright © 2013–2016, Texas Instruments Incorporated
General-Purpose Input/Output (GPIO)
20.2.5 GPIO Register Structure
The GPIO signals are grouped by banks of 16 signals per bank. Each bank of GPIO signals has several
registers with various control fields for each GPIO signal. Each 32-bit GPIO control register controls a pair
of GPIO banks.
The register names for each bank of control registers (or pair of banks of GPIO bits) are all of the form
register_nameXY , where X and Y are the two banks of GPIO bits controlled, such as 01, 23, 45, etc. The
register fields associated with each GPIO are all of the form B k P j , where k is the GPIO bank and j is the
pin number within the GPIO bank. For example, for GP2[5], which is located in GPIO bank 2, the control
register names are of the form
register_name 23, and the register field associated with GP2[5] is GP2P5.
Table 20-1 shows the banks and register control bit information associated with each GPIO pin for up to
144 supportable pins. The table is not indicative of how many GPIO pins are supported on a device; it is
only a reference for what register and field mappings look like for the first 144 supportable GPIO pins. For
devices with less than 144 GPIO pins, assume that the extraneous fields and registers listed in the table
are Reserved with no function. For devices with more than 144 GPIO pins, additional control registers and
fields should be appended using the same numbering scheme in the table. Detailed information regarding
the specific register names for each bank and the contents and function of these registers is presented in
Section 20.3 .
Table 20-1. GPIO Register Bits and Banks Associated With GPIO Signals
GPIO Pin Number GPIO Signal Name Bank Number Control Registers Register Bit Register Field
1 GP0[0] 0 register_name 01 Bit 0 GP0P0
2 GP0[1] 0 register_name 01 Bit 1 GP0P1
3 GP0[2] 0 register_name 01 Bit 2 GP0P2
4 GP0[3] 0 register_name 01 Bit 3 GP0P3
5 GP0[4] 0 register_name 01 Bit 4 GP0P4
6 GP0[5] 0 register_name 01 Bit 5 GP0P5
7 GP0[6] 0 register_name 01 Bit 6 GP0P6
8 GP0[7] 0 register_name 01 Bit 7 GP0P7
9 GP0[8] 0 register_name 01 Bit 8 GP0P8
10 GP0[9] 0 register_name 01 Bit 9 GP0P9
11 GP0[10] 0 register_name 01 Bit 10 GP0P10
12 GP0[11] 0 register_name 01 Bit 11 GP0P11
13 GP0[12] 0 register_name 01 Bit 12 GP0P12
14 GP0[13] 0 register_name 01 Bit 13 GP0P13
15 GP0[14] 0 register_name 01 Bit 14 GP0P14
16 GP0[15] 0 register_name 01 Bit 15 GP0P15
17 GP1[0] 1 register_name 01 Bit 16 GP1P0
18 GP1[1] 1 register_name 01 Bit 17 GP1P1
19 GP1[2] 1 register_name 01 Bit 18 GP1P2
20 GP1[3] 1 register_name 01 Bit 19 GP1P3
21 GP1[4] 1 register_name 01 Bit 20 GP1P4
22 GP1[5] 1 register_name 01 Bit 21 GP1P5
23 GP1[6] 1 register_name 01 Bit 22 GP1P6
24 GP1[7] 1 register_name 01 Bit 23 GP1P7
25 GP1[8] 1 register_name 01 Bit 24 GP1P8
26 GP1[9] 1 register_name 01 Bit 25 GP1P9
27 GP1[10] 1 register_name 01 Bit 26 GP1P10
28 GP1[11] 1 register_name 01 Bit 27 GP1P11
29 GP1[12] 1 register_name 01 Bit 28 GP1P12
30 GP1[13] 1 register_name 01 Bit 29 GP1P13