Section 12 DDR-SDRAM Interface (DDRIF)
Rev.1.00 Dec. 13, 2005 Page 429 of 1286
REJ09B0158-0100
12.5.6 Address
Multiplexing
Address multiplexing is performed in line with the settings of the SPLIT bits in SDR so that
connecting the SDRAM does not require an external address-multiplexing circuit. Table 12.7
shows the relationship between the settings of SPLIT bits and address multiplexing. The number
of ROW or COL line is the addresses (bit) that are output to the address pins according to the
setting of the SPLIT bits. If a setting not specified in table 12.7 is used, correct operation is not
guaranteed.
Table 12.7 Relationship between SPLIT Bits and Address Multiplexing
SPLIT[3:0] ROW × COL
BA1
BA0 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0
128 Mbit × 2
0001
12 × 9
ROW
13
12
— — 11 24 23 22 21 20 19 18 17 16 15 14
(8 M × 16 bit × 2)
COL
13
12
— — — AP
*
—
10 9 8 7 6 5 4 3 2
256 Mbit × 2
0011
13 × 9
ROW
13
12
— 11 25 24 23 22 21 20 19 18 17 16 15 14
(16 M × 16 bit × 2)
COL
13
12
— — — AP
*
—
10 9 8 7 6 5 4 3 2
512 Mbit × 2
0100
13 × 10
ROW
13
12
— 26 25 24 23 22 21 20 19 18 17 16 15 14
(32 M × 16 bit × 2)
COL
13
12
— — — AP
*
11
10 9 8 7 6 5 4 3 2
1 Gbit × 2
0110
14 × 10
ROW
13
12
27 26 25 24 23 22 21 20 19 18 17 16 15 14
(64 M × 16 bit × 2)
COL
13
12
— — — AP
*
11
10 9 8 7 6 5 4 3 2
Note:
*
Auto-precharge
Summary of Contents for SH7780 Series
Page 2: ...Rev 1 00 Dec 13 2005 Page ii of l ...
Page 28: ...Rev 1 00 Dec 13 2005 Page xxviii of l ...
Page 50: ...Rev 1 00 Dec 13 2005 Page l of l ...
Page 82: ...Section 1 Overview Rev 1 00 Dec 13 2005 Page 32 of 1286 REJ09B0158 0100 ...
Page 122: ...Section 3 Instruction Set Rev 1 00 Dec 13 2005 Page 72 of 1286 REJ09B0158 0100 ...
Page 146: ...Section 4 Pipelining Rev 1 00 Dec 13 2005 Page 96 of 1286 REJ09B0158 0100 ...
Page 196: ...Section 6 Floating Point Unit FPU Rev 1 00 Dec 13 2005 Page 146 of 1286 REJ09B0158 0100 ...
Page 292: ...Section 9 L Memory Rev 1 00 Dec 13 2005 Page 242 of 1286 REJ09B0158 0100 ...
Page 492: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Dec 13 2005 Page 442 of 1286 REJ09B0158 0100 ...
Page 674: ...Section 15 Clock Pulse Generator CPG Rev 1 00 Dec 13 2005 Page 624 of 1286 REJ09B0158 0100 ...
Page 692: ...Section 16 Watchdog Timer and Reset Rev 1 00 Dec 13 2005 Page 642 of 1286 REJ09B0158 0100 ...
Page 726: ...Section 18 Timer Unit TMU Rev 1 00 Dec 13 2005 Page 676 of 1286 REJ09B0158 0100 ...
Page 1032: ...Section 25 Audio Codec Interface HAC Rev 1 00 Dec 13 2005 Page 982 of 1286 REJ09B0158 0100 ...
Page 1150: ...Section 28 General Purpose I O GPIO Rev 1 00 Dec 13 2005 Page 1100 of 1286 REJ09B0158 0100 ...
Page 1184: ...Section 29 User Break Controller UBC Rev 1 00 Dec 13 2005 Page 1134 of 1286 REJ09B0158 0100 ...
Page 1266: ...Section 31 Electrical Characteristics Rev 1 00 Dec 13 2005 Page 1216 of 1286 REJ09B0158 0100 ...
Page 1328: ...Appendix Rev 1 00 Dec 13 2005 Page 1278 of 1286 REJ09B0158 0100 ...
Page 1336: ...Rev 1 00 Dec 13 2005 Page 1286 of 1286 REJ09B0158 0100 ...
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Page 1340: ...SH7780 Hardware Manual ...