Section 13 PCI Controller (PCIC)
Rev.1.00 Dec. 13, 2005 Page 545 of 1286
REJ09B0158-0100
D0
(normal)
D2
(clock stop)
D1
(bus idle)
D3
(power down)
Figure 13.16 PCI Local Bus Power Down State Transition
The PCIC detects when the power state (PS) bit of the PCI power management control/status
register changes (when it is written to from an external PCI device), and issues a power
management interrupt. To control the power management interrupts, there are the PCI power
management interrupt register (PCIPINT) and PCI power management interrupt mask register
(PCIPINTM). Of the power management interrupts, the power state D0 interrupt (PCIPWD0)
detects a transition from the power state D1/D2/D3 to D0, while power state D1 interrupt
(PCIPWD1) detects a transition from the power state D0 to D1, while power state D2 interrupt
(PCIPWD2) detects a transition from the power state D0/D1 to D2, while power state D3 interrupt
(PCIPWD3) detects a transition from the power state D0/D1/D2 to D3. Interrupt masks can be set
for each interrupt.
No power state D0 interrupt is generated at a power-on reset.
The following cautions should be noted when the PCIC is operating in normal mode and a power
down interrupt is received from the host: In PCI power management, the PCI local bus clock stops
within a minimum of 16 clocks after the host device has instructed a transition to power state D3.
After detecting a power state D3 interrupt, do not, therefore, attempt to read or write to local
registers and configuration registers that can be accessed from the SuperHyway bus and PCI local
bus access (I/O and memory spaces). Because these accesses operate using the PCI local bus
clock, the cycle for these accesses will not be completed if the clock stops and may be hung-up on
the SuperHyway bus.
13.4.8
PCI Local Bus Basic Interface
The PCIC of this LSI conforms to the PCI local bus specification revision 2.2 stipulations and can
be connected to a device with a PCI local bus interface. The following figures show the timing for
each operation mode.
Summary of Contents for SH7780 Series
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Page 122: ...Section 3 Instruction Set Rev 1 00 Dec 13 2005 Page 72 of 1286 REJ09B0158 0100 ...
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Page 196: ...Section 6 Floating Point Unit FPU Rev 1 00 Dec 13 2005 Page 146 of 1286 REJ09B0158 0100 ...
Page 292: ...Section 9 L Memory Rev 1 00 Dec 13 2005 Page 242 of 1286 REJ09B0158 0100 ...
Page 492: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Dec 13 2005 Page 442 of 1286 REJ09B0158 0100 ...
Page 674: ...Section 15 Clock Pulse Generator CPG Rev 1 00 Dec 13 2005 Page 624 of 1286 REJ09B0158 0100 ...
Page 692: ...Section 16 Watchdog Timer and Reset Rev 1 00 Dec 13 2005 Page 642 of 1286 REJ09B0158 0100 ...
Page 726: ...Section 18 Timer Unit TMU Rev 1 00 Dec 13 2005 Page 676 of 1286 REJ09B0158 0100 ...
Page 1032: ...Section 25 Audio Codec Interface HAC Rev 1 00 Dec 13 2005 Page 982 of 1286 REJ09B0158 0100 ...
Page 1150: ...Section 28 General Purpose I O GPIO Rev 1 00 Dec 13 2005 Page 1100 of 1286 REJ09B0158 0100 ...
Page 1184: ...Section 29 User Break Controller UBC Rev 1 00 Dec 13 2005 Page 1134 of 1286 REJ09B0158 0100 ...
Page 1266: ...Section 31 Electrical Characteristics Rev 1 00 Dec 13 2005 Page 1216 of 1286 REJ09B0158 0100 ...
Page 1328: ...Appendix Rev 1 00 Dec 13 2005 Page 1278 of 1286 REJ09B0158 0100 ...
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