Rev.1.00 Dec. 13, 2005 Page xxxvii of l
Figure 23.4 Timing Conditions when FBS = 1........................................................................... 864
Section 24 Multimedia Card Interface (MMCIF)
Figure 24.1 Block Diagram of MMCIF...................................................................................... 866
Figure 24.2 DR Access Example................................................................................................ 899
Figure 24.3 Example of Command Sequence for Commands
Not Requiring Command Response ........................................................................ 903
Figure 24.4 Example of Operational Flow for Commands
Not Requiring Command Response ........................................................................ 904
Figure 24.5 Example of Command Sequence for Commands without Data Transfer
(No Data Busy State)............................................................................................... 905
Figure 24.6 Example of Command Sequence for Commands without Data Transfer
(with Data Busy State)............................................................................................. 906
Figure 24.7 Example of Operational Flow for Commands without Data Transfer..................... 907
Figure 24.8 Example of Command Sequence for Commands with Read Data
(Block Size
≤
FIFO Size) ........................................................................................ 909
Figure 24.9 Example of Command Sequence for Commands with Read Data
(Block Size > FIFO Size) ........................................................................................ 910
Figure 24.10 Example of Command Sequence for Commands with Read Data
(Multiple Block Transfer)...................................................................................... 911
Figure 24.11 Example of Command Sequence for Commands with Read Data
(Stream Transfer)................................................................................................... 912
Figure 24.12 Example of Operational Flow for Commands with Read Data
(Single Block Transfer) ......................................................................................... 913
Figure 24.13 Example of Operational Flow for Commands with Read Data (1)
(Open-ended Multiple Block Transfer) ................................................................. 914
Figure 24.13 Example of Operational Flow for Commands with Read Data (2)
(Open-ended Multiple Block Transfer).................................................................. 915
Figure 24.13 Example of Operational Flow for Commands with Read Data (3)
(Pre-defined Multiple Block Transfer).................................................................. 916
Figure 24.13 Example of Operational Flow for Commands with Read Data (4)
(Pre-defined Multiple Block Transfer) .................................................................. 917
Figure 24.14 Example of Operational Flow for Commands with Read Data
(Stream Transfer) .................................................................................................. 918
Figure 24.15 Example of Command Sequence for Commands with Write Data
(Block Size
≤
FIFO Size) ...................................................................................... 921
Figure 24.16 Example of Command Sequence for Commands with Write Data
(Block Size > FIFO Size) ...................................................................................... 922
Figure 24.17 Example of Command Sequence for Commands with Write Data
(Multiple Block Transfer) ..................................................................................... 923
Summary of Contents for SH7780 Series
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Page 82: ...Section 1 Overview Rev 1 00 Dec 13 2005 Page 32 of 1286 REJ09B0158 0100 ...
Page 122: ...Section 3 Instruction Set Rev 1 00 Dec 13 2005 Page 72 of 1286 REJ09B0158 0100 ...
Page 146: ...Section 4 Pipelining Rev 1 00 Dec 13 2005 Page 96 of 1286 REJ09B0158 0100 ...
Page 196: ...Section 6 Floating Point Unit FPU Rev 1 00 Dec 13 2005 Page 146 of 1286 REJ09B0158 0100 ...
Page 292: ...Section 9 L Memory Rev 1 00 Dec 13 2005 Page 242 of 1286 REJ09B0158 0100 ...
Page 492: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Dec 13 2005 Page 442 of 1286 REJ09B0158 0100 ...
Page 674: ...Section 15 Clock Pulse Generator CPG Rev 1 00 Dec 13 2005 Page 624 of 1286 REJ09B0158 0100 ...
Page 692: ...Section 16 Watchdog Timer and Reset Rev 1 00 Dec 13 2005 Page 642 of 1286 REJ09B0158 0100 ...
Page 726: ...Section 18 Timer Unit TMU Rev 1 00 Dec 13 2005 Page 676 of 1286 REJ09B0158 0100 ...
Page 1032: ...Section 25 Audio Codec Interface HAC Rev 1 00 Dec 13 2005 Page 982 of 1286 REJ09B0158 0100 ...
Page 1150: ...Section 28 General Purpose I O GPIO Rev 1 00 Dec 13 2005 Page 1100 of 1286 REJ09B0158 0100 ...
Page 1184: ...Section 29 User Break Controller UBC Rev 1 00 Dec 13 2005 Page 1134 of 1286 REJ09B0158 0100 ...
Page 1266: ...Section 31 Electrical Characteristics Rev 1 00 Dec 13 2005 Page 1216 of 1286 REJ09B0158 0100 ...
Page 1328: ...Appendix Rev 1 00 Dec 13 2005 Page 1278 of 1286 REJ09B0158 0100 ...
Page 1336: ...Rev 1 00 Dec 13 2005 Page 1286 of 1286 REJ09B0158 0100 ...
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Page 1340: ...SH7780 Hardware Manual ...