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Renesas SH7780 Series, Hardware Manual

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Section 11   Local Bus State Controller (LBSC) 

 

 

Rev.1.00  Dec. 13, 2005  Page 395 of 1286 

 

 REJ09B0158-0100 

11.5.9 Bus 

Arbitration 

The LBSC is provided with a bus arbitration function that grants the bus to an external device 
when it makes a bus request. 

In normal operation, the bus is held by the LBSC (bus master), and is released to another device in 
response to a bus request. It is possible to connect an external device that issues bus requests. In 
the following description, an external device that issues bus requests is also referred to as a slave. 

The SH7780 has three internal bus masters: the CPU, DMAC, and PCIC. In addition to these are 
bus requests from external devices (highest priority). If requests occur simultaneously, the LRU 
method is used to decide the request priority. The initial priority order is : CPU > DMAC > PCIC. 

To prevent incorrect operation of connected devices when the bus is transferred between master 
and slave, all bus control signals are negated before the bus is released. When mastership of the 
bus is received, also, bus control signals begin driving the bus from the negated state. Since 
signals are driven to the same value by the master and slave exchanging the bus, output buffer 
collisions can be avoided. By turning off the output buffer on the side releasing the bus, and 
turning on the output buffer on the side receiving the bus, simultaneously with respect to the bus 
control signals, it is possible to eliminate the signal high-impedance period. It is not necessary to 
provide the pull-up resistors usually inserted in these control signal lines to prevent incorrect 
operation due to external noise in the high-impedance state. 

Bus transfer is executed between bus cycles. 

When the bus release request signal (

BREQ

) is asserted, the LBSC releases the bus as soon as the 

currently executing bus cycle ends, and outputs the bus use permission signal (

BACK

). However, 

bus release is not performed during multiple bus cycles generated because the data bus width is 
smaller than the access size (for example, when performing longword access to 8-bit bus width 
memory) or during a 32-byte transfer such as a cache fill or write-back. In addition, bus release is 
not performed between read and write cycles during execution of a TAS instruction, or between 
read and write cycles in DMA dual address mode of the bus locked. When 

BREQ

 is negated, 

BACK

 is negated and use of the bus is resumed. 

As the CPU is connected to cache memory by a dedicated internal bus, reading from cache 
memory can still be carried out when the bus is being used by another bus master inside or outside 
the SH7780. When writing from the CPU, an external write cycle is generated when write-through 
has been set for the cache in the SH7780, or when an access is made to a cache-off area. There is 
consequently a delay until the bus is returned. 

Summary of Contents for SH7780 Series

Page 1: ...Revision Date Dec 13 2005 32 SH7780 Hardware Manual Renesas 32 Bit RISC Microcomputer SuperHTM RISC Engine Family SH7780 Series R8A77800A Rev 1 00 REJ09B0158 0100 ...

Page 2: ...Rev 1 00 Dec 13 2005 Page ii of l ...

Page 3: ... a total system before making a final decision on the applicability of the information and products Renesas Technology Corp assumes no responsibility for any damage liability or other loss resulting from the information contained herein 5 Renesas Technology Corp semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is pot...

Page 4: ...ister settings and the output state of each pin are also undefined Design your system so that it does not malfunction because of processing while it is in this undefined state For those products which have a reset function reset the LSI immediately after the power supply has been turned on 4 Prohibition of Access to Undefined or Reserved Addresses Note Access to undefined or reserved addresses is ...

Page 5: ...owing items i Feature ii Input Output Pin iii Register Description iv Operation v Usage Note When designing an application system that includes this LSI take notes into account Each section includes notes in relation to the descriptions given and usage notes are given as required as the final part of each section 7 Electrical Characteristics 8 Appendix 9 Main Revisions and Additions in this Editio...

Page 6: ... logical circuits and microcomputers Objective This manual was written to explain the hardware functions and electrical characteristics of this LSI to the above users Notes on reading this manual In order to understand the overall functions of the chip Read the manual according to the contents This manual can be roughly categorized into parts on the CPU system control functions peripheral function...

Page 7: ...DR Double Data Rate DDRIF DDR SDRAM Interface DMA Direct Memory Access DMAC Direct Memory Access Controller FIFO First In First Out FLCTL NAND Flash Memory Controller FPU Floating point Unit HAC Audio Codec HSPI Serial Protocol Interface H UDI User Debugging Interface INTC Interrupt Controller JTAG Joint Test Action Group LBSC Local Bus State Controller LRAM L Memory LRU Least Recently Used LSB Le...

Page 8: ...nterconnect PCIC PCI local bus Controller RISC Reduced Instruction Set Computer RTC Realtime Clock SCIF Serial Communication Interface with FIFO SIOF Serial Interface with FIFO SSI Serial Sound Interface TAP Test Access Port TLB Translation Lookaside Buffer TMU Timer Unit UART Universal Asynchronous Receiver Transmitter UBC User Break Controller WDT Watchdog Timer ...

Page 9: ...eral Registers 37 2 2 3 Floating Point Registers 38 2 2 4 Control Registers 40 2 2 5 System Registers 42 2 3 Memory Mapped Registers 46 2 4 Data Formats in Registers 47 2 5 Data Formats in Memory 48 2 6 Processing States 49 2 7 Usage Note 50 2 7 1 Notes on self modified codes 50 Section 3 Instruction Set 51 3 1 Execution Environment 51 3 2 Addressing Modes 53 3 3 Instruction Set 57 Section 4 Pipel...

Page 10: ...General Exceptions 110 5 6 3 Interrupts 124 5 6 4 Priority Order with Multiple Exceptions 125 5 7 Usage Notes 127 Section 6 Floating Point Unit FPU 129 6 1 Features 129 6 2 Data Formats 130 6 2 1 Floating Point Format 130 6 2 2 Non Numbers NaN 133 6 2 3 Denormalized Numbers 134 6 3 Register Descriptions 135 6 3 1 Floating Point Registers 135 6 3 2 Floating Point Status Control Register FPSCR 137 6...

Page 11: ...ardware Management 173 7 4 2 MMU Software Management 173 7 4 3 MMU Instruction LDTLB 174 7 4 4 Hardware ITLB Miss Handling 175 7 4 5 Avoiding Synonym Problems 176 7 5 MMU Exceptions 177 7 5 1 Instruction TLB Multiple Hit Exception 177 7 5 2 Instruction TLB Miss Exception 178 7 5 3 Instruction TLB Protection Violation Exception 179 7 5 4 Data TLB Multiple Hit Exception 180 7 5 5 Data TLB Miss Excep...

Page 12: ...ite Through Buffer 211 8 3 6 OC Two Way Mode 211 8 4 Instruction Cache Operation 212 8 4 1 Read Operation 212 8 4 2 Prefetch Operation 213 8 4 3 IC Two Way Mode 213 8 5 Cache Operation Instruction 214 8 5 1 Coherency between Cache and External Memory 214 8 5 2 Prefetch Operation 215 8 6 Memory Mapped Cache Configuration 216 8 6 1 IC Address Array 217 8 6 2 IC Data Array 219 8 6 3 OC Address Array ...

Page 13: ...10 2 Input Output Pins 250 10 3 Register Descriptions 251 10 3 1 Interrupt Control Register 0 ICR0 255 10 3 2 Interrupt Control Register 1 ICR1 258 10 3 3 Interrupt Priority Register INTPRI 259 10 3 4 Interrupt Source Register INTREQ 260 10 3 5 Interrupt Mask Registers INTMSK0 to INTMSK2 261 10 3 6 Interrupt Mask Clear Registers INTMSKCLR0 to INTMSKCLR2 266 10 3 7 NMI Flag Control Register NMIFCR ...

Page 14: ...315 11 2 Input Output Pins 318 11 3 Area Overview 320 11 3 1 Space Divisions 320 11 3 2 Memory Bus Width 324 11 3 3 Data Alignment 325 11 3 4 PCMCIA Support 325 11 4 Register Descriptions 329 11 4 1 Memory Address Map Select Register MMSELR 331 11 4 2 Bus Control Register BCR 333 11 4 3 CSn Bus Control Register CSnBCR 336 11 4 4 CSn Wait Control Register CSnWCR 342 11 4 5 CSn PCMCIA Control Regist...

Page 15: ...AM Access 425 12 5 2 DDR SDRAM Initialization Sequence 425 12 5 3 Supported SDRAM Commands 426 12 5 4 SDRAM Access Mode 427 12 5 5 Power Down Modes 427 12 5 6 Address Multiplexing 429 12 6 DDR SDRAM Basic Timing 430 12 7 Usage Notes 440 12 7 1 Operating Frequency 440 12 7 2 Stopping Clock 440 12 7 3 Using SCR to Issue REFA Command Outside the Initialization Sequence 440 12 7 4 Timing of Connected ...

Page 16: ...ount Registers 0 to 11 TCR0 to TCR11 570 14 3 6 DMA Transfer Count Registers B0 to B3 B6 to B9 TCRB0 to TCRB3 TCRB6 to TCRB9 571 14 3 7 DMA Channel Control Registers 0 to 11 CHCR0 to CHCR11 572 14 3 8 DMA Operation Register 0 1 DMAOR0 and DMAOR1 581 14 3 9 DMA Extended Resource Selectors DMARS0 to DMARS2 584 14 4 Operation 588 14 4 1 DMA Transfer Requests 588 14 4 2 Channel Priority 592 14 4 3 DMA...

Page 17: ... Register WDTBST 631 16 3 4 Watchdog Timer Counter WDTCNT 632 16 3 5 Watchdog Timer Base Counter WDTBCNT 632 16 4 Operation 633 16 4 1 Reset request 633 16 4 2 Using watchdog timer mode 634 16 4 3 Using Interval timer mode 634 16 4 4 Time for WDT Overflow 635 16 4 5 Clearing WDT Counter 636 16 5 Status Pin Change Timing during Reset 636 16 5 1 Power On Reset by PRESET 636 16 5 2 Power On Reset by ...

Page 18: ...Features 657 18 2 Input Output Pins 659 18 3 Register Descriptions 660 18 3 1 Timer Output Control Register TOCR 662 18 3 2 Timer Start Register TSTR0 TSTR1 663 18 3 3 Timer Constant Register TCORn n 0 to 5 665 18 3 4 Timer Counter TCNTn n 0 to 5 665 18 3 5 Timer Control Registers TCRn n 0 to 5 666 18 3 6 Input Capture Register 2 TCPR2 668 18 4 Operation 669 18 4 1 Counter Operation 669 18 4 2 Inp...

Page 19: ...05 19 4 9 Interrupts 706 Section 20 Realtime Clock RTC 707 20 1 Features 707 20 1 1 Block Diagram 708 20 2 Input Output Pins 709 20 3 Register Descriptions 710 20 3 1 64 Hz Counter R64CNT 712 20 3 2 Second Counter RSECCNT 712 20 3 3 Minute Counter RMINCNT 713 20 3 4 Hour Counter RHRCNT 713 20 3 5 Day of Week Counter RWKCNT 714 20 3 6 Day Counter RDAYCNT 715 20 3 7 Month Counter RMONCNT 716 20 3 8 ...

Page 20: ...O Data Register SCFTDR 743 21 3 5 Serial Mode Register SCSMR 744 21 3 6 Serial Control Register SCSCR 747 21 3 7 Serial Status Register n SCFSR 751 21 3 8 Bit Rate Register n SCBRR 758 21 3 9 FIFO Control Register n SCFCR 759 21 3 10 Transmit FIFO Data Count Register n SCTFDR 762 21 3 11 Receive FIFO Data Count Register n SCRFDR 763 21 3 12 Serial Port Register n SCSPTR 764 21 3 13 Line Status Reg...

Page 21: ...a Format 830 22 4 4 Register Allocation of Transfer Data 832 22 4 5 Control Data Interface 834 22 4 6 FIFO 836 22 4 7 Transmit and Receive Procedures 838 22 4 8 Interrupts 843 22 4 9 Transmit and Receive Timing 845 Section 23 Serial Protocol Interface HSPI 849 23 1 Features 849 23 2 Input Output Pins 851 23 3 Register Descriptions 851 23 3 1 Control Register SPCR 852 23 3 2 Status Register SPSR 85...

Page 22: ... 24 3 13 Transfer Block Number Counter TBNCR 894 24 3 14 Response Registers 0 to 16 D RSPR0 to RSPR16 RSPRD 895 24 3 15 Data Timeout Register DTOUTR 897 24 3 16 Data Register DR 898 24 3 17 FIFO Pointer Clear Register FIFOCLR 899 24 3 18 DMA Control Register DMACR 900 24 4 Operation 901 24 4 1 Operations in MMC Mode 901 24 5 MMCIF Interrupt Sources 931 24 6 Operations when Using DMA 932 24 6 1 Ope...

Page 23: ... 26 3 1 Control Register SSICR 986 26 3 2 Status Register SSISR 992 26 3 3 Transmit Data Register SSITDR 997 26 3 4 Receive Data Register SSIRDR 997 26 4 Operation 998 26 4 1 Bus Format 998 26 4 2 Non Compressed Modes 999 26 4 3 Compressed Modes 1008 26 4 4 Operation Modes 1011 26 4 5 Transmit Operation 1012 26 4 6 Receive Operation 1015 26 4 7 Serial Clock Control 1018 26 5 Usage Note 1019 26 5 1...

Page 24: ...rces 1053 27 7 DMA Transfer Specifications 1053 Section 28 General Purpose I O GPIO 1055 28 1 Features 1055 28 2 Register Descriptions 1060 28 2 1 Port A Control Register PACR 1063 28 2 2 Port B Control Register PBCR 1064 28 2 3 Port C Control Register PCCR 1066 28 2 4 Port D Control Register PDCR 1067 28 2 5 Port E Control Register PECR 1069 28 2 6 Port F Control Register PFCR 1070 28 2 7 Port G ...

Page 25: ...n chip Module Function 1099 Section 29 User Break Controller UBC 1101 29 1 Features 1101 29 2 Register Descriptions 1103 29 2 1 Match Condition Setting Registers 0 and 1 CBR0 and CBR1 1105 29 2 2 Match Operation Setting Registers 0 and 1 CRR0 and CRR1 1111 29 2 3 Match Address Setting Registers 0 and 1 CAR0 and CAR1 1113 29 2 4 Match Address Mask Setting Registers 0 and 1 CAMR0 and CAMR1 1114 29 2...

Page 26: ...55 31 1 Absolute Maximum Ratings 1155 31 2 DC Characteristics 1156 31 3 AC Characteristics 1159 31 3 1 Clock and Control Signal Timing 1160 31 3 2 Control Signal Timing 1163 31 3 3 Bus Timing 1164 31 3 4 DDRIF Signal Timing 1182 31 3 5 INTC Module Signal Timing 1186 31 3 6 PCIC Module Signal Timing 1188 31 3 7 DMAC Module Signal Timing 1190 31 3 8 TMU Module Signal Timing 1191 31 3 9 CMT Module Si...

Page 27: ...ster CPUOPM 1217 B Instruction Prefetching and Its Side Effects 1219 C Speculative Execution for Subroutine Return 1220 D Register Address Map 1221 E Package Dimensions 1255 F Mode Pin Settings 1256 G Pin Functions 1258 G 1 Pin States 1258 G 2 Handling of Unused Pins 1267 H Turning On and Off Power Supply 1275 I Version Registers PVR PRR 1276 J Part Number List 1277 Index 1279 ...

Page 28: ...Rev 1 00 Dec 13 2005 Page xxviii of l ...

Page 29: ...lines 73 Figure 4 2 Instruction Execution Patterns 1 75 Figure 4 2 Instruction Execution Patterns 2 76 Figure 4 2 Instruction Execution Patterns 3 77 Figure 4 2 Instruction Execution Patterns 4 78 Figure 4 2 Instruction Execution Patterns 5 79 Figure 4 2 Instruction Execution Patterns 6 80 Figure 4 2 Instruction Execution Patterns 7 81 Figure 4 2 Instruction Execution Patterns 8 82 Figure 4 2 Inst...

Page 30: ...ess Space 32 Bit Address Extended Mode 188 Figure 7 17 PMB Configuration 190 Figure 7 18 Memory Mapped PMB Address Array 193 Figure 7 19 Memory Mapped PMB Data Array 193 Section 8 Caches Figure 8 1 Configuration of Operand Cache OC 198 Figure 8 2 Configuration of Instruction Cache IC 199 Figure 8 3 Configuration of Write Back Buffer 211 Figure 8 4 Configuration of Write Through Buffer 211 Figure 8...

Page 31: ...ng for PCMCIA I O Card Interface 380 Figure 11 19 Wait Timing for PCMCIA I O Card Interface 381 Figure 11 20 Dynamic Bus Sizing Timing for PCMCIA I O Card Interface 382 Figure 11 21 Example of 32 Bit Data Width MPX Connection 384 Figure 11 22 MPX Interface Timing 1 Single Read Cycle IW 0 No External Wait 384 Figure 11 23 MPX Interface Timing 2 Single Read IW 0 One External Wait Inserted 385 Figure...

Page 32: ... Burst Write 32 byte without Auto Precharge 435 Figure 12 11 DDRIF Basic Timing from Precharging All Banks to Bank Activation 436 Figure 12 12 DDRIF Basic Timing Mode Register Setting 437 Figure 12 13 DDRIF Basic Timing Enter Auto Refresh Exit to Bank Activation 438 Figure 12 14 DDRIF Basic Timing Enter Self Refresh Exit to Command Issuing 439 Section 13 PCI Controller PCIC Figure 13 1 PCIC Block ...

Page 33: ... Target Memory Read Cycle in Host Bus Bridge Mode Burst with stepping 556 Section 14 Direct Memory Access Controller DMAC Figure 14 1 Block Diagram of DMAC 558 Figure 14 2 Round Robin Mode example of channel 0 to 5 593 Figure 14 3 Changes in Channel Priority in Round Robin Mode example of channel 0 to 5 594 Figure 14 4 Data Flow of Dual Address Mode 595 Figure 14 5 Example of DMA Transfer Timing i...

Page 34: ...ual Reset during Sleep Mode 641 Section 17 Power Down Mode Figure 17 1 DDR SDRAM Interface Operation when Turning System Power Supply On Off 650 Figure 17 2 Sequence for Turning Off System Power Supply in Self Refresh Mode 652 Figure 17 3 Sequence for Turning System Power Supply On Off 654 Figure 17 4 Mode Transition Diagram 655 Figure 17 5 Status Pins Output from Sleep to Interrupt 656 Section 18...

Page 35: ...eration Count Up Timing 705 Figure 19 18 Rotary Switch Operation Count Down Timing 705 Section 20 Realtime Clock RTC Figure 20 1 Block Diagram of RTC 708 Figure 20 2 Examples of Time Setting Procedures 727 Figure 20 3 Examples of Time Reading Procedures 728 Figure 20 4 Example of Use of Alarm Function 729 Figure 20 5 Example of Crystal Oscillator Circuit Connection 731 Figure 20 6 Interrupt Reques...

Page 36: ...igure 22 3 Serial Data Synchronization Timing 829 Figure 22 4 SIOF Transmit Receive Timing 830 Figure 22 5 Transmit Receive Data Bit Alignment 832 Figure 22 6 Control Data Bit Alignment 833 Figure 22 7 Control Data Interface Slot Position 834 Figure 22 8 Control Data Interface Secondary FS 835 Figure 22 9 Example of Transmit Operation in Master Mode 838 Figure 22 10 Example of Receive Operation in...

Page 37: ...d Sequence for Commands with Read Data Multiple Block Transfer 911 Figure 24 11 Example of Command Sequence for Commands with Read Data Stream Transfer 912 Figure 24 12 Example of Operational Flow for Commands with Read Data Single Block Transfer 913 Figure 24 13 Example of Operational Flow for Commands with Read Data 1 Open ended Multiple Block Transfer 914 Figure 24 13 Example of Operational Flo...

Page 38: ...ad Sequence Flow 4 Pre defined Multiple Block Transfer 938 Figure 24 24 Example of Operational Flow for Stream Read Transfer 939 Figure 24 25 Example of Operational Flow for Auto mode Pre defined Multiple Block Read Transfer 1 940 Figure 24 25 Example of Operational Flow for Auto mode Pre defined Multiple Block Read Transfer 2 941 Figure 24 26 Example of Write Sequence Flow 1 Single Block Transfer...

Page 39: ...Bits First Followed by Serial Data with Delay 1006 Figure 26 14 Padding Bits First Followed by Serial Data without Delay 1007 Figure 26 15 Serial Data First Followed by Padding Bits without Delay 1007 Figure 26 16 Parallel Right Aligned with Delay 1007 Figure 26 17 Mute Enabled 1008 Figure 26 18 Compressed Data Format Slave Transmitter Burst Mode Disabled 1009 Figure 26 19 Compressed Data Format S...

Page 40: ...cs Figure 31 1 EXTAL Clock Input Timing 1161 Figure 31 2 CLKOUT Clock Output Timing 1 1161 Figure 31 3 CLKOUT Clock Output Timing 2 1161 Figure 31 4 Power On Oscillation Settling Time 1162 Figure 31 5 MODE pins Setup Hold Timing 1162 Figure 31 6 PLL Synchronization Settling Time 1163 Figure 31 7 Control Signal Timing 1163 Figure 31 8 SRAM Bus Cycle Basic Bus Cycle No Wait 1165 Figure 31 9 SRAM Bus...

Page 41: ...t Timing 1191 Figure 31 35 CMT Timing 1 1192 Figure 31 36 CMT Timing 2 1192 Figure 31 37 SCIFn_SCK Input Clock Timing n 0 1 1193 Figure 31 38 SCIF Channel n I O Synchronous Mode Clock Timing n 0 1 1194 Figure 31 39 SIOF_MCLK Input Timing 1195 Figure 31 40 SIOF Transmission Reception Timing Master Mode 1 Fall Sampling 1196 Figure 31 41 SIOF Transmission Reception Timing Master Mode 1 Rise Sampling ...

Page 42: ...pe Flash Memory 1210 Figure 31 61 Status Read Timing of NAND type Flash Memory 1210 Figure 31 62 GPIO Timing 1211 Figure 31 63 TCK Input Timing 1212 Figure 31 64 PRESET Hold Timing 1213 Figure 31 65 H UDI Data Transfer Timing 1213 Figure 31 66 ASEBRK Pin Break Timing 1213 Figure 31 67 Output Load Circuit 1214 Figure 31 68 Load Capacitance Delay Time 1215 Appendix Figure B 1 Instruction Prefetch 12...

Page 43: ...able 3 9 System Control Instructions 66 Table 3 10 Floating Point Single Precision Instructions 69 Table 3 11 Floating Point Double Precision Instructions 70 Table 3 12 Floating Point Control Instructions 70 Table 3 13 Floating Point Graphics Acceleration Instructions 71 Section 4 Pipelining Table 4 1 Representations of Instruction Execution Patterns 74 Table 4 2 Instruction Groups 84 Table 4 3 Co...

Page 44: ...n INT2A0 and Sources 277 Table 10 7 Correspondence between Bits in INT2A1 and Sources 280 Table 10 8 Correspondence between Bits in INT2MSKR and Interrupt Masking 283 Table 10 9 Correspondence between Bits in INT2MSKCR and Interrupt Mask Clearing 285 Table 10 10 Correspondence between Interrupt Input Pins and Bits in INT2GPIC 295 Table 10 11 IRL 3 0 IRL 7 4 Pins and Interrupt Levels 298 Table 10 1...

Page 45: ...ress Multiplexing 429 Section 13 PCI Controller PCIC Table 13 1 Input Output Pins 446 Table 13 2 List of PCIC Registers 449 Table 13 3 Register States in Each Operating Mode 452 Table 13 4 Supported Bus Commands 522 Table 13 5 PCIC Address Map 524 Table 13 6 Interrupt Priority 543 Section 14 Direct Memory Access Controller DMAC Table 14 1 Pin Configuration 559 Table 14 2 Register Configuration of ...

Page 46: ...le 18 3 Register States in Each Processing Mode 661 Table 18 4 TMU Interrupt Sources 674 Section 19 Timer Counter CMT Table 19 1 Pin Configuration 679 Table 19 2 Register Configuration 679 Table 19 3 Register States of CMT in Each Processing Mode 680 Table 19 4 32 bit Timer Mode Example of Input Capture Setting 693 Table 19 5 32 bit Timer Mode Example of Output Compare Setting 696 Table 19 6 16 bi...

Page 47: ...fer Modes 830 Table 22 7 Frame Length 831 Table 22 8 Audio Mode Specification for Transmit Data 833 Table 22 9 Audio Mode Specification for Receive Data 833 Table 22 10 Setting Number of Channels in Control Data 834 Table 22 11 Conditions to Issue Transmit Request 836 Table 22 12 Conditions to Issue Receive Request 836 Table 22 13 Transmit and Receive Reset 842 Table 22 14 SIOF Interrupt Sources 8...

Page 48: ... Read of NAND Type Flash Memory 1049 Table 27 5 FLCTL Interrupt Requests 1053 Table 27 6 DMA Transfer Specifications 1053 Section 28 General Purpose I O GPIO Table 28 1 Multiplexed Pins Controlled by Port Control Registers 1056 Table 28 2 Register Configuration 1060 Table 28 3 Register States of GPIO in Each Processing Mode 1062 Section 29 User Break Controller UBC Table 29 1 Register Configuratio...

Page 49: ...al Timing 1193 Table 31 15 SIOF Module Signal Timing 1195 Table 31 16 HSPI Module Signal Timing 1199 Table 31 17 MMCIF Module Signal Timing 1201 Table 31 18 HAC Interface Module Signal Timing 1203 Table 31 19 SSI Interface Module Signal Timing 1205 Table 31 20 FLCTL Module Signal Timing 1207 Table 31 21 GPIO Signal Timing 1211 Table 31 22 H UDI Module Signal Timing 1212 Appendix Table F 1 Clock Op...

Page 50: ...Rev 1 00 Dec 13 2005 Page l of l ...

Page 51: ...oller timers and serial communications functions with an audio interface as required for multimedia network and OA equipment use of the SH7780 enables a high performance and high integrated system The SH7780 contains the new generation SH 4A 32 bit RISC reduced instruction set computer microprocessor core which runs at 400 MHz 720 MIPS 2 8 GFLOPS The SH 4A is upwardly compatible with the SH 1 SH 2...

Page 52: ... address data multiplexing External bus frequency 33M or 66 MHz CPU Renesas Technology original architecture 32 bit internal data bus General register files Sixteen 32 bit general registers eight 32 bit shadow registers Seven 32 bit control registers Four 32 bit system registers RISC type instruction set upward compatible with the SH 1 SH 2 SH 3 and SH 4 microcomputers Instruction length 16 bit fi...

Page 53: ...ion register FPUL Supports FMAC multiply and accumulate instruction Supports FDIV divide and FSQRT square root instructions Supports FLDI0 FLDI1 load constant 0 1 instructions Instruction execution times Latency FADD FSUB 3 cycles single precision 5 cycles double precision Latency FMAC FMUL 5 cycles single precision 7 cycles double precision Pitch FADD FSUB 1 cycle single precision double precisio...

Page 54: ...nd random counter replacement algorithms Contents of TLB are directly accessible through address mapping Cache memory Instruction cache IC 32 Kbyte 4 way set associative 32 byte block length Operand cache OC 32 Kbyte 4 way set associative 32 byte block length Selectable write method copy back or write through Storage queue 32 bytes 2 entries L memory Three independent read write ports Instruction ...

Page 55: ...e access type and data size are available as break condition settings Supports sequential break functions Local bus state controller LBSC Supports external memory access External memory space divided into seven areas each of up to 64 Mbytes with the following parameters settable for each area Bus size 8 16 or 32 bits Number of wait cycles hardware wait function also supported SRAM or burst ROM Sup...

Page 56: ...or 32 bits 16 or 32 bytes Address modes 2 bus cycle dual address mode Transfer requests External channel 0 to 3 peripheral module channel 0 to 5 or auto requests Choice of DACK or DRAK four external pins Bus modes Cycle steal or burst mode Clock pulse generator CPG Main clock 12 times XTAL clock Clock modes CPU frequency 1 1 time main clock Local bus frequency 1 4 1 6 1 8 or 1 12 times main clock ...

Page 57: ... full duplex communications channels On chip 64 byte FIFOs for all channels Choice of asynchronous mode or synchronous mode Can select any bit rate generated by on chip baud rate generator On chip modem control function SCIF0_RTS and SCIF0_CTS for channel 0 Serial I O with FIFO SIOF Internal 64 byte transmit receive FIFOs Supports 8 16 bit data and 16 bit stereo audio input output Sampling rate cl...

Page 58: ... compressed mode is used for continuous bit stream transfer The non compressed mode supports all serial audio streams divided into channels The SSI module is configured as any of a transmitter or receiver The serial bus format can be used in the compressed and non compressed mode NAND flash memory controller FLCTL Interface connectable to a NAND type flash memory Read or write in sector units 512 ...

Page 59: ...face Instruction cache Interrupt controller Local bus state controller L memory Multimedia card interface Memory management unit Operand data cache PCI controller Realtime clock SCIF SIOF SSI SuperHyway RAM TMU UBC WDT Serial communication interface with FIFO Serial I O with FIFO Serial sound interface SuperHyway memory Timer unit User break controller Watchdog timer FPU MMU O cache LRAM SH 4A cor...

Page 60: ...ODE8 SIOF_TXD HAC_SDOUT SSI_SDATA DACK3 IRQOUT AUDATA3 DACK0 MODE0 AUDSYNC FCE AUDCK FALE AUDATA3 FD3 AUDATA2 FD2 DACK1 MODE1 VDDQ VDD VSSQ VSS VSS VSS VSS VSS VSS VSS VSS VSS Top view VSS VSS VSS VSS VSS VSS VSS VSS VSS DDR VSS DDR VSS DDR VSS VSS VSS VSSQ VSSQ VSSQ VSSQ VSSQ VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VDDQ ASEBRK BRKACK AUDATA1 FD1 AUD...

Page 61: ...R write enable 7 A7 MRAS O DDR RAS 8 A8 BA0 O DDR bank address 0 9 A9 MA10 O DDR address 10 A10 MA1 O DDR address 11 A11 MA3 O DDR address 12 A12 PRESET I Power on reset 13 A13 DRAK1 MODE7 O I DMA channel 1 transfer request acknowledge mode control 7 L0 O 14 A14 DREQ0 I DMA channel 0 request K7 15 A15 DREQ3 INTC AUDATA1 I I O DMA channel 3 request PCI interrupt C H UDI emulator K4 16 A16 DACK2 MRE...

Page 62: ... DDR address 35 B10 MA2 O DDR address 36 B11 MA4 O DDR address 37 B12 VSS Internal GND 38 B13 DRAK2 CE2A AUDCK O O O DMA channel 2 transfer request acknowledge PCMCIA CE2 H UDI emulator K1 O 39 B14 DREQ1 I DMA channel 1 request K6 40 B15 DACK0 MODE0 O I DMA channel 0 bus acknowledgement mode control 0 L3 O 41 B16 DACK3 IRQOUT AUDATA3 O O O DMA channel 3 bus acknowledgement interrupt request output...

Page 63: ...O DDR address 62 C12 DRAK0 MODE2 O I DMA channel 0 transfer request acknowledge mode control 2 L1 O 63 C13 DRAK3 CE2B AUDSYNC O O O DMA channel 3 request acknowledgment PCMCIA CE2 H UDI emulator K0 O 64 C14 DREQ2 INTB AUDATA0 I I O DMA channel 2 request PCI interrupt B H UDI emulator K5 65 C15 DACK1 MODE1 O I DMA channel 1 bus acknowledgement mode control 1 L2 O 66 C16 TCK I H UDI clock 67 C17 ASE...

Page 64: ...3 VSSQ DDR DDR I O GND 79 D4 VCCQ DDR DDR I O VCC 80 D5 VSSQ DDR DDR I O GND 81 D6 VSSQ DDR DDR I O GND 82 D7 VCCQ DDR DDR I O VCC 83 D8 VCCQ DDR DDR I O VCC 84 D9 VSSQ DDR DDR I O GND 85 D10 VSSQ DDR DDR I O GND 86 D11 VCCQ DDR DDR I O VCC 87 D12 VSSQ I O GND 88 D13 VDDQ I O VDD 89 D14 VDDQ I O VDD 90 D15 VSSQ I O GND 91 D16 TMS I H UDI emulator 92 D17 TRST I H UDI emulator 93 D18 AUDATA2 FD2 O I...

Page 65: ... 105 E5 VSSQ DDR DDR I O GND 106 E6 VSSQ DDR DDR I O GND 107 E7 VCCQ DDR DDR I O VCC 108 E8 VDD Internal VDD 109 E9 VSS Internal GND 110 E10 VSSQ DDR DDR I O GND 111 E11 VCCQ DDR DDR I O VCC 112 E12 VSSQ I O GND 113 E13 VDDQ I O VDD 114 E14 VDD Internal VDD 115 E15 VSS Internal GND 116 E16 VSSQ I O GND 117 E17 VSSQ I O GND 118 E18 VDDQ I O VDD 119 E19 VDDQ I O VDD 120 E20 VDDQ I O VDD 121 E21 VSSQ...

Page 66: ...askable interrupt 136 G1 MDA4 IO DDR data 137 G2 MDA21 IO DDR data 138 G3 MDA22 IO DDR data 139 G4 VSS Internal GND 140 G5 VSS Internal GND 141 G21 VSSQ I O GND 142 G22 AD1 IO PCI address data D1 143 G23 AD3 IO PCI address data D3 144 G24 AD5 IO PCI address data D5 145 G25 AD0 IO PCI address data D0 146 H1 MDA5 IO DDR data 147 H2 MDA23 IO DDR data 148 H3 MDQS2 IO DDR data strobe 149 H4 VDD Interna...

Page 67: ...BE0 IO PCI command byte enable 166 K1 MDQM0 O DDR data mask 167 K2 MDQS0 IO DDR data strobe 168 K3 MDQS3 IO DDR data strobe 169 K4 VDD Internal VDD 170 K5 VSS Internal GND 171 K10 VSS Internal GND 172 K11 VSS Internal GND 173 K12 VSS Internal GND 174 K13 VSS Internal GND 175 K14 VSS Internal GND 176 K15 VSS Internal GND 177 K16 VSS Internal GND 178 K21 VDD Internal VDD 179 K22 AD14 IO PCI address ...

Page 68: ...nal GND 195 L21 VDDQ I O VDD 196 L22 SERR IO PCI system error 197 L23 PERR IO PCI parity error 198 L24 AD13 IO PCI address data C5 199 L25 AD15 IO PCI address data C7 200 M1 MDA8 IO DDR data 201 M2 MDA24 IO DDR data 202 M3 MDA25 IO DDR data 203 M4 VDD DLL2 DLL2 VDD 204 M5 VSS DLL2 DLL2 GND 205 M10 VSS Internal GND 206 M11 VSS Internal GND 207 M12 VSSQ DDR DDR I O GND 208 M13 VSSQ I O GND 209 M14 V...

Page 69: ...Q DDR DDR I O GND 225 N13 VSSQ I O GND 226 N14 VSS Internal GND 227 N15 VSS Internal GND 228 N16 VSS Internal GND 229 N21 VSS Internal GND 230 N22 IRDY IO PCI initiator ready 231 N23 CBE2 IO PCI command byte enable 232 N24 TRDY IO PCI target ready 233 N25 PCIFRAME IO PCI cycle frame 234 P1 MDA10 IO DDR data 235 P2 MDA28 IO DDR data 236 P3 MDA29 IO DDR data 237 P4 VCCQ DDR DDR I O VCC 238 P5 VCCQ D...

Page 70: ...a 254 R4 VCCQ DDR DDR I O VCC 255 R5 VCCQ DDR DDR I O VCC 256 R10 VSS Internal GND 257 R11 VSS Internal GND 258 R12 VSS Internal GND 259 R13 VSSQ I O GND 260 R14 VSS Internal GND 261 R15 VSS Internal GND 262 R16 VSS Internal GND 263 R21 VDDQ I O VDD 264 R22 AD21 IO PCI address data B5 265 R23 AD23 IO PCI address data B7 266 R24 AD20 IO PCI address data B4 267 R25 AD22 IO PCI address data B6 268 T1...

Page 71: ...a A0 285 U1 MDA15 IO DDR data 286 U2 MDA14 IO DDR data 287 U3 VSSQ DDR DDR I O GND 288 U4 VSSQ DDR DDR I O GND 289 U5 VSSQ DDR DDR I O GND 290 U21 VDD Internal VDD 291 U22 AD27 IO PCI address data A3 292 U23 AD29 IO PCI address data A5 293 U24 AD26 IO PCI address data A2 294 U25 AD28 IO PCI address data A4 295 V1 VCCQ DDR DDR I O VCC 296 V2 VCCQ DDR DDR I O VCC 297 V3 VCCQ DDR DDR I O VCC 298 V4 V...

Page 72: ...host E5 313 W24 GNT2 O PCI bus grant E1 314 W25 GNT1 O PCI bus grant E2 315 Y1 A22 O Address bus 316 Y2 A23 O Address bus 317 Y3 A24 O Address bus 318 Y4 VSS Internal GND 319 Y5 VSS Internal GND 320 Y21 VDDQ I O VDD 321 Y22 REQ0 REQOUT I O Bus request PCI host bus request output 322 Y23 PCICLK I PCI input clock 323 Y24 GNT0 GNTIN O I PCI bus grant 324 Y25 PCIRESET O PCI reset 325 AA1 A19 O Address...

Page 73: ...VDDQ I O VDD 343 AA19 VSSQ I O GND 344 AA20 VSSQ I O GND 345 AA21 VSSQ I O GND 346 AA22 NC Open 347 AA23 NC Open 348 AA24 VSS Internal GND 349 AA25 INTA IO PCI interrupt A 350 AB1 A16 O Address bus 351 AB2 A17 O Address bus 352 AB3 A18 O Address bus 353 AB4 VSSQ I O GND 354 AB5 A6 O Address bus 355 AB6 A2 O Address bus 356 AB7 D30 IO Data bus F6 357 AB8 D26 IO Data bus F2 358 AB9 D23 IO Data bus G...

Page 74: ... VDD 373 AB24 VSS Internal GND 374 AB25 VSS Internal GND 375 AC1 A14 O Address bus 376 AC2 A15 O Address bus 377 AC3 VDDQ I O VDD 378 AC4 A9 O Address bus 379 AC5 A5 O Address bus 380 AC6 A1 O Address bus 381 AC7 D29 IO Data bus F5 382 AC8 D25 IO Data bus F1 383 AC9 D22 IO Data bus G6 384 AC10 D19 IO Data bus G3 385 AC11 D15 IO Data bus 386 AC12 D14 IO Data bus 387 AC13 D11 IO Data bus 388 AC14 D8...

Page 75: ...ress bus 404 AD5 A4 O Address bus 405 AD6 A0 O Address bus 406 AD7 D28 IO Data bus F4 407 AD8 D24 IO Data bus F0 408 AD9 D21 IO Data bus G5 409 AD10 D18 IO Data bus G2 410 AD11 D16 IO Data bus G0 411 AD12 D13 IO Data bus 412 AD13 D10 IO Data bus 413 AD14 D7 IO Data bus 414 AD15 D5 IO Data bus 415 AD16 D2 IO Data bus 416 AD17 D0 IO Data bus 417 AD18 RD FRAME O Read strobe MPX interface cycle frame ...

Page 76: ...10 D17 IO Data bus G1 435 AE11 WE2 IORD O O Selection signal for D23 to D16 PCMCIA IORD 436 AE12 D12 IO Data bus 437 AE13 D9 IO Data bus 438 AE14 WE1 O Selection signal for D15 to D8 439 AE15 D4 IO Data bus 440 AE16 D1 IO Data bus 441 AE17 WE0 REG O O Selection signal for D7 to D0 PCMCIA REG 442 AE18 R W O Read write 443 AE19 RDY I Bus ready 444 AE20 CLKOUT O Clock output 445 AE21 VDD PLL2 PLL2 VD...

Page 77: ...PCIC has up to 512 Mbytes external memory space individually and the SH7780 can control the external memory space up to 1152 Mbytes totally Areas 0 1 and 6 are controlled by the LBSC Areas 2 4 and 5 are controlled by the LBSC DDRIF or PCIC that depends on the setting of the memory address map select register MMSELR of the LBSC Note that area 3 is for the DDRIF For details see section 11 Local Bus ...

Page 78: ...FC00 0000 H FC80 0000 H FD00 0000 H FE00 0000 H FE40 0000 H FE80 0000 H FF00 0000 H FF40 0000 H FF80 0000 H FFC0 0000 Control register area H FC00 0000 to H FFFF FFFF 32 bit physical address space Extended mode H E000 0000 H E500 0000 H F000 0000 29 bit physical address space Normal mode Note For details of these areas refer to section 7 1 1 Address Spaces H UDI 8MB DMAC 8MB PCI memory 16MB PCIC 4...

Page 79: ...2 DDRIF 3 DDRIF 1 DDRIF 0 DDRIF 2 DDRIF 3 DDRIF 1 DDRIF 0 DDRIF 1 DDRIF 0 DDRIF 2 DDRIF 3 DDRIF 2 DDRIF 3 DDRIF 1 DDRIF 0 DDRIF 2 DDRIF 3 DDRIF 1 DDRIF 0 DDRIF 2 DDRIF 3 DDRIF 1 DDRIF 0 DDRIF 1 DDRIF 0 DDRIF 2 DDRIF 3 DDRIF 2 DDRIF 3 DDRIF 1 DDRIF 0 DDRIF 2 DDRIF 3 DDRIF 1 DDRIF 0 DDRIF 2 DDRIF 3 DDRIF 1 DDRIF 0 DDRIF 1 H 0000 0000 H 0400 0000 H 0800 0000 H 0C00 0000 H 1000 0000 H 1400 0000 H 1800...

Page 80: ... is CPU DMAC PCIC The response priority level is fixed peripheral modules DMAC CPU SuperHyway RAM LBSC PCIC DDRIF Note that when using debugging function H UDI emulator the debugging functional module has the highest priority The transfer data size varies with each module For details refer to the corresponding section for each module An actual transaction on the SuperHyway bus is started from a re...

Page 81: ...ory is enabled by the SuperHyway bus master Access The SuperHyway memory is always accessed by the SuperHyway bus master module including the CPU via the SuperHyway bus which is a physical address bus 1 2 4 8 16 32 byte access is possible for both reading and writing with wraparound on 32 byte boundary data A 32 byte cache fill can be read out with one access an 8 byte 4 transfer on the SuperHyway...

Page 82: ...Section 1 Overview Rev 1 00 Dec 13 2005 Page 32 of 1286 REJ09B0158 0100 ...

Page 83: ... LSI has registers and data formats as shown below 2 1 Data Formats The data formats supported in this LSI are shown in figure 2 1 Byte 8 bits Word 16 bits Longword 32 bits Single precision floating point 32 bits Double precision floating point 64 bits 0 7 0 15 0 31 0 31 30 22 s e f 0 63 62 51 s e f Legend s e f Sign field Exponent field Fraction field Figure 2 1 Data Formats ...

Page 84: ...is case the eight registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 are accessed by the LDC STC instructions When the RB bit is 0 that is when bank 0 is selected the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non banked general registers R8 to R15 can be accessed as general registers R0 to R15 In this case the eight registers comprising bank 1 genera...

Page 85: ...on register FPUL and the floating point status control register FPSCR These registers are used for communication between the FPU and the CPU and the exception handling setting Register values after a reset are shown in table 2 1 Table 2 1 Initial Register Values Type Registers Initial Value General registers R0_BANK0 to R7_BANK0 R0_BANK1 to R7_BANK1 R8 to R15 Undefined SR MD bit 1 RB bit 1 BL bit ...

Page 86: ...2_BANK1 3 R3_BANK1 3 R4_BANK1 3 R5_BANK1 3 R6_BANK1 3 R7_BANK1 3 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK0 1 4 R1_BANK0 4 R2_BANK0 4 R3_BANK0 4 R4_BANK0 4 R5_BANK0 4 R6_BANK0 4 R7_BANK0 4 c Register configuration in privileged mode RB 0 GBR MACH MACL VBR PR SR SSR PC SPC SGR DBR SGR DBR R0 is used as the index register in indexed register indirect addressing mode and indexed GBR indirect addressing m...

Page 87: ...to R7 in user mode SR MD 0 Allocated to R0 to R7 when SR RB 0 in privileged mode SR MD 1 R0_BANK1 to R7_BANK1 Cannot be accessed in user mode Allocated to R0 to R7 when SR RB 1 in privileged mode SR MD 0 or SR MD 1 SR RB 0 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK1 R1_BANK1 R2_BANK1 R3_BAN...

Page 88: ... FPR15_BANK1 2 Single precision floating point registers FRi 16 registers When FPSCR FR 0 FR0 to FR15 are assigned to FPR0_BANK0 to FPR15_BANK0 when FPSCR FR 1 FR0 to FR15 are assigned to FPR0_BANK1 to FPR15_BANK1 3 Double precision floating point registers or single precision floating point registers DRi 8 registers A DR register comprises two FR registers DR0 FR0 FR1 DR2 FR2 FR3 DR4 FR4 FR5 DR6 ...

Page 89: ...XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 DR0 DR2 DR4 DR6 DR8 DR10 DR12 DR14 FV0 FV4 FV8 FV12 XD0 XMTRX XD2 XD4 XD6 XD8 XD10 XD12 XD14 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1 XF0 XF1 XF2 XF3 X...

Page 90: ...rocessing mode 0 User mode Some instructions cannot be executed and some resources cannot be accessed 1 Privileged mode This bit is set to 1 by an exception or interrupt 29 RB 1 R W Privileged Mode General Register Bank Specification Bit 0 R0_BANK0 to R7_BANK0 are accessed as general registers R0 to R7 and R0_BANK1 to R7_BANK1 can be accessed using LDC STC instructions 1 R0_BANK1 to R7_BANK1 are a...

Page 91: ...ing this bit see General Precautions on Handling of Product 9 M 0 R W M Bit Used by the DIV0S DIV0U and DIV1 instructions 8 Q 0 R W Q Bit Used by the DIV0S DIV0U and DIV1 instructions 7 to 4 IMASK All 1 R W Interrupt Mask Level Bits An interrupt whose priority is equal to or less than the value of the IMASK bits is masked It can be chosen by CPU operation mode register CPUOPM whether the level of ...

Page 92: ...ng Saved General Register 15 SGR 32 bits Privileged Mode Initial Value Undefined The contents of R15 are saved to SGR in the event of an exception or interrupt Debug Base Register DBR 32 bits Privileged Mode Initial Value Undefined When the user break debugging function is enabled CBCR UBDE 1 DBR is referenced as the branch destination address of the user break handler instead of VBR 2 2 5 System ...

Page 93: ... Register Bank 0 FPR0_BANK0 to FPR15_BANK0 are assigned to FR0 to FR15 and FPR0_BANK1 to FPR15_BANK1 are assigned to XF0 to XF15 1 FPR0_BANK0 to FPR15_BANK0 are assigned to XF0 to XF15 and FPR0_BANK1 to FPR15_BANK1 are assigned to FR0 to FR15 20 SZ 0 R W Transfer Size Mode 0 Data size of FMOV instruction is 32 bits 1 Data size of FMOV instruction is a 32 bit register pair 64 bits For relationship ...

Page 94: ...ag Field Each time an FPU operation instruction is executed the FPU exception cause field is cleared to 0 When an FPU exception occurs the bits corresponding to FPU exception cause field and flag field are set to 1 The FPU exception flag field remains set to 1 until it is cleared to 0 by software For bit allocations of each field see table 2 2 1 0 RM 01 R W Rounding Mode These bits select the roun...

Page 95: ...r can not be used 2 The bit location of DR register is used for double precision format when PR 1 In the case of 2 it is used when PR is changed from 0 to 1 Figure 2 5 Relationship between SZ bit and Endian Table 2 2 Bit Allocation for FPU Exception Handling Field Name FPU Error E Invalid Operation V Division by Zero Z Overflow O Underflow U Inexact I Cause FPU exception cause field Bit 17 Bit 16 ...

Page 96: ...of the TLB enables access to a memory mapped register The operation of an access to this area without using the address translation function of the MMU is not guaranteed H FC00 0000 to H FFFF FFFF Access to area H FC00 0000 to H FFFF FFFF in user mode will cause an address error Memory mapped registers can be referenced in user mode by means of access that involves address translation Note Do not ...

Page 97: ...mats in Registers Register operands are always longwords 32 bits When a memory operand is only a byte 8 bits or a word 16 bits it is sign extended into a longword when loaded into a register 31 S S S 0 6 7 6 7 0 31 S S S 0 14 15 14 15 0 Figure 2 6 Formats of Byte Data and Word Data in Register ...

Page 98: ...dress Big endian or little endian byte order can be selected for the data format The endian should be set with the external pin after a power on reset The endian cannot be changed dynamically Bit positions are numbered left to right from most significant to least significant Thus in a 32 bit longword the leftmost bit bit 31 is the most significant bit and the rightmost bit bit 0 is the least signi...

Page 99: ...es are initialized For details see register descriptions for each section Instruction Execution State In this state the CPU executes program instructions in sequence The Instruction execution state has the normal program execution state and the exception handling state Power Down State In a power down state the CPU halts operation and power consumption is reduced The power down state is entered by...

Page 100: ... address within the range where no address error exception occurs 2 In case the modified codes are in cacheable area write through SYNCO ICBI Rn The all instruction cache area corresponding to the modified codes should be invalidated by the ICBI instruction The ICBI instruction should be issued to each cache line One cache line is 32 bytes 3 In case the modified codes are in cacheable area copy ba...

Page 101: ...r bit manipulation operations such as logical AND that are executed directly in memory operands in an operation that requires memory access are loaded into registers and the operation is executed between the registers Delayed Branches Except for the two branch instructions BF and BT this LSI s branch instructions and RTE are delayed branches In a delayed branch the instruction following the branch...

Page 102: ...ification and in data access the MD bit is accessed after modification The other bits S T M Q FD BL and RB after modification are used for delay slot instruction execution The STC and STC L SR instructions access all SR bits after modification Constant Values An 8 bit constant value can be specified by the instruction code and an immediate value 16 bit and 32 bit constant values can be defined as ...

Page 103: ...Rn Effective address is register Rn Operand is register Rn contents Register indirect Rn Effective address is register Rn contents Rn Rn Rn EA EA effective address Register indirect with post increment Rn Effective address is register Rn contents A constant is added to Rn after instruction execution 1 for a byte operand 2 for a word operand 4 for a longword operand 8 for a quadword operand Rn Rn 1...

Page 104: ... disp zero extended Byte Rn disp EA Word Rn disp 2 EA Longword Rn disp 4 EA Indexed register indirect R0 Rn Effective address is sum of register Rn and R0 contents Rn R0 Rn R0 Rn R0 EA GBR indirect with displace ment disp 8 GBR Effective address is register GBR contents with 8 bit displacement disp added After disp is zero extended it is multiplied by 1 byte 2 word or 4 longword according to the o...

Page 105: ...ero extended it is multiplied by 2 word or 4 longword according to the operand size With a longword operand the lower 2 bits of PC are masked PC H FFFF FFFC PC 4 disp 2 or PC H FFFF FFFC 4 disp 4 4 2 4 disp zero extended With longword operand Word PC 4 disp 2 EA Longword PC H FFFF FFFC 4 disp 4 EA PC relative disp 8 Effective address is PC 4 with 8 bit displacement disp added after being sign exte...

Page 106: ...T AND OR or XOR instruction is zero extended imm 8 8 bit immediate data imm of MOV ADD or CMP EQ instruction is sign extended imm 8 8 bit immediate data imm of TRAPA instruction is zero extended and multiplied by 4 Note For the addressing modes below that use a displacement disp the assembler descriptions in this manual show the value before scaling 1 2 or 4 is performed according to the operand s...

Page 107: ...m Immediate data disp Displacement Operation notation Transfer direction xx Memory operand M Q T SR flag bits Logical AND of individual bits Logical OR of individual bits Logical exclusive OR of individual bits Logical NOT of individual bits n n n bit shift Instruction code MSB LSB mmmm Register number Rm FRm nnnn Register number Rn FRn 0000 R0 FR0 0001 R1 FR1 1111 R15 FR15 mmm Register number DRm...

Page 108: ...tion Privileged mode Privileged means the instruction can only be executed in privileged mode T bit Value of T bit after instruction execution No change New New means the instruction which is newly added in this LSI Note Scaling 1 2 4 or 8 is executed according to the size of the instruction operand ...

Page 109: ...Rm Rn Rm Rn 0110nnnnmmmm0010 MOV B Rm Rn Rn 1 Rn Rm Rn 0010nnnnmmmm0100 MOV W Rm Rn Rn 2 Rn Rm Rn 0010nnnnmmmm0101 MOV L Rm Rn Rn 4 Rn Rm Rn 0010nnnnmmmm0110 MOV B Rm Rn Rm sign extension Rn Rm 1 Rm 0110nnnnmmmm0100 MOV W Rm Rn Rm sign extension Rn Rm 2 Rm 0110nnnnmmmm0101 MOV L Rm Rn Rm Rn Rm 4 Rm 0110nnnnmmmm0110 MOV B R0 disp Rn R0 disp Rn 10000000nnnndddd MOV W R0 disp Rn R0 disp 2 Rn 10000001...

Page 110: ...OV L disp GBR R0 disp 4 GBR R0 11000110dddddddd MOVA disp PC R0 disp 4 PC H FFFF FFFC 4 R0 11000111dddddddd MOVCO L R0 Rn LDST T If T 1 R0 Rn 0 LDST 0000nnnn01110011 LDST New MOVLI L Rm R0 1 LDST Rm R0 When interrupt exception occurred 0 LDST 0000mmmm01100011 New MOVUA L Rm R0 Rm R0 Load non boundary alignment data 0100mmmm10101001 New MOVUA L Rm R0 Rm R0 Rm 4 Rm Load non boundary alignment data 0...

Page 111: ...0 T 0011nnnnmmmm0010 Comparison result CMP GE Rm Rn When Rn Rm signed 1 T Otherwise 0 T 0011nnnnmmmm0011 Comparison result CMP HI Rm Rn When Rn Rm unsigned 1 T Otherwise 0 T 0011nnnnmmmm0110 Comparison result CMP GT Rm Rn When Rn Rm signed 1 T Otherwise 0 T 0011nnnnmmmm0111 Comparison result CMP PZ Rn When Rn 0 1 T Otherwise 0 T 0100nnnn00010001 Comparison result CMP PL Rn When Rn 0 1 T Otherwise ...

Page 112: ...mmmm1100 EXTU W Rm Rn Rm zero extended from word Rn 0110nnnnmmmm1101 MAC L Rm Rn Signed Rn Rm MAC MAC Rn 4 Rn Rm 4 Rm 32 32 64 64 bits 0000nnnnmmmm1111 MAC W Rm Rn Signed Rn Rm MAC MAC Rn 2 Rn Rm 2 Rm 16 16 64 64 bits 0100nnnnmmmm1111 MUL L Rm Rn Rn Rm MACL 32 32 32 bits 0000nnnnmmmm0111 MULS W Rm Rn Signed Rn Rm MACL 16 16 32 bits 0010nnnnmmmm1111 MULU W Rm Rn Unsigned Rn Rm MACL 16 16 32 bits 00...

Page 113: ...nnnmmmm1011 OR imm R0 R0 imm R0 11001011iiiiiiii OR B imm R0 GBR R0 GBR imm R0 GBR 11001111iiiiiiii TAS B Rn When Rn 0 1 T Otherwise 0 T In both cases 1 MSB of Rn 0100nnnn00011011 Test result TST Rm Rn Rn Rm when result 0 1 T Otherwise 0 T 0010nnnnmmmm1000 Test result TST imm R0 R0 imm when result 0 1 T Otherwise 0 T 11001000iiiiiiii Test result TST B imm R0 GBR R0 GBR imm when result 0 1 T Otherw...

Page 114: ...n00100101 LSB SHAD Rm Rn When Rm 0 Rn Rm Rn When Rm 0 Rn Rm MSB Rn 0100nnnnmmmm1100 SHAL Rn T Rn 0 0100nnnn00100000 MSB SHAR Rn MSB Rn T 0100nnnn00100001 LSB SHLD Rm Rn When Rm 0 Rn Rm Rn When Rm 0 Rn Rm 0 Rn 0100nnnnmmmm1101 SHLL Rn T Rn 0 0100nnnn00000000 MSB SHLR Rn 0 Rn T 0100nnnn00000001 LSB SHLL2 Rn Rn 2 Rn 0100nnnn00001000 SHLR2 Rn Rn 2 Rn 0100nnnn00001001 SHLL8 Rn Rn 8 Rn 0100nnnn00011000 ...

Page 115: ...BT label When T 1 disp 2 PC 4 PC When T 0 nop 10001001dddddddd BT S label Delayed branch when T 1 disp 2 PC 4 PC When T 0 nop 10001101dddddddd BRA label Delayed branch disp 2 PC 4 PC 1010dddddddddddd BRAF Rn Delayed branch Rn PC 4 PC 0000nnnn00100011 BSR label Delayed branch PC 4 PR disp 2 PC 4 PC 1011dddddddddddd BSRF Rn Delayed branch PC 4 PR Rn PC 4 PC 0000nnnn00000011 JMP Rn Delayed branch Rn ...

Page 116: ...ged LDC Rm Rn_BANK Rm Rn_BANK n 0 to 7 0100mmmm1nnn1110 Privileged LDC L Rm SR Rm SR Rm 4 Rm 0100mmmm00000111 Privileged LSB LDC L Rm GBR Rm GBR Rm 4 Rm 0100mmmm00010111 LDC L Rm VBR Rm VBR Rm 4 Rm 0100mmmm00100111 Privileged LDC L Rm SGR Rm SGR Rm 4 Rm 0100mmmm00110110 Privileged New LDC L Rm SSR Rm SSR Rm 4 Rm 0100mmmm00110111 Privileged LDC L Rm SPC Rm SPC Rm 4 Rm 0100mmmm01000111 Privileged LD...

Page 117: ...000010 Privileged STC GBR Rn GBR Rn 0000nnnn00010010 STC VBR Rn VBR Rn 0000nnnn00100010 Privileged STC SSR Rn SSR Rn 0000nnnn00110010 Privileged STC SPC Rn SPC Rn 0000nnnn01000010 Privileged STC SGR Rn SGR Rn 0000nnnn00111010 Privileged STC DBR Rn DBR Rn 0000nnnn11111010 Privileged STC Rm_BANK Rn Rm_BANK Rn m 0 to 7 0000nnnn1mmm0010 Privileged STC L SR Rn Rn 4 Rn SR Rn 0100nnnn00000011 Privileged ...

Page 118: ...01010 STS L MACH Rn Rn 4 Rn MACH Rn 0100nnnn00000010 STS L MACL Rn Rn 4 Rn MACL Rn 0100nnnn00010010 STS L PR Rn Rn 4 Rn PR Rn 0100nnnn00100010 SYNCO Prevents the next instruction from being issued until instructions issued before this instruction have been completed 0000000010101011 New TRAPA imm PC 2 SPC SR SSR imm 2 TRA H 160 EXPEVT VBR H 0100 PC 11000011iiiiiiii ...

Page 119: ... DRn 1111nnn0mmmm0110 FMOV Rm DRn Rm DRn Rm 8 Rm 1111nnn0mmmm1001 FMOV DRm Rn DRm Rn 1111nnnnmmm01010 FMOV DRm Rn Rn 8 Rn DRm Rn 1111nnnnmmm01011 FMOV DRm R0 Rn DRm R0 Rn 1111nnnnmmm00111 FLDS FRm FPUL FRm FPUL 1111mmmm00011101 FSTS FPUL FRn FPUL FRn 1111nnnn00001101 FABS FRn FRn H 7FFF FFFF FRn 1111nnnn01011101 FADD FRm FRn FRn FRm FRn 1111nnnnmmmm0000 FCMP EQ FRm FRn When FRn FRm 1 T Otherwise 0...

Page 120: ...PUL DRn float_to_ double FPUL DRn 1111nnn010101101 FLOAT FPUL DRn float FPUL DRn 1111nnn000101101 FMUL DRm DRn DRn DRm DRn 1111nnn0mmm00010 FNEG DRn DRn H 8000 0000 0000 0000 DRn 1111nnn001001101 FSQRT DRn DRn DRn 1111nnn001101101 FSUB DRm DRn DRn DRm DRn 1111nnn0mmm00001 FTRC DRm FPUL long DRm FPUL 1111mmm000111101 Table 3 12 Floating Point Control Instructions Instruction Operation Instruction C...

Page 121: ...1111nnn1mmmm1001 FMOV R0 Rm XDn R0 Rm XDn 1111nnn1mmmm0110 FMOV XDm Rn XDm Rn 1111nnnnmmm11010 FMOV XDm Rn Rn 8 Rn XDm Rn 1111nnnnmmm11011 FMOV XDm R0 Rn XDm R0 Rn 1111nnnnmmm10111 FIPR FVm FVn inner_product FVm FVn FR n 3 1111nnmm11101101 FTRV XMTRX FVn transform_vector XMTRX FVn FVn 1111nn0111111101 FRCHG FPSCR FR FPSCR FR 1111101111111101 FSCHG FPSCR SZ FPSCR SZ 1111001111111101 FPCHG FPSCR PR ...

Page 122: ...Section 3 Instruction Set Rev 1 00 Dec 13 2005 Page 72 of 1286 REJ09B0158 0100 ...

Page 123: ...Address calculation I1 I2 ID E1 E2 E3 WB 2 General Load Store Pipeline 3 Special Pipeline 4 Special Load Store Pipeline 5 Floating Point Pipeline 6 Floating Point Extended Pipeline Instruction fetch Instruction decode Issue Operation Write back Operation Operation Register read Forwarding I1 I2 ID FS1 FS2 FS4 FS3 FS Operation Instruction fetch Instruction decode Issue Register read Forwarding Oper...

Page 124: ...tation Description E1 E2 E3 WB CPU EX pipe is occupied S1 S2 S3 WB CPU LS pipe is occupied with memory access s1 s2 s3 WB CPU LS pipe is occupied without memory access E1 S1 Either CPU EX pipe or CPU LS pipe is occupied E1S1 E1s1 Both CPU EX pipe and CPU LS pipe are occupied M2 M3 MS CPU MULT operation unit is occupied FE1 FE2 FE3 FE4 FE5 FE6 FS FPU EX pipe is occupied FS1 FS2 FS3 FS4 FS FPU LS pi...

Page 125: ... issue cycles I1 ID I2 Branch destination instruction Branch destination instruction I1 ID I2 Branch destination instruction Note Note I1 I2 ID s1 s2 s3 WB E2s2 ID E3s3 ID WB ID I1 ID I2 E1s1 I1 I2 ID S1 S2 S3 WB E1s1 E3s3 E2s2 E1s1 E1s1 E1s1 E1s1 E2s2 E2s2 E2s2 E2s2 E3s3 E3s3 E3s3 E3s3 WB WB WB WB E2s2 E3s3 WB E2s2 E3s3 WB E1s1 E1s1 I1 ID I2 ID ID ID ID ID ID ID WB I1 I2 ID S1 S2 S3 WB E1s1 E2s2 ...

Page 126: ...3 E1 s1 E2 s2 E3 S3 WB 2 2 1 step operation LS type 1 issue cycle 2 3 1 step operation MT type 1 issue cycle 2 4 MOV MT type 1 issue cycle EXT SU BW MOVT SWAP XTRCT ADD CMP DIV DT NEG SUB AND AND NOT OR OR TST TST XOR XOR ROT SHA SHL CLRS CLRT SETS SETT MOV NOP MOVA MOV Note Except for AND OR TST and XOR instructions using GBR relative addressing mode Figure 4 2 Instruction Execution Patterns 2 ...

Page 127: ...REFI 5 issue cycles 5 cycles 3 branch cycle 3 8 MOVLI L 1 issue cycle I1 I2 ID S1 S2 S3 WB 3 9 MOVCO L 1 issue cycle I1 I2 ID S1 S2 S3 WB 3 10 MOVUA L 2 issue cycles I1 I2 ID S1 S2 S3 WB S1 S2 S3 WB Branch to the next instruction of ICBI E2S2 E3S3 WB E1S1 ID ID E2S2 E3S3 WB E1S1 E2S2 E3S3 WB E1S1 ID ID ID I1 I2 ID s1 s2 s3 WB E1s1 E1s1 E1s1 E2s2 E2s2 E2s2 E3s3 E3s3 E3s3 WB WB WB I1 ID I2 ID ID ID ...

Page 128: ...es ID ID ID I1 I2 ID s1 s2 s3 WB I1 I2 ID S1 S2 S3 WB 4 5 LDC L to Rp_BANK SSR SPC VBR 1 issue cycle I1 I2 ID E1s1 E2s2 E3s3 WB ID ID ID 4 6 LDC L to DBR SGR 4 issue cycles 4 7 LDC L to GBR 1 issue cycle I1 I2 ID S1 S2 S3 WB ID ID ID I1 I2 ID E1S1 E2S2 E3S3 WB ID ID ID ID ID I1 I2 ID S1 S2 S3 WB 4 8 LDC L to SR 6 issue cycles 3 branch cycles I1 ID I2 Branch to the next instruction Branch to the ne...

Page 129: ...LDS to PR 1 issue cycle I1 I2 ID WB I1 I2 ID S1 S2 S3 E1S1 E2S2 E3S3 WB I1 I2 ID s1 s2 s3 WB 4 14 LDS L to PR 1 issue cycle I1 I2 ID s1 s2 s3 WB 4 15 STS from PR 1 issue cycle I1 I2 ID S1 S2 S3 WB 4 16 STS L from PR 1 issue cycle I1 I2 ID 1 2 3 WB 4 17 BSRF BSR JSR delay slot instructions PR set 0 issue cycle The value of PR is changed in the E3 stage of delay slot instruction When the STS and STS...

Page 130: ...ycle I1 I2 ID E1 M2 M3 E1 M2 M3 MS E1 M2 M3 MS M2 M3 MS 5 5 MULS W MULU W 1 issue cycle 5 6 DMULS L DMULU L MUL L 1 issue cycle 5 7 CLRMAC 1 issue cycle I1 I2 ID I1 I2 ID S1 S2 S3 WB S1 S2 S3 WB I1 I2 ID 5 8 MAC W 2 issue cycle 5 9 MAC L 2 issue cycle I1 I2 ID s1 s2 s3 WB MS I1 I2 ID S1 S2 S3 WB MS I1 I2 ID S1 S2 S3 WB MS M2 M3 MS M2 M3 MS M2 M3 I1 I2 ID S1 S2 S3 WB S1 S2 S3 WB ID ID Figure 4 2 In...

Page 131: ... to FPUL 1 issue cycle 6 4 STS L from FPUL 1 issue cycle 6 5 LDS to FPSCR 1 issue cycle 6 6 STS from FPSCR 1 issue cycle 6 7 LDS L to FPSCR 1 issue cycle 6 8 STS L from FPSCR 1 issue cycle 6 9 FPU load store instruction FMOV 1 issue cycle I1 I2 ID I1 I2 ID S1 S2 S3 WB S1 S2 S3 S1 S2 S3 WB I1 I2 ID s1 s2 s3 I1 I2 ID WB S1 S2 S3 WB FS3 S1 S2 S3 WB FS1 FS2 FS3 FS4 FS s1 s2 s3 WB I1 I2 ID 6 10 FLDS 1 ...

Page 132: ...nt computation 1 issue cycle 6 18 Double precision FDIV FSQRT 1 issue cycle I1 I2 ID s1 s2 s3 FS1 FS2 FS3 FS4 I1 I2 ID FE1 FE2 FE3 FE4 FE5 FE6 FS FEDS Divider occupied cycle FS FCMP EQ FCMP GT FADD FLOAT FMAC FMUL FSUB FTRC FRCHG FSCHG FPCHG FCMP EQ FCMP GT FADD FLOAT FSUB FTRC FCNVSD FCNVDS FMUL FEDS Divider occupied cycle I1 I2 ID FE1 FE2 FE3 FE4 FE5 FE6 FS I1 I2 ID FE1 FE2 FE3 FE4 FE5 FE6 FS FE...

Page 133: ...unit occupied cycle Function computing unit occupied cycle I1 I2 ID FE1 FE2 FE3 FE4 FE5 FE6 FS I1 I2 ID FE1 FE2 FE1 FE2 FE3 FE4 FE5 FE6 FS FE3 FE4 FE5 FE6 FS FE1 FE2 FE3 FE4 FE5 FE6 FS FE1 FE2 FE3 FE4 FE5 FE6 FS I1 I2 ID FE1 FE2 FE3 FEPL FE4 FE5 FE6 FS FEPL I1 I2 ID FE1 FE2 FE1 FE2 FE3 FE4 FE5 FE6 FS FE3 FE4 FE5 FE6 FS FE1 FE2 FE3 FE4 FE5 FE6 FS Figure 4 2 Instruction Execution Patterns 9 ...

Page 134: ...MAC CLRS CLRT CMP DIV0S DIV0U DIV1 DMUS L DMULU L DT EXTS EXTU MOVT MUL L MULS W MULU W NEG NEGC NOT OR imm R0 OR Rm Rn ROTCL ROTCR ROTL ROTR SETS SETT SHAD SHAL SHAR SHLD SHLL SHLL2 SHLL8 SHLL16 SHLR SHLR2 SHLR8 SHLR16 SUB SUBC SUBV SWAP TST imm R0 TST Rm Rn XOR imm R0 XOR Rm Rn XTRCT MT MOV imm Rn MOV Rm Rn NOP BR BF BF S BRA BRAF BSR BSRF BT BT S JMP JSR RTS LS FABS FNEG FLDI0 FLDI1 FLDS FMOV a...

Page 135: ...Address SR1 MACH MACL PR SR2 FPUL FPSCR CR1 GBR Rp_BANK SPC SSR VBR CR2 CR1 DBR SGR FR FRm FRn DRm DRn XDm XDn The parallel execution of two instructions can be carried out under following conditions 1 Both addr preceding instruction and addr 2 following instruction are specified within the minimum page size 1 Kbyte 2 The execution of these two instructions is supported in table 4 3 Combination of...

Page 136: ...I It is different from table 4 3 Preceding Instruction addr EX MT BR LS FLSR FLSM FE CO EX No Yes Yes Yes Yes Yes Yes No MT Yes Yes Yes Yes Yes Yes Yes No Following Instruction addr 2 BR Yes Yes No Yes Yes Yes Yes No LS Yes Yes Yes No Yes No Yes No FLSR Yes Yes Yes Yes No No No No FLSM Yes Yes Yes No No No Yes No FE Yes Yes Yes Yes No Yes No No CO No No No No No No No No Legend FLSR FABS FNEG FLDI...

Page 137: ...ion E1S1 I1 I2 ID S1 S2 S3 WB MS S2 S3 WB S1 ID ID ID I1 ID I2 Next instruction M3 M2 Issue rate 2 I1 ID I2 E g MAC W instruction Execution cycles indicates the cycle counts an instruction occupied the pipeline based on the next rules CPU instruction E g AND B instruction I1 I2 ID S1 S2 S3 WB Execution Cycles 3 E2S2 E3S3 WB E1S1 ID ID I1 I2 ID S1 S2 S3 WB MS S2 S3 WB S1 ID M3 M2 E g MAC W instruct...

Page 138: ... 3 1 9 MOV L disp PC Rn LS 1 1 3 1 10 MOV B Rm Rn LS 1 1 3 1 11 MOV W Rm Rn LS 1 1 3 1 12 MOV L Rm Rn LS 1 1 3 1 13 MOV B Rm Rn LS 1 1 3 1 14 MOV W Rm Rn LS 1 1 3 1 15 MOV L Rm Rn LS 1 1 3 1 16 MOV B disp Rm R0 LS 1 1 3 1 17 MOV W disp Rm R0 LS 1 1 3 1 18 MOV L disp Rm Rn LS 1 1 3 1 19 MOV B R0 Rm Rn LS 1 1 3 1 20 MOV W R0 Rm Rn LS 1 1 3 1 21 MOV L R0 Rm Rn LS 1 1 3 1 22 MOV B disp GBR R0 LS 1 1 3...

Page 139: ... 3 1 39 MOV L R0 disp GBR LS 1 1 3 1 40 MOVCA L R0 Rn LS 1 1 3 4 41 MOVCO L R0 Rn CO 1 1 3 9 42 MOVLI L Rm R0 CO 1 1 3 8 43 MOVUA L Rm R0 LS 2 2 3 10 44 MOVUA L Rm R0 LS 2 2 3 10 45 MOVT Rn EX 1 1 2 1 46 OCBI Rn LS 1 1 3 4 47 OCBP Rn LS 1 1 3 4 48 OCBWB Rn LS 1 1 3 4 49 PREF Rn LS 1 1 3 4 50 SWAP B Rm Rn EX 1 1 2 1 51 SWAP W Rm Rn EX 1 1 2 1 Data transfer instructions 52 XTRCT Rm Rn EX 1 1 2 1 53 ...

Page 140: ...MULU L Rm Rn EX 1 2 5 6 71 DT Rn EX 1 1 2 1 72 MAC L Rm Rn CO 2 5 5 9 73 MAC W Rm Rn CO 2 4 5 8 74 MUL L Rm Rn EX 1 2 5 6 75 MULS W Rm Rn EX 1 1 5 5 76 MULU W Rm Rn EX 1 1 5 5 77 NEG Rm Rn EX 1 1 2 1 78 NEGC Rm Rn EX 1 1 2 1 79 SUB Rm Rn EX 1 1 2 1 80 SUBC Rm Rn EX 1 1 2 1 Fixed point arithmetic instructions 81 SUBV Rm Rn EX 1 1 2 1 82 AND Rm Rn EX 1 1 2 1 83 AND imm R0 EX 1 1 2 1 84 AND B imm R0 ...

Page 141: ... 2 1 101 SHAL Rn EX 1 1 2 1 102 SHAR Rn EX 1 1 2 1 103 SHLD Rm Rn EX 1 1 2 1 104 SHLL Rn EX 1 1 2 1 105 SHLL2 Rn EX 1 1 2 1 106 SHLL8 Rn EX 1 1 2 1 107 SHLL16 Rn EX 1 1 2 1 108 SHLR Rn EX 1 1 2 1 109 SHLR2 Rn EX 1 1 2 1 110 SHLR8 Rn EX 1 1 2 1 Shift instructions 111 SHLR16 Rn EX 1 1 2 1 112 BF disp BR 1 0 to 2 1 1 1 113 BF S disp BR 1 0 to 2 1 1 1 114 BT disp BR 1 0 to 2 1 1 1 115 BT S disp BR 1 0...

Page 142: ...1 13 1 5 133 RTE CO 4 1 4 1 4 134 SLEEP CO Undefined Undefined 1 6 135 LDTLB CO 1 1 3 5 136 LDC Rm DBR CO 4 4 4 2 137 LDC Rm SGR CO 4 4 4 2 138 LDC Rm GBR LS 1 1 4 3 139 LDC Rm Rp_BANK LS 1 1 4 1 140 LDC Rm SR CO 4 3 4 4 4 141 LDC Rm SSR LS 1 1 4 1 142 LDC Rm SPC LS 1 1 4 1 143 LDC Rm VBR LS 1 1 4 1 144 LDC L Rm DBR CO 4 4 4 6 145 LDC L Rm SGR CO 4 4 4 6 146 LDC L Rm GBR LS 1 1 4 7 147 LDC L Rm Rp...

Page 143: ...SPC Rn LS 1 1 4 9 165 STC VBR Rn LS 1 1 4 9 166 STC L DBR Rn LS 1 1 4 11 167 STC L SGR Rn LS 1 1 4 11 168 STC L GBR Rn LS 1 1 4 11 169 STC L Rp_BANK Rn LS 1 1 4 11 170 STC L SR Rn CO 1 1 4 12 171 STC L SSR Rn LS 1 1 4 11 172 STC L SPC Rn LS 1 1 4 11 173 STC L VBR Rn LS 1 1 4 11 174 STS MACH Rn LS 1 1 5 3 175 STS MACL Rn LS 1 1 5 3 176 STS PR Rn LS 1 1 4 15 177 STS L MACH Rn LS 1 1 5 4 178 STS L MA...

Page 144: ...FRn FE 1 14 6 15 196 FLOAT FPUL FRn FE 1 1 6 14 197 FMAC FR0 FRm FRn FE 1 1 6 14 198 FMUL FRm FRn FE 1 1 6 14 199 FNEG FRn LS 1 1 6 12 200 FSQRT FRn FE 1 30 6 15 201 FSUB FRm FRn FE 1 1 6 14 202 FTRC FRm FPUL FE 1 1 6 14 203 FMOV DRm DRn LS 1 1 6 9 204 FMOV Rm DRn LS 1 1 6 9 205 FMOV Rm DRn LS 1 1 6 9 206 FMOV R0 Rm DRn LS 1 1 6 9 207 FMOV DRm Rn LS 1 1 6 9 208 FMOV DRm Rn LS 1 1 6 9 Single precis...

Page 145: ... 225 LDS L Rm FPUL LS 1 1 6 3 226 LDS L Rm FPSCR LS 1 1 6 7 227 STS FPUL Rn LS 1 1 6 2 228 STS FPSCR Rn LS 1 1 6 6 229 STS L FPUL Rn LS 1 1 6 4 FPU system control instructions 230 STS L FPSCR Rn LS 1 1 6 8 231 FMOV DRm XDn LS 1 1 6 9 232 FMOV XDm DRn LS 1 1 6 9 233 FMOV XDm XDn LS 1 1 6 9 234 FMOV Rm XDn LS 1 1 6 9 235 FMOV Rm XDn LS 1 1 6 9 236 FMOV R0 Rm XDn LS 1 1 6 9 237 FMOV XDm Rn LS 1 1 6 9...

Page 146: ...Section 4 Pipelining Rev 1 00 Dec 13 2005 Page 96 of 1286 REJ09B0158 0100 ...

Page 147: ...xception handling in this LSI is of three kinds resets general exceptions and interrupts 5 2 Register Descriptions Table 5 1 lists the configuration of registers related exception handling Table 5 1 Register Configuration Register Name Abbreviation R W P4 Address Area 7 Address Access Size TRAPA exception register TRA R W H FF00 0020 H 1F00 0020 32 Exception event register EXPEVT R W H FF00 0024 H...

Page 148: ... 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value R R R R R R R R R R R R R R R R R W R W R W TRACODE R W R W R W R R R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 R R R R R R R W R W Bit Bit Name Initial Value R W Description 31 to 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 to 2 TRACODE Undefined...

Page 149: ...d by software 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Initial value R R R R R R R R R R R R R R R R R W R W EXPCODE R W R W R W R W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 R R R R R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 12 All 0 R Reserved These bits are always rea...

Page 150: ... 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value R R R R R R R R R R R R R R R R R W INTCODE R W R W R W R W R W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 R R R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 14 All 0 R Reserved These bits are always read as 0 The write value should always be 0 ...

Page 151: ... Programming Model 1 The PC SR and R15 contents are saved in SPC SSR and SGR respectively 2 The block bit BL in SR is set to 1 3 The mode bit MD in SR is set to 1 4 The register bank bit RB in SR is set to 1 5 In a reset the FPU disable bit FD in SR is cleared to 0 6 The exception code is written to bits 11 to 0 of the exception event register EXPEVT or interrupt event register INTEVT 7 The CPU br...

Page 152: ...re instruction execution 1 2 0 VBR DBR H 100 H 1E0 Instruction address error 2 1 VBR H 100 H 0E0 Instruction TLB miss exception 2 2 VBR H 400 H 040 Instruction TLB protection violation exception 2 3 VBR H 100 H 0A0 General illegal instruction exception 2 4 VBR H 100 H 180 Slot illegal instruction exception 2 4 VBR H 100 H 1A0 General FPU disable exception 2 4 VBR H 100 H 800 Slot FPU disable excep...

Page 153: ...ak after instruction execution 1 2 10 VBR DBR H 100 H 1E0 Nonmaskable interrupt 3 VBR H 600 H 1C0 Interrupt Completion type General interrupt request 4 VBR H 600 Notes 1 When UBDE in CBCR 1 PC DBR In other cases PC VBR H 100 2 Priority is first assigned by priority level then by priority order within each level the lowest number represents the highest priority 3 Control passes to H A000 0000 in a ...

Page 154: ...ive priority order of the different kinds of exceptions reset general exception and interrupt Register settings in the event of an exception are shown only for SSR SPC SGR EXPEVT INTEVT SR and PC However other registers may be set automatically by hardware depending on the exception For details see section 5 6 Description of Exceptions Also see section 5 6 4 Priority Order with Multiple Exceptions...

Page 155: ... SGR R15 EXPEVT INTEVT exception code SR MD RB BL 111 SR IMASK received interuupt level PC CBCR UBDE 1 User_Break DBR VBR Offset Interrupt requested General exception requested Reset requested EXPEVT exception code SR MD RB BL FD IMASK 11101111 PC H A000 0000 Note When the exception of the highest priority is an interrupt Whether IMASK is updated or not can be set by software Figure 5 1 Instructio...

Page 156: ... an earlier instruction is accepted before that for a later instruction An example of the order of acceptance for general exceptions is shown in figure 5 2 I1 I1 ID ID E3 WB WB TLB miss data access Pipeline flow Order of detection Instruction n Instruction n 1 General illegal instruction exception instruction n 1 and TLB miss instruction n 2 are detected simultaneously Order of exception handling ...

Page 157: ...e interrupt request is held pending and is accepted after the BL bit has been cleared to 0 by software If a nonmaskable interrupt NMI occurs it can be held pending or accepted according to the setting made by software Thus normally SPC and SSR are saved and then the BL bit in SR is cleared to 0 to enable multiple exception state acceptance 5 5 4 Return from Exception Handling The RTE instruction i...

Page 158: ...ons A power on reset should be executed when power is supplied Manual Reset Condition Manual reset request Operations Exception code H 020 is set in EXPEVT initialization of the CPU and on chip peripheral module is carried out and then a branch is made to the branch vector H A0000000 The registers initialized by a power on reset and manual reset are different For details see the register descripti...

Page 159: ...pheral module initialization is performed in the same way as in a manual reset For details see the register descriptions in the relevant sections Data TLB Multiple Hit Exception Source Multiple UTLB address matches Transition address H A0000000 Transition operations The virtual address 32 bits at which this exception occurred is set in TEA and the corresponding virtual page number 22 bits is set i...

Page 160: ... the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 040 for a read access or H 060 for a write access is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0400 To speed up TLB miss processing the offset is sepa...

Page 161: ...31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 40 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0400 To speed up TLB miss processing the offset is separate from that of o...

Page 162: ...rtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 080 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Initial_write_exception TEA...

Page 163: ...s The virtual address 32 bits at which this exception occurred is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 0A0 for a read access or H...

Page 164: ... at which this exception occurred is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 0A0 is set in EXPEVT The BL MD and RB bits are set to 1...

Page 165: ...ss VBR H 0000100 Transition operations The virtual address 32 bits at which this exception occurred is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Except...

Page 166: ...ption occurred is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in the SPC and SSR The R15 contents at this time are saved in SGR Exception code H 0E0 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a br...

Page 167: ...ruction following the TRAPA instruction are saved in SPC The value of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR The 8 bit immediate value in the TRAPA instruction is multiplied by 4 and the result is set in TRA 9 0 Exception code H 160 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 TRAPA_exception SPC PC 2 SSR SR SGR...

Page 168: ...C RTE LDTLB SLEEP but excluding LDC STC instructions that access GBR Transition address VBR H 00000100 Transition operations The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 180 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Operation ...

Page 169: ...elay slot Privileged instructions LDC STC RTE LDTLB SLEEP but excluding LDC STC instructions that access GBR Decoding of a PC relative MOV instruction or MOVA instruction in a delay slot Transition address VBR H 000 0100 Transition operations The PC contents for the preceding delayed branch instruction are saved in SPC The SR and R15 contents when this exception occurred are saved in SSR and SGR E...

Page 170: ...are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 800 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Note FPU instructions are instructions in which the first 4 bits of the instruction code are F but excluding undefined instruction H FFFD and the LDS STS LDS L and STS L instructions corresponding to FPUL and FP...

Page 171: ...00 Transition operations The PC contents for the preceding delayed branch instruction are saved in SPC The SR and R15 contents when this exception occurred are saved in SSR and SGR Exception code H 820 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Slot_fpu_disable_exception SPC PC 2 SSR SR SGR R15 EXPEVT H 0000 0820 SR MD 1 SR RB 1 SR BL 1 PC VBR H...

Page 172: ...t are set in SPC In the case of a pre execution break the PC contents for the instruction at which the breakpoint is set are set in SPC The SR and R15 contents when the break occurred are saved in SSR and SGR Exception code H 1E0 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 It is also possible to branch to PC DBR For details of PC etc when a data ...

Page 173: ...00100 Transition operations The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 120 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 FPU_exception SPC PC SSR SR SGR R15 EXPEVT H 0000 0120 SR MD 1 SR RB 1 SR BL 1 PC VBR H 0000 0100 ...

Page 174: ... in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 1C0 is set in INTEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0600 When the BL bit in SR is 0 this interrupt is not masked by the interrupt mask bits in SR and is accepted at the highest priority level When the BL bit in SR is 1 a software setting can specify whether this interrupt is t...

Page 175: ...cceptance are set in SSR and SGR The code corresponding to the each interrupt source is set in INTEVT The BL MD and RB bits are set to 1 in SR and a branch is made to VBR H 0600 Module_interruption SPC PC SSR SR SGR R15 INTEVT H 0000 0400 H 0000 3FE0 SR MD 1 SR RB 1 SR BL 1 if cond SR IMASK level_of accepted_interrupt PC VBR H 0000 0600 5 6 4 Priority Order with Multiple Exceptions With some instr...

Page 176: ...ere the delay slot instruction has only one data transfer 1 A check is performed for the interrupt type and re execution type exceptions of priority levels 1 and 2 in the delayed branch instruction 2 A check is performed for the interrupt type and re execution type exceptions of priority levels 1 and 2 in the delay slot instruction 3 A check is performed for the completion type exception of priori...

Page 177: ...PC value for the instruction at which the exception occurred is set in SPC and the instruction is re executed after returning from the exception handling routine If an exception occurs in a delay slot instruction however the PC value for the delayed branch instruction is saved in SPC regardless of whether or not the preceding delay slot instruction condition is satisfied B Completion type exceptio...

Page 178: ...tion is determined by the changed SR value starting from the next instruction In the completion type exception an exception is accepted after the next instruction has been executed However an interrupt of completion type exception is accepted before the next instruction is executed Note When the LDC instruction for SR is executed following instructions are fetched again and the instruction fetch e...

Page 179: ...nd to Zero Two denormalization modes Flush to Zero and Treat Denormalized Number Six exception sources FPU Error Invalid Operation Divide By Zero Overflow Underflow and Inexact Comprehensive instructions Single precision double precision graphics support and system control Following three instructions are added in the SH 4A FSRRA FSCA and FPCHG When the FD bit in SR is set to 1 the FPU cannot be u...

Page 180: ...res 6 1 and 6 2 31 s e f 30 23 22 0 Figure 6 1 Format of Single Precision Floating Point Number 63 s e f 62 52 51 0 Figure 6 2 Format of Double Precision Floating Point Number The exponent is expressed in biased form as follows e E bias The range of unbiased exponent E is Emin 1 to Emax 1 The two values Emin 1 and Emax 1 are distinguished as follows Emin 1 indicates zero both positive and negative...

Page 181: ...22 Floating point number value v is determined as follows If E Emax 1 and f 0 v is a non number NaN irrespective of sign s If E Emax 1 and f 0 v 1 s infinity positive or negative infinity If Emin E Emax v 1 s 2E 1 f normalized number If E Emin 1 and f 0 v 1 s 2Emin 0 f denormalized number If E Emin 1 and f 0 v 1 s 0 positive or negative zero Table 6 2 shows the ranges of the various numbers in hex...

Page 182: ...FFFF to H 0010 0000 0000 0000 Positive denormalized number H 007F FFFF to H 0000 0001 H 000F FFFF FFFF FFFF to H 0000 0000 0000 0001 Positive zero H 0000 0000 H 0000 0000 0000 0000 Negative zero H 8000 0000 H 8000 0000 0000 0000 Negative denormalized number H 8000 0001 to H 807F FFFF H 8000 0000 0000 0001 to H 800F FFFF FFFF FFFF Negative normalized number H 8080 0000 to H FF7F FFFF H 8010 0000 00...

Page 183: ... registers FABS and FNEG that generates a floating point value When the EN V bit in FPSCR is 0 the operation result output is a qNaN When the EN V bit in FPSCR is 1 an invalid operation exception will be generated In this case the contents of the operation destination register are unchanged Following three instructions are used as transfer instructions between registers FMOV FRm FRn FLDS FRm FPUL ...

Page 184: ...action field as a non zero value When the DN bit in FPSCR of the FPU is 1 a denormalized number source operand or operation result is always positive or negative zero in a floating point operation that generates a value an operation other than transfer instructions between registers FNEG or FABS When the DN bit in FPSCR is 0 a denormalized number source operand or operation result is processed as ...

Page 185: ...n FPSCR FR 0 FR0 to FR15 are allocated to FPR0_BANK0 to FPR15_BANK0 when FPSCR FR 1 FR0 to FR15 are allocated to FPR0_BANK1 to FPR15_BANK1 3 Double precision floating point registers DRi 8 registers A DR register comprises two FR registers DR0 FR0 FR1 DR2 FR2 FR3 DR4 FR4 FR5 DR6 FR6 FR7 DR8 FR8 FR9 DR10 FR10 FR11 DR12 FR12 FR13 DR14 FR14 FR15 4 Single precision floating point vector registers FVi ...

Page 186: ...XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 DR0 DR2 DR4 DR6 DR8 DR10 DR12 DR14 FV0 FV4 FV8 FV12 XD0 XMTRX XD2 XD4 XD6 XD8 XD10 XD12 XD14 FPR0 BANK1 FPR1 BANK1 FPR2 BANK1 FPR3 BANK1 FPR4 BANK1 FPR5 BANK1 FPR6 BANK1 FPR7 BANK1 FPR8 BANK1 FPR9 BANK1 FPR10 BANK1 FPR11 BANK1 FPR12 BANK1 FPR13 BANK1 FPR14 BANK1 FPR15 BANK1 XF0 XF1 XF2 X...

Page 187: ...egister Bank 0 FPR0_BANK0 to FPR15_BANK0 are assigned to FR0 to FR15 and FPR0_BANK1 to FPR15_BANK1 are assigned to XF0 to XF15 1 FPR0_BANK0 to FPR15_BANK0 are assigned to XF0 to XF15 and FPR0_BANK1 to FPR15_BANK1 are assigned to FR0 to FR15 20 SZ 0 R W Transfer Size Mode 0 Data size of FMOV instruction is 32 bits 1 Data size of FMOV instruction is a 32 bit register pair 64 bits For relations betwe...

Page 188: ...Field Each time an FPU operation instruction is executed the FPU exception cause field is cleared to 0 When an FPU exception occurs the bits corresponding to FPU exception cause field and flag field are set to 1 The FPU exception flag field remains set to 1 until it is cleared to 0 by software For bit allocations of each field see table 6 3 1 0 RM1 RM0 0 1 R W R W Rounding Mode These bits select t...

Page 189: ... 2i FR 2i 1 4n 4m 4n 3 4m 3 63 0 63 32 31 0 DR 2i FR 2i 1 FR 2i 8n 4 8n 7 8n 3 8n 63 0 63 32 31 0 1 SZ 0 2 SZ 1 PR 0 63 0 63 0 DR 2i FR 2i 1 FR 2i 8n 8n 3 8n 7 8n 4 63 0 63 32 31 0 3 SZ 1 PR 1 63 0 1 2 2 Notes 1 In the case of SZ 0 and PR 0 DR register can not be used 2 The bit location of DR register is used for double precision format when PR 1 In the case of 2 it is used when PR is changed from...

Page 190: ...nable field None Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Flag FPU exception flag field None Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 6 3 3 Floating Point Communication Register FPUL Information is transferred between the FPU and CPU via FPUL FPUL is a 32 bit system register that is accessed from the CPU side by means of LDS and STS instructions For example to convert the integer stored in general register R1 to a si...

Page 191: ...M bits in FPSCR FPSCR RM 1 0 00 Round to Nearest FPSCR RM 1 0 01 Round to Zero Round to Nearest The operation result is rounded to the nearest expressible value If there are two nearest expressible values the one with an LSB of 0 is selected If the unrounded value is 2Emax 2 2 P or more the result will be infinity with the same sign as the unrounded value The values of Emax and P respectively are ...

Page 192: ...erflow or rounding occurs The FPU exception cause field in FPSCR contains bits corresponding to all of above sources E V Z O U and I and the FPU exception flag and enable fields in FPSCR contain bits corresponding to sources V Z O U and I but not E Thus FPU errors cannot be disabled When an FPU exception occurs the corresponding bit in the FPU exception cause field is set to 1 and 1 is added to th...

Page 193: ... exception sources except for above are generated the bit corresponding to source V Z O U or I is set to 1 and a default value is generated as the operation result Invalid operation V qNaN is generated as the result Division by zero Z Infinity with the same sign as the unrounded value is generated Overflow O When rounding mode RZ the maximum normalized number with the same sign as the unrounded va...

Page 194: ...os in the fractional part In a future version of the SH Series the above error is guaranteed but the same result between different processor cores is not guaranteed FIPR FVm FVn m n 0 4 8 12 This instruction is basically used for the following purposes Inner product m n This operation is generally used for surface rear surface determination for polygon surfaces Sum of square of elements m n This o...

Page 195: ...rray in the background bank However to create the actual elements of a translation matrix it is easier to use registers in the foreground bank When the LDS instruction is used on FPSCR this instruction takes four to five cycles in order to maintain the FPU state With the FRCHG instruction the FR bit in FPSCR can be changed in one cycle 6 6 2 Pair Single Precision Data Transfer In addition to the p...

Page 196: ...Section 6 Floating Point Unit FPU Rev 1 00 Dec 13 2005 Page 146 of 1286 REJ09B0158 0100 ...

Page 197: ...sion arises 1 in figure 7 1 Having this mapping onto physical memory executed consciously by the process itself imposes a heavy burden on the process The virtual memory system was devised as a means of handling all physical memory mapping to reduce this burden 2 in figure 7 1 With a virtual memory system the size of the available virtual memory is much larger than the actual physical memory and pr...

Page 198: ...on lookaside buffer TLB is provided by hardware and frequently used address translation information is placed here The TLB can be described as a cache for address translation information However unlike a cache if address translation fails that is if an exception occurs switching of the address translation information is normally performed by software Thus memory management can be performed in a fl...

Page 199: ...eged mode the 4 Gbyte space from the P0 area to the P4 area can be accessed In user mode a 2 Gbyte space in the U0 area can be accessed When the SQMD bit in the MMU control register MMUCR is 0 a 64 Mbyte space in the store queue area can be accessed When the RMD bit in the on chip memory control register RAMCR is 1 a 16 Mbyte space in on chip memory area can be accessed Accessing areas other than ...

Page 200: ...00 0000 H E600 0000 H FFFF FFFF H 0000 0000 H 8000 0000 H FFFF FFFF H A000 0000 H C000 0000 H E000 0000 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 Physical address space Address error Address error Address error On chip memory area Store queue area User mode Privileged mode P1 area Cacheable P0 area Cacheable P2 area Non cacheable P3 area Cacheable P4 area Non cacheable U0 area Cachea...

Page 201: ...queue area P0 area Cacheable Address translation possible User mode Privileged mode P1 area Cacheable Address translation not possible P2 area Non cacheable Address translation not possible P3 area Cacheable Address translation possible P4 area Non cacheable Address translation not possible H 0000 0000 H 8000 0000 H E000 0000 H E400 0000 H E500 0000 H E600 0000 H FFFF FFFF H FFFF FFFF H 0000 0000 ...

Page 202: ...When the P0 P3 and U0 areas are mapped onto the control register area which is allocated in the area 7 in physical address space by means of the TLB the C bit for the corresponding page must be cleared to 0 P1 Area The P1 area does not allow address translation using the TLB but can be accessed using the cache Regardless of whether the MMU is enabled or disabled clearing the upper 3 bits of an add...

Page 203: ...ueues SQs In user mode the access right is specified by the SQMD bit in MMUCR For details see section 8 7 Store Queues The area from H E500 0000 to H E5FF FFFF comprises addresses for accessing the on chip memory In user mode the access right is specified by the RMD bit in RAMCR For details see section 9 L Memory The area from H F000 0000 to H F0FF FFFF is used for direct access to the instruction...

Page 204: ...ction 7 7 5 Memory Mapped PMB Configuration The area from H F710 0000 to H F71F FFFF is used for direct access to the PMB data array For details see section 7 7 5 Memory Mapped PMB Configuration The area from H FC00 0000 to H FFFF FFFF is the on chip peripheral module control register area For details see register descriptions in each section Physical Address Space This LSI supports a 29 bit physi...

Page 205: ...recorded in the TLB After the return from the exception handling routine the instruction which caused the TLB miss exception is re executed Single Virtual Memory Mode and Multiple Virtual Memory Mode There are two virtual memory systems single virtual memory and multiple virtual memory either of which can be selected with the SV bit in MMUCR In the single virtual memory system a number of processe...

Page 206: ...H 1F00 0070 32 Instruction re fetch inhibit control register IRMCR R W H FF00 0078 H 1F00 0078 32 Note These P4 addresses are for the P4 area in the virtual address space These area 7 addresses are accessed from area 7 in the physical address space by means of the TLB Table 7 2 Register States in Each Processing State Register Name Abbreviation Power on Reset Manual Reset Sleep Page table entry hi...

Page 207: ...e an access including an instruction fetch to the P0 P3 or U0 area that uses the updated ASID value is performed 1 Execute a branch using the RTE instruction In this case the branch destination may be the P0 P3 or U0 area 2 Execute the ICBI instruction for any address including non cacheable area 3 If the R2 bit in IRMCR is 0 initial value before updating the ASID field the specific instruction do...

Page 208: ... of the LDTLB instruction The contents of this register are not changed unless a software directive is issued 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 Initial value R R R R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W PPN PPN V SZ1 PR1 PR0 SZ0 C D SH WT R W R W R W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R W R W R W R W R W R W ...

Page 209: ...0 19 18 17 16 Bit Initial value R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W TTB TTB R W R W R W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W 7 2 4 TLB Exception Address Register TEA After an MMU exception or address error exception occurs the virtual address at which the exception occurred is stored The cont...

Page 210: ...ore updating MMUCR the specific instruction does not need to be executed However note that the CPU processing performance will be lowered because the instruction fetch is performed again for the next instruction after MMUCR has been updated Note that the method 3 may not be guaranteed in the future SuperH Series Therefore it is recommended that the method 1 or 2 should be used for being compatible...

Page 211: ... entry 3 is used XXXXXX Other than above When the LRUI bit settings are as shown below the corresponding ITLB entry is updated by an ITLB miss Ensure that values for which Setting prohibited is indicated below are not set at the discretion of software After a power on or manual reset the LRUI bits are initialized to 0 and therefore a prohibited setting is never made by a hardware update X means do...

Page 212: ...re which results in the condition of URC URB incrementing is first performed in excess of URB until URC H 3F URC is not incremented by an LDTLB instruction 9 SQMD 0 R W Store Queue Mode Bit Specifies the right of access to the store queues 0 User privileged access possible 1 Privileged access possible address error exception in case of user access 8 SV 0 R W Single Virtual Memory Mode Multiple Vir...

Page 213: ...ption 1 0 R Reserved This bit is always read as 0 The write value should always be 0 0 AT 0 R W Address Translation Enable Bit These bits enable or disable the MMU 0 MMU disabled 1 MMU enabled MMU exceptions are not generated when the AT bit is 0 In the case of software that does not use the MMU the AT bit should be cleared to 0 ...

Page 214: ...ed These bits are always read as 0 The write value should always be 0 7 to 0 UB All 0 R W Buffered Write Control for Each Area 64 Mbytes When writing is performed without using the cache or in the cache write through mode these bits specify whether the next bus access from the CPU waits for the end of writing for each area 0 The CPU does not wait for the end of writing bus access and starts the ne...

Page 215: ...of the program which uses changed resources For details on the specific sequence see descriptions in each resource 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value R R R R R R R R R R R R R R R R R R2 R1 LT MT MC R R R W R W R W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R Bi...

Page 216: ...etch is not performed 1 MT 0 R W Re Fetch Inhibit after Writing Memory Mapped TLB This bit controls whether re fetch is performed for the next instruction after writing memory mapped ITLB UTLB while the AT bit in MMUCR is set to 1 0 Re fetch is performed 1 Re fetch is not performed 0 MC 0 R W Re Fetch Inhibit after Writing Memory Mapped IC This bit controls whether re fetch is performed for the ne...

Page 217: ...onfiguration The UTLB consists of 64 fully associative type entries Figure 7 7 shows the relationship between the page size and address format PPN 28 10 PPN 28 10 PPN 28 10 SZ 1 0 SZ 1 0 SZ 1 0 SH SH SH C C C PR 1 0 PR 1 0 PR 1 0 ASID 7 0 ASID 7 0 ASID 7 0 VPN 31 10 VPN 31 10 VPN 31 10 V V V Entry 0 Entry 1 Entry 2 D D D WT WT WT PPN 28 10 SZ 1 0 SH C PR 1 0 ASID 7 0 VPN 31 10 V Entry 63 D WT Figu...

Page 218: ...ical address of the physical page number With a 1 Kbyte page PPN 28 10 are valid With a 4 Kbyte page PPN 28 12 are valid With a 64 Kbyte page PPN 28 16 are valid With a 1 Mbyte page PPN 28 20 are valid The synonym problem must be taken into account when setting the PPN see section 7 4 5 Avoiding Synonym Problems PR 1 0 Protection key data 2 bit data expressing the page access right as a code 00 Ca...

Page 219: ...rite through bit Specifies the cache write mode 0 Copy back mode 1 Write through mode 31 1 Kbyte page 10 9 0 Virtual address 31 4 Kbyte page 12 11 0 Virtual address 31 64 Kbyte page 16 15 0 Virtual address 31 1 Mbyte page 20 19 0 Virtual address VPN Offset VPN Offset VPN Offset VPN Offset 28 10 9 0 Physical address 28 12 11 0 Physical address 28 16 15 0 Physical address 28 20 19 0 Physical address...

Page 220: ...s cached into the ITLB Figure 7 8 shows the ITLB configuration The ITLB consists of four fully associative type entries PPN 28 10 PPN 28 10 PPN 28 10 PPN 28 10 SZ 1 0 SZ 1 0 SZ 1 0 SZ 1 0 SH SH SH SH C C C C PR PR PR PR ASID 7 0 ASID 7 0 ASID 7 0 ASID 7 0 VPN 31 10 VPN 31 10 VPN 31 10 VPN 31 10 V V V V Entry 0 Entry 1 Entry 2 Entry 3 Notes 1 The D and WT bits are not supported 2 There is only one ...

Page 221: ...CR OCE No Data access to virtual address VA VA is in P4 area VA is in P2 area VA is in P1 area VA is in P0 U0 or P3 area MMUCR AT 1 SH 0 and MMUCR SV 0 or SR MD 0 VPNs match ASIDs match and V 1 Only one entry matches 1 Privileged Data TLB multiple hit exception Data TLB protection violation exception Data TLB miss exception 0 User VPNs match and V 1 Data TLB protection violation exception Initial ...

Page 222: ...4 area VA is in P2 area VA is in P1 area VA is in P0 U0 or P3 area MMUCR AT 1 SH 0 and MMUCR SV 0 or SR MD 0 VPNs match and V 1 VPNs match ASIDs match and V 1 Only one entry matches SR MD Instruction TLB multiple hit exception 0 User 1 Privileged PR C 1 and CCR ICE 1 Cache access Memory access Non cacheable Instruction TLB protection violation exception Instruction TLB miss exception Hardware ITLB...

Page 223: ...rded in the ITLB in an instruction access the MMU searches the UTLB If the necessary address translation information is recorded in the UTLB the MMU copies this information into the ITLB in accordance with the LRUI bit setting in MMUCR 7 4 2 MMU Software Management Software processing for the MMU consists of the following 1 Setting of MMU related registers Some registers are also partially updated...

Page 224: ...ethods before an access include an instruction fetch the area where TLB is used to translate the address is performed 1 Execute a branch using the RTE instruction In this case the branch destination may be the area where TLB is used to translate the address 2 Execute the ICBI instruction for any address including non cacheable area 3 If the LT bit in IRMCR is 0 initial value before executing the L...

Page 225: ...PN 10 PPN Entry specification 31 26252423 18171615 10 9 8 7 3 2 1 0 LRUI URB URC SV TI AT SQMD Figure 7 11 Operation of LDTLB Instruction 7 4 4 Hardware ITLB Miss Handling In an instruction access this LSI searches the ITLB If it cannot find the necessary address translation information ITLB miss occurred the UTLB is searched by hardware and if the necessary address translation information is pres...

Page 226: ...differ from bits 12 to 10 of the virtual address Consequently the following restrictions apply to the recording of address translation information in UTLB entries When address translation information whereby a number of 1 Kbyte page UTLB entries are translated into the same physical address is recorded in the UTLB ensure that the VPN 12 10 values are the same When address translation information w...

Page 227: ...ual address to which an instruction access has been made If multiple hits occur when the UTLB is searched by hardware in hardware ITLB miss handling an instruction TLB multiple hit exception will result When an instruction TLB multiple hit exception occurs a reset is executed and cache coherency is not guaranteed Hardware Processing In the event of an instruction TLB multiple hit exception hardwar...

Page 228: ... saved in SGR 6 Sets the MD bit in SR to 1 and switches to privileged mode 7 Sets the BL bit in SR to 1 and masks subsequent exception requests 8 Sets the RB bit in SR to 1 9 Branches to the address obtained by adding offset H 0000 0400 to the contents of VBR and starts the instruction TLB miss exception handling routine Software Processing Instruction TLB Miss Exception Handling Routine Software ...

Page 229: ... code H 0A0 in EXPEVT 4 Sets the PC value indicating the address of the instruction at which the exception occurred in SPC If the exception occurred at a delay slot sets the PC value indicating the address of the delayed branch instruction in SPC 5 Sets the SR contents at the time of the exception in SSR The R15 contents at this time are saved in SGR 6 Sets the MD bit in SR to 1 and switches to pr...

Page 230: ...7 5 5 Data TLB Miss Exception A data TLB miss exception occurs when address translation information for the virtual address to which a data access is made is not found in the UTLB entries The data TLB miss exception processing carried out by hardware and software is shown below Hardware Processing In the event of a data TLB miss exception hardware carries out the following processing 1 Sets the VP...

Page 231: ...d be issued at least one instruction after the LDTLB instruction 7 5 6 Data TLB Protection Violation Exception A data TLB protection violation exception occurs when even though a UTLB entry contains address translation information matching the virtual address to which a data access is made the actual access type is not permitted by the access right specified by the PR bit The data TLB protection v...

Page 232: ... carries out the following processing 1 Sets the VPN of the virtual address at which the exception occurred in PTEH 2 Sets the virtual address at which the exception occurred in TEA 3 Sets exception code H 080 in EXPEVT 4 Sets the PC value indicating the address of the instruction at which the exception occurred in SPC If the exception occurred at a delay slot sets the PC value indicating the addr...

Page 233: ... fetch to an area other than the P2 area is performed 1 Execute a branch using the RTE instruction In this case the branch destination may be an area other than the P2 area 2 Execute the ICBI instruction for any address including non cacheable area 3 If the MT bit in IRMCR is 0 initial value before accessing the memory mapped TLB the specific instruction does not need to be executed However note t...

Page 234: ...its 9 8 As only longword access is used 0 should be specified for address field bits 1 0 In the data field bits 31 10 indicate VPN bit 8 indicates V and bits 7 0 indicate ASID The following two kinds of operation can be used on the ITLB address array 1 ITLB address array read VPN V and ASID are read into the data field from the ITLB entry corresponding to the entry set in the address field 2 ITLB ...

Page 235: ... indicate PPN bit 8 indicates V bits 7 and 4 indicate SZ bit 6 indicates PR bit 3 indicates C and bit 1 indicates SH The following two kinds of operation can be used on ITLB data array 1 ITLB data array read PPN V SZ PR C and SH are read into the data field from the ITLB entry corresponding to the entry set in the address field 2 ITLB data array write PPN V SZ PR C and SH specified in the data fie...

Page 236: ...ponding to the entry set in the address field In a read associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0 2 UTLB address array write non associative VPN D V and ASID specified in the data field are written to the UTLB entry corresponding to the entry set in the address field The A bit in the address field should be cleared to ...

Page 237: ...when writing Information for selecting the entry to be accessed is specified in the address field and PPN V SZ PR C D SH and WT to be written to data array are specified in the data field In the address field bits 31 20 have the value H F70 indicating UTLB data array and the entry is specified by bits 13 8 In the data field bits 28 10 indicate PPN bit 8 indicates V bits 7 and 4 indicate SZ bits 6 ...

Page 238: ...0 0 0 0 E 19 20 8 7 14 13 0 0 Figure 7 15 Memory Mapped UTLB Data Array 7 7 32 Bit Address Extended Mode Setting the SE bit in PASCR to 1 changes mode from 29 bit address mode which handles the 29 bit physical address space to 32 bit address extended mode which handles the 32 bit physical address space P1 0 5GB P1 P2 1GB 0 5GB 4GB U0 P0 2GB U0 P0 2GB P2 0 5GB P3 0 5GB P3 0 5GB P4 0 5GB P4 0 5GB Vi...

Page 239: ...ual addresses in the U0 P0 or P3 area become 32 bit physical addresses Addresses in the P1 or P2 area are translated according to the PMB mapping information B 10 should be set to the upper 2 bits of virtual page number VPN 31 30 in the PMB in order to indicate P1 or P2 area The operation is not guaranteed when the value except B 10 is set to these bits 2 When the AT bit in MMUCR is 1 virtual addr...

Page 240: ...28 Mbyte page Upper 5 bits of virtual address For 512 Mbyte page Upper 3 bits of virtual address Note B 10 should be set to the upper 2 bits of VPN in order to indicate P1 or P2 area SZ Page size bits Specify the page size 00 16 Mbyte page 01 64 Mbyte page 10 128 Mbyte page 11 512 Mbyte page V Validity bit Indicates whether the entry is valid 0 Invalid 1 Valid Cleared to 0 by a power on reset Not ...

Page 241: ... 2 Software must ensure that every accessed P1 or P2 address has a corresponding PMB entry before the access occurs When an access to an address in the P1 or P2 area which is not recorded in the PMB is made this LSI is reset by the TLB In this case the accessed address in the P1 or P2 area which causes the TLB reset is stored in the TEA and code H 140 in the EXPEVT 3 This LSI does not guarantee th...

Page 242: ...e address field as an entry bits 31 to 24 in the data field are read as VPN and bit 8 in the data field as V 2 PMB address array write When memory writing is performed while bits 31 to 20 in the address field are specified as H F61 which indicates the PMB address array and bits 11 to 8 in the address field as an entry and bits 31 to 24 in the data field are specified as VPN and bit 8 in the data f...

Page 243: ... 1 0 0 E 23 24 12 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 7 18 Memory Mapped PMB Address Array Address field Data field PPN V E SZ Physical page number Validity bit Entry Page size bits UB C WT Buffered write bit Cacheability bit Write through bit Reserved bits write value should be 0 and read value is undefined 31 2 1 0 V UB 10 9 8 7 4 3 6 5 C PPN 31 0 1 1 1 1 0 1 1 1 0 0 0 1 E 23 24 19 20 8 7 12 1...

Page 244: ...the P0 P3 or U0 area When the MMU is disabled writing to the P0 P3 or U0 area is always performed as a buffered write Bit Bit Name Initial Value R W Description 31 SE 0 R W 0 29 bit address mode 1 32 bit address extended mode 30 to 8 All 0 R Reserved For details on reading from or writing to these bits see description in General Precautions on Handling of Product 7 to 0 UB All 0 R W Buffered Write...

Page 245: ... are extended to AREA0 7 2 AREA1 7 2 corresponding to physical address 31 26 See section 8 2 2 Queue Address Control Register 0 QACR0 and 8 2 3 Queue Address Control Register 1 QACR1 LSA0 LSA1 LDA0 LDA1 L0SADR L1SADR L0DADR and L1DADR fields are extended to bits 31 to 10 See section 9 2 2 L Memory Transfer Source Address Register 0 LSA0 section 9 2 3 L Memory Transfer Source Address Register 1 LSA...

Page 246: ...ev 1 00 Dec 13 2005 Page 196 of 1286 REJ09B0158 0100 4 Note that the V bit is mapped to both address array and data array in PMB registration That is first write 0 to the V bit in one of arrays and then write 1 to the V bit in another array ...

Page 247: ...Capacity 32 Kbyte cache 32 Kbyte cache Type 4 way set associative virtual address index physical address tag 4 way set associative virtual address index physical address tag Line size 32 bytes 32 bytes Entries 256 entries way 256 entries way Write method Copy back write through selectable Replacement method LRU least recently used algorithm LRU least recently used algorithm Table 8 2 Store Queue F...

Page 248: ...y is comprising 256 cache lines Figure 8 2 shows the configuration of the instruction cache Comparison 31 5 4 2 LW0 32 bits LW1 32 bits LW2 32 bits LW3 32 bits LW4 32 bits LW5 32 bits LW6 32 bits LW7 32 bits 6 bits MMU 12 5 255 19 bits 1 bit 1 bit Tag U V Address array way 0 to way 3 Data array way 0 to way 3 LRU Entry selection Longword LW selection Virtual address 3 8 22 19 0 Write data Read dat...

Page 249: ...tialized by a power on or manual reset V bit validity bit Indicates that valid data is stored in the cache line When this bit is 1 the cache line data is valid The V bit is initialized to 0 by a power on reset but retains its value in a manual reset U bit dirty bit The U bit is set to 1 if data is written to the cache line while the cache is being used in copy back mode That is the U bit indicates...

Page 250: ...tions The following registers are related to cache Table 8 3 Register Configuration Register Name Abbreviation R W P4 Address Area 7 Address Access Size Cache control register CCR R W H FF00 001C H 1F00 001C 32 Queue address control register 0 QACR0 R W H FF00 0038 H 1F00 0038 32 Queue address control register 1 QACR1 R W H FF00 003C H 1F00 003C 32 On chip memory control register RAMCR R W H FF00 ...

Page 251: ...ecuted However note that the CPU processing performance will be lowered because the instruction fetch is performed again for the next instruction after CCR has been updated Note that the method 3 may not be guaranteed in the future SuperH Series Therefore it is recommended that the method 1 or 2 should be used for being compatible with the future SuperH Series 31 30 29 28 27 26 25 24 23 22 21 20 1...

Page 252: ...always be 0 3 OCI 0 R W OC Invalidation Bit When 1 is written to this bit the V and U bits of all OC entries are cleared to 0 This bit is always read as 0 2 CB 0 R W Copy Back Bit Indicates the P1 area cache write mode 0 Write through mode 1 Copy back mode 1 WT 0 R W Write Through Mode Indicates the P0 U0 and P3 area cache write mode When address translation is performed the value of the WT bit in...

Page 253: ... R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R W R W R W R R R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AREA0 Bit Bit Name Initial Value R W Description 31 to 5 All 0 R Reserved These bits are always read as 0 The write value should always be 0 4 to 2 AREA0 Undefined R W When the MMU is disabled these bits generate physical address bits ...

Page 254: ...R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R W R W R W R R R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AREA1 Bit Bit Name Initial Value R W Description 31 to 5 All 0 R Reserved These bits are always read as 0 The write value should always be 0 4 to 2 AREA1 Undefined R W When the MMU is disabled these bits generate physical address bits 2...

Page 255: ...ddress including non cacheable area 3 If the R2 bit in IRMCR is 0 initial value before updating RAMCR the specific instruction does not need to be executed However note that the CPU processing performance will be lowered because the instruction fetch is performed again for the next instruction after RAMCR has been updated Note that the method 3 may not be guaranteed in the future SuperH Series The...

Page 256: ...Protective Functions 8 RP 0 R W On Chip Memory Protection Enable Bit For details see section 9 4 L Memory Protective Functions 7 IC2W 0 R W IC Two Way Mode bit 0 IC is a four way operation 1 IC is a two way operation For details see section 8 4 3 IC Two Way Mode 6 OC2W 0 R W OC Two Way Mode bit 0 OC is a four way operation 1 OC is a two way operation For details see section 8 3 6 OC Two Way Mode 5...

Page 257: ...to replace using the LRU bits is 1 see No 5 3 Cache hit The data indexed by virtual address bits 4 0 is read from the data field of the cache line on the hitted way in accordance with the access size Then the LRU bits are updated to indicate the hitted way is the latest one 4 Cache miss no write back Data is read into the cache line on the way which is selected to replace from the physical address...

Page 258: ... bits on each way are read from the cache line indexed by virtual address bits 12 5 2 The tag read from each way is compared with bits 28 10 of the physical address resulting from virtual address translation by the MMU If there is a way whose tag matches and its V bit is 1 see No 3 If there is no way whose tag matches and the V bit is 1 and the U bit of the way which is selected to replace using t...

Page 259: ...ts 12 5 2 The tag read from each way is compared with bits 28 10 of the physical address resulting from virtual address translation by the MMU If there is a way whose tag matches and its V bit is 1 see No 3 for copy back and No 4 for write through I If there is no way whose tag matches and its V bit is 1 and the U bit of the way which is selected to replace using the LRU bits is 0 see No 5 for cop...

Page 260: ... data field of the cache line on the way which is selected to replace are saved in the write back buffer Then a data write in accordance with the access size is performed for the data field on the hit way which is indexed by virtual address bits 4 0 Then the data excluding the cache missed data which is written already is read into the cache line on the way which is selected to replace from the ph...

Page 261: ...te through mode or writing to a non cacheable area This allows the CPU to proceed to the next operation as soon as the write to the write through buffer is completed without waiting for completion of the write to external memory Physical address bits 28 0 LW1 LW0 Figure 8 4 Configuration of Write Through Buffer 8 3 6 OC Two Way Mode When the OC2W bit in RAMCR is set to 1 OC two way mode which only...

Page 262: ...exed by virtual address bits 4 2 is read as an instruction from the data field on the hit way The LRU bits are updated to indicate the way is the latest one 4 Cache miss Data is read into the cache line on the way which selected using LRU bits to replace from the physical address space corresponding to the virtual address Data reading is performed using the wraparound method in order from the quad...

Page 263: ...corresponding to the virtual address Data reading is performed using the wraparound method in order from the quad word data 8 bytes including the cache missed data In the prefetch opreration the CPU doesn t wait the data arrived While the one cache line of data is being read the CPU can execute the next processing When reading of one line of data is completed the tag corresponding to the physical ...

Page 264: ...instruction OCBP Rn Operand cache invalidation with write back Operand cache write back instruction OCBWB Rn Operand cache write back Operand cache allocate instruction MOVCA L R0 Rn Operand cache allocation Instruction cache invalidate instruction ICBI Rn Instruction cache invalidation Operand access synchronization instruction SYNCO Wait for data transfer completion The operand cache can receive...

Page 265: ...entry is not dirty it is no operation 8 5 2 Prefetch Operation This LSI supports a prefetch instruction to reduce the cache fill penalty incurred as the result of a cache miss If it is known that a cache miss will result from a read or write operation it is possible to fill the cache with data beforehand by means of the prefetch instruction to prevent a cache miss due to the read or write operatio...

Page 266: ...ed to be executed However note that the CPU processing performance will be lowered because the instruction fetch is performed again for the next instruction after making an access to the memory mapped IC Note that the method 3 may not be guaranteed in the future SuperH Series Therefore it is recommended that the method 1 or 2 should be used for being compatible with the future SuperH Series In pri...

Page 267: ...he IC entry corresponding to the way and entry set in the address field In a read associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0 2 IC address array write non associative The tag and V bit specified in the data field are written to the IC entry corresponding to the way and entry set in the address field The A bit in the addr...

Page 268: ...0100 Address field 31 23 12 5 4 3 2 1 0 1 1 1 1 0 0 0 0 0 0 0 0 Entry A Data field 31 10 9 1 0 V Tag Way V A 24 13 14 15 Validity bit Association bit Reserved bits write value should be 0 and read value is undefined Don t care Figure 8 5 Memory Mapped IC Address Array ...

Page 269: ...the entry As only longword access is used 0 should be specified for address field bits 1 0 The data field is used for the longword data specification The following two kinds of operation can be used on the IC data array 1 IC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the IC entry corresponding to the ...

Page 270: ...ing to the way and entry set in the address field In a read associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0 2 OC address array write non associative The tag U bit and V bit specified in the data field are written to the OC entry corresponding to the way and entry set in the address field The A bit in the address field should...

Page 271: ...CBP or OCBWB instruction should be used to operate the OC definitely by reporting data TLB miss exception Address field 31 23 5 4 3 2 1 0 1 1 1 1 0 1 0 0 Entry A Data field 31 10 9 1 0 V Tag 24 1312 14 15 2 U V U A Validity bit Dirty bit Association bit Reserved bits write value should be 0 and read value is undefined Don t care Way 0 0 0 0 Figure 8 7 Memory Mapped OC Address Array ...

Page 272: ... is used 0 should be specified for address field bits 1 0 The data field is used for the longword data specification The following two kinds of operation can be used on the OC data array 1 OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the way and entry set in the address ...

Page 273: ... 7 SQ1 SQ1 0 SQ1 1 SQ1 2 SQ1 3 SQ1 4 SQ1 5 SQ1 6 SQ1 7 4B 4B 4B 4B 4B 4B 4B 4B Figure 8 9 Store Queue Configuration 8 7 2 Writing to SQ A write to the SQs can be performed using a store instruction for addresses H E000 0000 to H E3FF FFFC in the P4 area A longword or quadword access size can be used The meanings of the address bits are as follows 31 26 111000 Store queue specification 25 6 Don t c...

Page 274: ...n but the C and WT bits have no meaning with regard to this page When a prefetch instruction is issued for the SQ area address translation is performed and physical address bits 28 10 are generated in accordance with the SZ bit specification For physical address bits 9 5 the address prior to address translation is generated in the same way as when the MMU is disabled Physical address bits 4 0 are ...

Page 275: ... the SQs to external memory using a PREF instruction As a result a TLB miss exception or protection violation exception is generated as required However if SQ access is enabled in privileged mode only by the SQMD bit in MMUCR an address error will occur even if address translation is successful in user mode When MMU is disabled AT 0 in MMUCR Operation is in accordance with the SQMD bit in MMUCR 0 ...

Page 276: ...follows 1 The tag bits 28 10 19 bits in the IC and OC are extended to bits 31 10 22 bits 2 An instruction which operates the IC a memory mapped IC access and writing to the ICI bit in CCR should be located in the P1 or P2 area The cacheable bit C bit in the corresponding entry in the PMB should be 0 3 Bits 4 2 3 bits for the AREA0 bit in QACR0 and the AREA1 bit in QACR1 are extended to bits 7 2 6 ...

Page 277: ...ize Two Pages Total Page 16 Kbytes Page 0 of L memory H E500E000 to H E500FFFF Page 1 of L memory H E5010000 to H E5011FFF Ports Each page has three independent read write ports and is connected to each bus The instruction bus is used when L memory is accessed through instruction fetch The operand bus is used when L memory is accessed through operand access The SuperHyway bus is used for L memory ...

Page 278: ...transfer destination address register 1 LDA1 R W H FF00005C H 1F00005C 32 Note The P4 address is the address used when using P4 area in the virtual address space The area 7 address is the address used when accessing from area 7 in the physical address space using the TLB Table 9 3 Register Status in Each Processing State Name Abbreviation Power On Reset Manual Reset Sleep On chip memory control re...

Page 279: ...Memory Access Mode Specifies the right of access to the L memory from the virtual address space 0 An access in privileged mode is allowed An address error exception occurs in user mode 1 An access user privileged mode is allowed 8 RP 0 R W On Chip Memory Protection Enable Selects whether or not to use the protective functions using ITLB and UTLB for accessing the L memory from the virtual address ...

Page 280: ... R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 0 0 0 0 Initial value R W R W R W R W R W R W R R R R R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 29 All 0 R Reserved These bits are always read as 0 The write value should always be 0 28 to 10 L0SADR Undefined R W L Memory Page 0 Block Transfer Source Address When MMUCR AT 0 or RAMCR RP 0 these...

Page 281: ...ss is used as the transfer source physical address 1 The L0SADR value is used as the transfer source physical address Settable values 111111 Transfer source physical address is specified in 1 Kbyte units 111110 Transfer source physical address is specified in 2 Kbyte units 111100 Transfer source physical address is specified in 4 Kbyte units 111000 Transfer source physical address is specified in ...

Page 282: ...SZ R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 0 0 0 0 Initial value R W R W R W R W R W R W R R R R R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 29 All 0 R Reserved These bits are always read as 0 The write value should always be 0 28 to 10 L1SADR Undefined R W L Memory Page 1 Block Transfer Source Address When MMUCR AT 0 or RAMCR RP 0 the...

Page 283: ...d address is used as the transfer source physical address 1 The L1SADR value is used as the transfer source physical address Settable values 111111 Transfer source physical address is specified in 1 Kbyte units 111110 Transfer source physical address is specified in 2 Kbyte units 111100 Transfer source physical address is specified in 4 Kbyte units 111000 Transfer source physical address is specif...

Page 284: ... R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 0 0 0 0 Initial value R W R W R W R W R W R W R R R R R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 29 All 0 R Reserved These bits are always read as 0 The write value should always be 0 28 to 10 L0DADR Undefined R W L Memory Page 0 Block Transfer Destination Address When MMUCR AT 0 or RAMCR RP 0 ...

Page 285: ...used as the transfer destination physical address 1 The L0DADR value is used as the transfer destination physical address Settable values 111111 Transfer destination physical address is specified in 1 Kbyte units 111110 Transfer destination physical address is specified in 2 Kbyte units 111100 Transfer destination physical address is specified in 4 Kbyte units 111000 Transfer destination physical ...

Page 286: ... R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 0 0 0 0 Initial value R W R W R W R W R W R W R R R R R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 29 All 0 R Reserved These bits are always read as 0 The write value should always be 0 28 to 10 L1DADR Undefined R W L Memory Page 1 Block Transfer Destination Address When MMUCR AT 0 or RAMCR RP 0 ...

Page 287: ...ed as the transfer destination physical address 1 The L1DADR value is used as the transfer destination physical address Settable values 111111 Transfer destination physical address is specified in 1 Kbyte units 111110 Transfer destination physical address is specified in 2 Kbyte units 111100 Transfer destination physical address is specified in 4 Kbyte units 111000 Transfer destination physical ad...

Page 288: ...e L memory to the external memory through a write back instruction OCBWB Block transfer from the L memory to the external memory begins when the OCBWB instruction is issued to the address in the L memory area in the virtual address space In either case transfer rate is fixed to 32 bytes Since the start address is always limited to a 32 byte boundary the lower five bits of the address indicated by ...

Page 289: ...gister And the L0SSZ bits in the LSA0 register choose either the virtual addresses specified through the PRFF instruction or the L0SADR values as bits 15 to 10 of the transfer source physical address In other words the transfer source area can be specified in units of 1 Kbyte to 64 Kbytes The transfer destination physical address in block transfer from page 0 in the L memory is set in the L0DADR b...

Page 290: ...he L memory is accessed in user mode it is determined to be an address error exception When MMUCR AT 1 and RAMCR RP 1 MMU exception and address error exception are checked in the L memory area which is a part of P4 area as with the area P0 P3 U0 The above descriptions are summarized in table 9 4 Table 9 4 Protective Function Exceptions to Access L Memory MMUCR AT RAMCR RP SR MD RAMCR RMD Always Oc...

Page 291: ...ency In order to allocate instructions in the L memory write an instruction to the L memory execute the following sequence then branch to the rewritten instruction SYNCO ICBI Rn In this case the target for the ICBI instruction can be any address L memory address may be possible within the range where no address error exception occurs and cache hit miss is possible 9 5 3 Sleep Mode The SuperHyway b...

Page 292: ...Section 9 L Memory Rev 1 00 Dec 13 2005 Page 242 of 1286 REJ09B0158 0100 ...

Page 293: ...The bit can be read within the interrupt exception handling routine to confirm the pin state and thus achieve a form of noise cancellation NMI request masking when the block bit BL in the status register SR is set to 1 Masking or non masking of NMI requests when the BL bit in SR is set to 1 can be selected Extended functions for the SH 4A Automatically updates the IMASK bit in SR according to the ...

Page 294: ...FLCTL H UDI DMAC Interrupt requests Interrupt requests Interrupt requests INT2GPIC INT2PRI0 to INT2PRI7 INT2PRII INTC Legend CMT DMAC FLCTL HAC HSPI H UDI ICR0 ICR1 INTPRI INT2PRI0 to INT2PRI7 INT2GPIC Compare Match Timer Timer Counter Direct Memory Access Controller NAND Flash Memory Controller Audio Codec Interface Serial Protocol Interface User Debugging Interface Interrupt Control Register 0 1...

Page 295: ...y executing a return from exception instruction RTE This instruction restores the contents of PC and SR and returns control to the normal processing routine at the point at which the exception occurred The contents of SGR are not written back to R15 by the RTE instruction 1 The contents of the PC SR and R15 are saved in SPC SSR and SGR respectively 2 The block BL bit in SR is set to 1 3 The mode M...

Page 296: ...detection of IRQ input Table 10 1 Interrupt Types Source Number of Sources Max Priority INTEVT Remarks NMI 1 H 1C0 IRL 7 4 pin H 0 External interrupts IRL interrupt 1 2 H 200 IRL 3 0 pin H 0 High IRL 7 4 pin H 1 H 220 IRL 3 0 pin H 1 IRL 7 4 pin H 2 H 240 IRL 3 0 pin H 2 IRL 7 4 pin H 3 H 260 IRL 3 0 pin H 3 IRL 7 4 pin H 4 Inverse of values on the input pins because the signals are active low For...

Page 297: ...n the input pins because the signals are active low For example IRL 7 4 pin H 0 means the external pin input levels are IRL 7 pin Low IRL 6 pin Low IRL 5 pin Low IRL 4 pin Low so the priority level is 15 H F see table 10 11 H 3C0 IRL 3 0 pin H E Low 8 Values set in INTPRI H 240 IRQ 0 High IRQ interrupt H 280 IRQ 1 H 2C0 IRQ 2 H 300 IRQ 3 H 340 IRQ 4 H 380 IRQ 5 H 3C0 IRQ 6 H 200 IRQ 7 Low RTC 3 H ...

Page 298: ...0 DMAE 2 SCIF ch0 4 H 700 ERI0 2 H 720 RXI0 2 H 740 BRI0 2 H 760 TXI0 2 DMAC 0 7 2 7 H 780 DMINT4 2 H 7A0 DMINT5 2 DMAC 1 6 2 6 H 7C0 DMINT6 2 H 7E0 DMINT7 2 CMT 1 H 900 CMTI HAC 1 H 980 HACI PCIC 0 1 H A00 PCISERR PCIC 1 1 H A20 PCIINTA PCIC 2 1 H A40 PCIINTB PCIC 3 1 H A60 PCIINTC PCIC 4 1 H A80 PCIINTD PCIC 5 5 H AA0 PCIERR H AC0 PCIPWD3 H AE0 PCIPWD2 H B00 PCIPWD1 H B20 PCIPWD0 SCIF ch1 4 H B8...

Page 299: ...t J0 Port K4 H FE0 GPIOI3 Port E6 Port K5 Notes 1 IRL 7 4 and IRL 3 0 interrupts produce the same INTEVT codes When using level encoded interrupt requests note that there is no flag to distinguish between interrupt requests on the IRL 7 4 and IRL 3 0 pins 2 ITI Interval timer interrupt TUNI0 to TUNI5 TMU channel 0 to 5 under flow interrupt TICPI2 TMU channel 2 input capture interrupt DMINT0 to DMI...

Page 300: ...el encoded interrupt input when ICR0 IRLM0 0 IRQ3 to IRQ0 individual pin interrupt input when ICR0 IRLM0 1 IRQ IRL7 to IRQ IRL4 1 External interrupt input pin Input Interrupt request signal input IRL 7 4 4 bit level encoded interrupt input when ICR0 IRLM1 0 IRQ7 to IRQ4 individual pin interrupt input when ICR0 IRLM1 1 IRQOUT 2 Interrupt request output Output Indicates that an interrupt request has...

Page 301: ... Pck Interrupt mask register 2 INTMSK2 R W H FFD4 0080 H 1FD4 0080 32 Pck Interrupt mask clear register 0 INTMSKCLR0 R W H FFD0 0064 H 1FD0 0064 32 Pck Interrupt mask clear register 1 INTMSKCLR1 R W H FFD0 0068 H 1FD0 0068 32 Pck Interrupt mask clear register 2 INTMSKCLR2 R W H FFD4 0084 H 1FD4 0084 32 Pck NMI flag control register NMIFCR R W H FFD0 00C0 H 1FD0 00C0 32 Pck User interrupt mask leve...

Page 302: ...W H FFD4 003C H 1FD4 003C 32 Pck INT2B0 R H FFD4 0040 H 1FD4 0040 32 Pck INT2B1 R H FFD4 0044 H 1FD4 0044 32 Pck On chip module interrupt source registers INT2B2 R H FFD4 0048 H 1FD4 0048 32 Pck INT2B3 R H FFD4 004C H 1FD4 004C 32 Pck INT2B4 R H FFD4 0050 H 1FD4 0050 32 Pck INT2B5 R H FFD4 0054 H 1FD4 0054 32 Pck INT2B6 R H FFD4 0058 H 1FD4 0058 32 Pck INT2B7 R H FFD4 005C H 1FD4 005C 32 Pck GPIO ...

Page 303: ...ed Interrupt mask clear register 1 INTMSKCLR1 H 0000 0000 H 0000 0000 Retained Interrupt mask clear register 2 INTMSKCLR2 H 0000 0000 H 0000 0000 Retained NMI flag control register NMIFCR H x000 0000 H x000 0000 Retained User interrupt mask level register USERIMASK H 0000 0000 H 0000 0000 Retained INT2PRI0 H 0000 0000 H 0000 0000 Retained On chip module interrupt priority registers INT2PRI1 H 0000...

Page 304: ...x xxxx Retained On chip module interrupt source registers INT2B2 H xxxx xxxx H xxxx xxxx Retained INT2B3 H xxxx xxxx H xxxx xxxx Retained INT2B4 H xxxx xxxx H xxxx xxxx Retained INT2B5 H xxxx xxxx H xxxx xxxx Retained INT2B6 H xxxx xxxx H xxxx xxxx Retained INT2B7 H xxxx xxxx H xxxx xxxx Retained GPIO interrupt set register INT2GPIC H 0000 0000 H 0000 0000 Retained Legend x Undefined Note The init...

Page 305: ...R R R R Bit Initial value R W Bit Name Initial Value R W Description 31 NMIL Undefined R NMI Input Level Indicates the signal level being input on the NMI pin Reading this bit allows the user to know the NMI pin level and writing is invalid 0 Low level is being input on the NMI pin 1 High level is being input on the NMI pin Note The initial value of this bit depends on the level initially being in...

Page 306: ...er an interrupt request signal to the NMI pin is detected at the rising edge or the falling edge 0 An interrupt request is detected at the falling edge of NMI input initial value 1 An interrupt request is detected at the rising edge of NMI input Note NMI interrupt is not detected for at least six bus clock cycles after modification of this bit 23 IRLM0 0 R W IRL Pin Mode 0 Selects whether IRQ IRL3...

Page 307: ...ls are sampled in four consecutive bus clock cycles 21 LSH 0 R W IRQ IRL Level sense with holding function Selects whether or not to use the holding function for level encoded IRL and level sense IRQ interrupts 0 IRQ level sense and IRL interrupt requests are held initial value 1 IRQ level sense and IRL interrupt requests are not held compatible with current SH 4 behavior for IRQ in level sense mo...

Page 308: ...R R Bit Initial value R W Bit Name Initial Value R W Description 31 30 IRQ0S 00 R W 29 28 IRQ1S 00 R W 27 26 IRQ2S 00 R W 25 24 IRQ3S 00 R W 23 22 IRQ4S 00 R W 21 20 IRQ5S 00 R W 19 18 IRQ6S 00 R W 17 16 IRQ7S 00 R W IRQn Sense Select n 0 to 7 Selects whether the corresponding individual pin interrupt signal on the IRQ IRL7 to IRQ IRL0 pins is detected on rising or falling edges or at the high or ...

Page 309: ... W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IP7 IP6 IP5 IP4 Bit Initial value R W Bit Name Initial Value R W Description 31 to 28 IP0 H 0 R W Set the priority of IRQ0 as an individual pin interrupt request 27 to 24 IP1 H 0 R W Set the priori...

Page 310: ...R R R R R R R R R R R R Bit Initial value R W Description Bit Name Initial Value R W In Edge Detection IRQnS 00 or 01 n 0 to 7 In Level Detection IRQnS 10 or 11 n 0 to 7 31 IR0 0 R W 30 IR1 0 R W 29 IR2 0 R W 28 IR3 0 R W 27 IR4 0 R W 26 IR5 0 R W 25 IR6 0 R W 24 IR7 0 R W When reading 0 The corresponding IRQ interrupt request has not been detected 1 The corresponding IRQ interrupt request has bee...

Page 311: ...t Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Name Initial Value R W Description 31 IM00 1 R W Sets masking of individual pin interrupt request on IRQ0 30 IM01 1 R W Sets masking of individual pin interrupt request on IRQ1 29 IM02 1 R W Sets masking of individual pin interrupt request on IRQ2 28 I...

Page 312: ...W Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Name Initial Value R W Description 31 IM10 1 R W Mask setting for all IRL3 to IRL0 interrupt requests when pins IRQ IRL3 to IRQ IRL0 operate as a level encoded interrupt input 30 IM11 1 R W Mask setting for all IRL7 to IRL4 interrupt requests when ...

Page 313: ...0 0 0 IM101 IM102 IM103 IM104 IM105 IM106 IM107 IM108 IM109 IM110 IM111 IM112 IM113 IM115 IM114 Bit Initial value R W Bit Name Initial Value R W Description 31 IM015 0 R W Sets masking of interrupt request generation by IRL3 to IRL0 LLLL H 0 30 IM014 0 R W Sets masking of interrupt request generation by IRL3 to IRL0 LLLH H 1 29 IM013 0 R W Sets masking of interrupt request generation by IRL3 to IR...

Page 314: ...9 IM003 0 R W Sets masking of interrupt request generation by IRL3 to IRL0 HHLL H C 18 IM002 0 R W Sets masking of interrupt request generation by IRL3 to IRL0 HHLH H D 17 IM001 0 R W Sets masking of interrupt request generation by IRL3 to IRL0 HHHL H E 16 0 R Reserved This bit is always read as 0 The write value should always be 0 15 IM115 0 R W Sets masking of interrupt request generation by IRL...

Page 315: ...masking of interrupt request generation by IRL7 to IRL4 HLLL H 8 6 IM106 0 R W Sets masking of interrupt request generation by IRL7 to IRL4 HLLH H 9 5 IM105 0 R W Sets masking of interrupt request generation by IRL7 to IRL4 HLHL H A 4 IM104 0 R W Sets masking of interrupt request generation by IRL7 to IRL4 HLHH H B 3 IM103 0 R W Sets masking of interrupt request generation by IRL7 to IRL4 HHLL H C...

Page 316: ...e Initial Value R W Description 31 IC00 0 R W Clears masking of IRQ0 as an individual pin interrupt request 30 IC01 0 R W Clears masking of IRQ1 as an individual pin interrupt request 29 IC02 0 R W Clears masking of IRQ2 as an individual pin interrupt request 28 IC03 0 R W Clears masking of IRQ3 as an individual pin interrupt request 27 IC04 0 R W Clears masking of IRQ4 as an individual pin interr...

Page 317: ... R R R R R R R R R Bit Initial value R W Bit Name Initial Value R W Description 31 IC10 0 R W Clears masking of IRL3 to IRL0 interrupt requests when IRQ IRL3 to IRQ IRL0 operate as a level encoded interrupt input 30 IC11 0 R W Clears masking of IRL7 to IRL4 interrupt requests when IRQ IRL7 to IRQ IRL4 operate as a level encoded interrupt input When reading Values read are undefined When writing 0 ...

Page 318: ...rs masking of interrupt request generation by IRL3 to IRL0 LLLL H 0 30 IC014 0 R W Clears masking of interrupt request generation by IRL3 to IRL0 LLLH H 1 29 IC013 0 R W Clears masking of interrupt request generation by IRL3 to IRL0 LLHL H 2 When reading Values read are undefined When writing 0 No effect 1 Clears the corresponding interrupt mask enables the interrupt 28 IC012 0 R W Clears masking ...

Page 319: ...C002 0 R W Clears masking of interrupt request generation by IRL3 to IRL0 HHLH H D 17 IC001 0 R W Clears masking of interrupt request generation by IRL3 to IRL0 HHHL H E 16 0 R Reserved This bit is always read as 0 The write value should always be 0 15 IC115 0 R W Clears masking of interrupt request generation by IRL7 to IRL4 LLLL H 0 14 IC114 0 R W Clears masking of interrupt request generation b...

Page 320: ...es the Interrupt 6 IC106 0 R W Clears masking of interrupt request generation by IRL7 to IRL4 HLLH H 9 5 IC105 0 R W Clears masking of interrupt request generation by IRL7 to IRL4 HLHL H A 4 IC104 0 R W Clears masking of interrupt request generation by IRL7 to IRL4 HLHH H B 3 IC103 0 R W Clears masking of interrupt request generation by IRL7 to IRL4 HHLL H C 2 IC102 0 R W Clears masking of interru...

Page 321: ...tically Even if 0 is written to the NMIFL bit before the NMI request is accepted by the CPU the NMI request is not canceled 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 NMIFL NMIL R W R R R R R R R R R R R R R R R Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Nam...

Page 322: ...her an NMI interrupt request signal has been detected This bit is automatically set to 1 when the INTC detects an NMI interrupt request Write 0 to clear the bit Writing 1 to this bit has no effect When reading 1 NMI has been detected 0 NMI has not been detected When writing 0 Clears the NMI flag 1 No effect 15 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0...

Page 323: ... masked Interrupts with priority levels higher than the level set in the UIMASK bits are accepted under the following conditions The corresponding interrupt mask bit in the interrupt mask register is cleared to 0 the interrupt is enabled The priority level setting in the IMASK bits in also SR is lower than that of the interrupt Even if an interrupt is accepted the UIMASK value does not change USER...

Page 324: ...to which the other INTC registers are allocated When accessing this register in user mode translate the address through the MMU In a system with a multitasking OS the memory protection functions of the MMU must be used to control which processes have access to USERIMASK When terminating a task or switching to another task be sure to clear USERIMASK to 0 beforehand If the UIMASK bits are erroneousl...

Page 325: ...09B0158 0100 4 Set the UIMASK bits so that B type interrupts are masked during execution of the device driver that is operating in user mode 5 Process interrupts with a high priority in the device driver 6 Clear the UIMASK bits to 0 to return from processing in the device driver ...

Page 326: ...1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R R R R W R W R W R W R W R R R Bit Initial value R W Table 10 5 shows the correspondence between interrupt request sources and bits in INT2PRI0 to INT2PRI7 Table 10 5 Interrupt Request Sources and INT2PRI0 to INT2PRI7 Bits Register 28 to 24 20 to 16 12 to 8 4 to 0 INT2PRI0 TMU channel 0 TMU channel 1 TMU chann...

Page 327: ... 15 14 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Table 10 6 shows the correspondence between bits in INT2A0 and sources Table 10 6 Correspondence between Bits in INT2A0 and Sources Bit Initial Value R W Source Function Description 31 to 26 All 0 R Reserved These bits are always read as 0 The write value should always be 0 25 R GPIO Indicates GPIO interrupt source 24 R FLCTL Indic...

Page 328: ...e should always be 0 9 R DMAC 1 Indicates interrupt sources of DMAC channels 6 to 11 8 R DMAC 0 Indicates interrupt sources of DMAC channels 0 to 5 and address error interrupt 7 R H UDI Indicates H UDI interrupt source 6 0 R Reserved This bit is always read as 0 The write value should always be 0 5 R WDT Indicates WDT interrupt source 4 R SCIF channel 1 Indicates the SCIF channel 1 interrupt sourc...

Page 329: ...3 to 5 interrupt sources 0 R TMU channels 0 to 2 Indicates the TMU channel 0 to 2 interrupt sources Indicates interrupt sources for the individual peripheral modules INT2A0 is not affected by the state of the interrupt mask register 0 No interrupt 1 An interrupt has been generated Note Interrupt sources can also be identified by directly reading the INTEVT code that is sent to the CPU In this case...

Page 330: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Table 10 7 shows the correspondence between bits in INT2A1 and sources Table 10 7 Correspondence between Bits in INT2A1 and Sources Bit Initial Value R W Source Function Description 31 to 26 0 R Reserved These bits are always read as 0 The write value should always be 0 25 0 R GPIO Indicates GPIO interrupt source 24 ...

Page 331: ...always read as 0 The write value should always be 0 9 0 R DMAC 1 Indicates interrupt sources of DMAC channels 6 to 11 Indicates interrupt sources for the individual peripheral modules INT2A1 is affected by the state of the interrupt mask register 0 No interrupt 1 An interrupt has been generated Note Interrupt sources can also be identified by directly reading the INTEVT code that is sent to the CP...

Page 332: ... that is sent to the CPU In this case reading INT2A0 is not necessary 10 3 12 Interrupt Mask Register INT2MSKR INT2MSKR is a 32 bit readable writable register that sets interrupt masking for each of the sources indicated in the interrupt source register The CPU is not notified of interrupts for which the corresponding bits in INT2MSKRG are set to 1 INT2MSKR is initialized to H FFFF FFFF mask state...

Page 333: ...Masks the PCIINTC interrupt 16 1 R W PCIC 2 Masks the PCIINTB interrupt Masks interrupts for individual modules When reading 0 No masking 1 Masking When writing 0 No effect 1 Masks the interrupt 15 1 R W PCIC 1 Masks the PCIINTA interrupt 14 1 R W PCIC 0 Masks the PCISERR interrupt 13 1 R W HAC Masks the HAC interrupt 12 1 R W CMT Masks the CMT interrupt 11 10 All 1 R W Reserved These bits are alw...

Page 334: ...arget Function Description 2 1 R W RTC Masks the RTC interrupt 1 1 R W TMU channels 3 to 5 Masks TMU channels 3 to 5 interrupts 0 1 R W TMU channels 0 to 2 Masks TMU channels 0 to 2 interrupts Masks interrupts for individual modules When reading 0 No masking 1 Masking When writing 0 No effect 1 Masks the interrupt ...

Page 335: ...9 shows the correspondence between bits in INT2MSKCR and interrupt mask clearing Table 10 9 Correspondence between Bits in INT2MSKCR and Interrupt Mask Clearing Bit Initial Value R W Target Function Description 31 to 26 All 0 R Reserved These bits are always read as 0 The write value should always be 0 25 0 R W GPIO Clears the GPIO interrupt masking 24 0 R W FLCTL Clears the FLCTL interrupt maskin...

Page 336: ...channels 6 to 11 8 0 R W DMAC 0 Clears the interrupt masking for DMAC channels 0 to 5 and address error interrupt Clears interrupt masking for each peripheral module When reading Always 0 When writing 0 Invalid 1 Interrupt mask is cleared 7 0 R W H UDI Clears H UDI interrupt masking 6 0 R Reserved This bit is always read as 0 The write value should always be 0 5 0 R W WDT Clears the WDT interrupt ...

Page 337: ... always read as 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 R R R R R R R R R R R R R R R R Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 R R R R R R R R R R R R R R R R Bit Initial value R W INT2B0 Indicates detailed interrupt sources for the TMU Module Bit Name Detailed Source Description 31 to 7 Reserved These bits are always read as 0 Writing to these bits is invalid 6 TUNI...

Page 338: ...e Detailed Source Description SCIF 31 to 8 Reserved These bits are always read as 0 Writing to these bits is invalid 7 TXI1 SCIF channel 1 transmit FIFO data empty interrupt 6 BRI1 SCIF channel 1 break interrupt or overrun error interrupt 5 RXI1 SCIF channel 1 receive FIFO data full interrupt or receive data ready interrupt 4 ERI1 SCIF channel 1 receive error interrupt 3 TXI0 SCIF channel 0 transm...

Page 339: ...f end interrupt 7 DMINT7 Channel 7 DMA transfer end or half end interrupt 6 DMINT6 Channel 6 DMA transfer end or half end interrupt 5 DMINT5 Channel 5 DMA transfer end or half end interrupt 4 DMINT4 Channel 4 DMA transfer end or half end interrupt 3 DMINT3 Channel 3 DMA transfer end or half end interrupt 2 DMINT2 Channel 2 DMA transfer end or half end interrupt 1 DMINT1 Channel 1 DMA transfer end ...

Page 340: ... state D0 state interrupt 8 PWD1 PCIC power state D1 state interrupt 7 PWD2 PCIC power state D2 state interrupt 6 PWD3 PCIC power state D3 state interrupt 5 ERR PCIC error interrupt 4 INTD PCIC INTD interrupt 3 INTC PCIC INTC interrupt 2 INTB PCIC INTB interrupt 1 INTA PCIC INTA interrupt PCIC 0 SERR PCIC SERR interrupt Indicates PCIC interrupt sources This register indicates the PCIC interrupt so...

Page 341: ...ady interrupt 2 ERR CRC error interrupt data timeout error interrupt or command timeout error interrupt 1 TRAN Data response interrupt data transfer end interrupt command response receive end interrupt command transmit end interrupt or data busy end interrupt MMCIF 0 FSTAT MMC FIFO empty interrupt or FIFO full interrupt Indicates MMC interrupt sources This register indicates MMC interrupt sources ...

Page 342: ...ead as 0 Writing to these bits is invalid 3 FLTRQ1 FLCTL FLECFIFO transfer request interrupt 2 FLTRQ0 FLCTL TLDTFIFO transfer request interrupt 1 FLTEND FLCTL transfer end interrupt FLCTL 0 FLSTE FLCTL status error interrupt or ready busy timeout error interrupt Indicates FLCTL interrupt sources This register indicates FLCTL interrupt sources even if the mask setting for FLCTL interrupts has been ...

Page 343: ...1I GPIO interrupt from port H pin 1 16 PORTH0I GPIO interrupt from port H pin 0 15 to 11 Reserved These bits are always read as 0 Writing to these bits is invalid 10 PORTE5I GPIO interrupt from port E pin 5 9 PORTE4I GPIO interrupt from port e pin 4 8 PORTE3I GPIO interrupt from port E pin 3 7 to 3 Reserved These bits are always read as 0 Writing to these bits is invalid 2 PORTE2I GPIO interrupt f...

Page 344: ...onding pin as an input in the corresponding port control register PECR PHCR PJCR PKCR For the port control registers see section 28 General Purpose I O GPIO 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R R R R R W R W R R R R R R Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R R R R R R W R...

Page 345: ...n 0 Disables the corresponding interrupt request 1 Enables the corresponding interrupt request 19 0 R W PORTK4E Enables interrupt request from pin 4 of port K 18 0 R W PORTJ0E Enables interrupt request from pin 0 of port J 17 0 R W PORTH1E Enables interrupt request from pin 1 of port H 16 0 R W PORTH0E Enables interrupt request from pin 0 of port H 15 to 11 All 0 R W Reserved Initial value all 0 1...

Page 346: ...o 0 the IMASK value in SR is not affected by the acceptance of an NMI interrupt 10 4 2 IRQ Interrupts IRQ interrupts are input by single pin interrupts on pins IRQ IRL7 to IRQ IRL0 IRQ interrupts are available when pins IRQ IRL7 to IRQ IRL0 are made to operate as IRQn n 0 to 7 independent interrupt inputs by setting the IRLM0 and IRLM1 bits in ICR0 to 1 The IRQnS1 and IRQnS0 bits in ICR1 are used ...

Page 347: ...tion 10 7 Usage Notes When the INTMU bit in CPUOPM is set to 1 the interrupt mask level IMASK in SR is automatically modified to the level of an accepted interrupt When the INTMU bit is cleared to 0 the IMASK value in SR is not affected by the acceptance of an interrupt 10 4 3 IRL Interrupts IRL interrupts are input as combinations of levels on pins IRQ IRL7 to IRQ IRL4 or IRQ IRL3 to IRQ IRL0 The...

Page 348: ...IRL interrupt detection requires a built in noise cancellation feature that is a mechanism to ensure that transient level changes on the IRL pins are not detected as interrupts For this purpose an IRL interrupt is not detected unless the levels sampled per bus clock cycle remain unchanged for four consecutive cycles The IRL interrupt priority level should be maintained until the CPU has accepted t...

Page 349: ...seful way to identify the sources and handle the individual interrupts A priority level from 31 to 0 can be set for each module by means of INT2PRI0 to INT2PRI7 The INTC rounds off the lowest order bit and sends a 4 bit code to the CPU For details see section 10 4 5 Interrupt Priority Levels of On chip Module Interrupts The interrupt mask level bits IMASK in SR are not affected by the processing o...

Page 350: ...can be assigned any of 30 5 bit priority levels see figure 10 3 The interrupt level reception interface is four bits wide and thus handles 15 priority levels with H 0 as the interrupt request mask setting The value in the INTC consists of five bits one bit of which is an extension that allows the assignment of an individual priority level to each of the on chip modules When the CPU is notified of ...

Page 351: ...priority register thus H 02 to H 1F 30 priority levels 1 1 0 1 1 1 0 1 1 1 1 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 Figure 10 3 On chip Module Interrupt Priority 10 4 6 Interrupt Exception Handling and Priority Table 10 12 lists the codes for the interrupt event register INTEVT and the order of interrupt priority Each interrupt source is assigned a unique INTEVT code The start address of the exception ha...

Page 352: ... INTMSK2 15 INTMSKCLR2 15 IRL 3 0 LLLL H 0 INTMSK2 31 INTMSKCLR2 31 IRL 7 4 LLLH H 1 H 220 14 INTMSK2 14 INTMSKCLR2 14 IRL 3 0 LLLH H 1 INTMSK2 30 INTMSKCLR2 30 IRL 7 4 LLHL H 2 H 240 13 INTMSK2 13 INTMSKCLR2 13 IRL 3 0 LLHL H 2 INTMSK2 29 INTMSKCLR2 29 IRL L Low level input H High level input See table 10 11 IRL 7 4 LLHH H 3 H 260 12 INTMSK2 12 INTMSKCLR2 12 IRL 3 0 LLHH H 3 INTMSK2 28 INTMSKCLR2...

Page 353: ...NTMSK2 23 INTMSKCLR2 23 IRL 7 4 HLLH H 9 H 320 6 INTMSK2 6 INTMSKCLR2 6 IRL 3 0 HLLH H 9 INTMSK2 22 INTMSKCLR2 22 IRL L Low level input H High level input See table 10 11 IRL 7 4 HLHL H A H 340 5 INTMSK2 5 INTMSKCLR2 5 IRL 3 0 HLHL H A INTMSK2 21 INTMSKCLR2 21 IRL 7 4 HLHH H B H 360 4 INTMSK2 4 INTMSKCLR2 4 IRL 3 0 HLHH H B INTMSK2 20 INTMSKCLR2 20 IRL 7 4 HHLL H C H 380 3 INTMSK2 3 INTMSKCLR2 3 I...

Page 354: ...6 INTMSK0 28 INTMSKCLR0 28 INTREQ 28 IRQ 4 H 340 INTPRI 15 12 INTMSK0 27 INTMSKCLR0 27 INTREQ 27 IRQ 5 H 380 INTPRI 11 8 INTMSK0 26 INTMSKCLR0 26 INTREQ 26 IRQ 6 H 3C0 INTPRI 7 4 INTMSK0 25 INTMSKCLR0 25 INTREQ 25 IRQ 7 H 200 INTPRI 3 0 INTMSK0 24 INTMSKCLR0 24 INTREQ 24 Low RTC ATI H 480 INT2B1 0 High PRI H 4A0 INT2B1 1 CUI H 4C0 INT2PRI1 4 0 INT2MSKR 2 INT2MSKCR 2 INT2A0 2 INT2A1 2 INT2B1 2 Low ...

Page 355: ...0 H 740 INT2B2 2 TXI0 H 760 INT2B2 3 Low DMAC 0 DMINT4 H 780 INT2B3 4 High DMINT5 H 7A0 INT2PRI3 20 16 INT2MSKR 8 INT2MSKCR 8 INT2A0 8 INT2A1 8 INT2B3 5 Low DMAC 1 DMINT6 H 7C0 INT2B3 6 High DMINT7 H 7E0 INT2PRI3 12 8 INT2MSKR 9 INT2MSKCR 9 INT2A0 9 INT2A1 9 INT2B3 7 Low CTM CMTI H 900 INT2PRI4 28 24 INT2MSKR 12 INT2MSKCR 12 INT2A0 12 INT2A1 12 HAC HACI H 980 INT2PRI4 20 16 INT2MSKR 13 INT2MSKCR 1...

Page 356: ...5 BRI1 H BC0 INT2B2 6 TXI1 H BE0 INT2B2 7 Low SIOF SIOFI H C00 INT2PRI6 28 24 INT2MSKR 14 INT2MSKCR 14 INT2A0 14 INT2A1 14 HSPI SPII H C80 INT2PRI6 20 16 INT2MSKR 21 INT2MSKCR 21 INT2A0 21 INT2A1 21 MMCIF FSTAT H D00 INT2B5 0 High TRAN H D20 INT2PRI6 12 8 INT2MSKR 22 INT2MSKCR 22 INT2A0 22 INT2A1 22 INT2B5 1 ERR H D40 INT2B5 2 FRDY H D60 INT2B5 3 Low DMAC 1 DMINT8 H D80 INT2B3 8 High DMINT9 H DA0 ...

Page 357: ...OI1 Port E5 INT2B7 10 GPIOI2 Port H0 H FC0 INT2B7 16 GPIOI2 Port H1 INT2B7 17 GPIOI2 Port J0 INT2B7 18 GPIOI2 Port K4 INT2B7 19 GPIOI3 Port K5 H FE0 INT2B7 24 GPIOI3 Port E6 INT2B7 25 Low Low Note ITI Interval timer interrupt TUNI0 to TUNI5 TMU channels 0 to 5 under flow interrupt TICPI2 TMU channel 2 input capture interrupt DMINT0 to DMINT11 Transfer end or half end interrupts for DMAC channel 0 ...

Page 358: ... and SPC respectively At the same time R15 is saved in SGR 7 The BL MD and RB bits in SR are set to 1 8 Execution jumps to the start address of the interrupt exception handling routine the sum of the value set in the vector base register VBR and H 0000 0600 In the exception handling routine branching with the INTEVT value as an offset provides a convenient way to differentiate between the interrup...

Page 359: ...o No No No No NMI No Yes No No Yes Is NMI input low Level 15 interrupt No No No Set interrupt source code in INTEVT Save SR in SSR save PC in SPC save R15 in SGR Set SR IMASK to accepted interrupt level Branch to exception handling routine Is SR IMASK level 14 or less Level 14 interrupt Level 1 interrupt NMI Is SR IMASK level 13 or less Is SR IMASK level 0 ICR0 NMIB 1 CPUOPM INTMU 1 Figure 10 4 In...

Page 360: ...in CPUOPM is cleared to 0 use software to set the IMASK bit in SR to the same priority level as the accepted interrupt 5 Execute processing as required in response to the interrupt 6 Set the BL bit in SR to 1 7 Restore SSR and SPC from the stack 8 Execute the RTE instruction Following this procedure in the above order ensures that if further interrupts are generated an interrupt with higher priori...

Page 361: ...iority determination time 5Bcyc 2Pcyc 8Bcyc 2Pcyc 4Bcyc 2Pcyc 5Pcyc 7Pcyc Wait time until the CPU finishes the current sequence S 1 0 Icyc Interval from the start of interrupt exception handling saving SR and PC until a SuperHyway bus request is issued to fetch the first instruction of the exception handling routine 11Icyc 1Scyc Total S 10 Icyc 1Scyc 5Bcyc 2Pcyc S 10 Icyc 1Scyc 8Bcyc 2Pcyc S 10 Ic...

Page 362: ...IRQ IRL level interrupt handling 1 Writing to the GPIO register or local bus space 2 Read the address of writing Allow at least 8 bus clock cycles for cancellation and the INTC response time 1 Set the corresponding bit in INTMSK0 1 to 1 2 Set the corresponding bit in INTMSKCLR0 1 to 1 3 Read INTMSK0 1 Start of IRQ level sense or IRL level encoded interrupt IRQ IRL level interrupt handling Figure 1...

Page 363: ...ge of holding function for IRQ level sense or IRL interrupt Set the IRLM 1 0 bits and the LSH bit in ICR0 4 Start of IRL and IRQ interrupt detection Write 1 to the corresponding bit in INTMSKCLR0 and INTMSKCLR1 10 7 3 To clear IRQ and IRL interrupt requests The procedure for clearing interrupts held in the INTC is as follows To clear IRL interrupt requests When the holding function is in use ICR0 ...

Page 364: ...ding INTREQ When not using holding function ICR0 LSH 1 the interrupt request is not held but the interrupt source is set to the corresponding bit in INTREQ that is to be cleared when the CPU accepts it To clear IRQ edge detection interrupt requests To clear an IRQ edge detection interrupt request from the IRQ IRL 7 0 pins read the value 1 from the corresponding IRn n 0 to 7 bit in INTREQ and then ...

Page 365: ...6 Bus width of each area can be controlled through register settings except area 0 which is controlled by the external pin setting Wait cycle insertion by the RDY pin Wait cycle insertion can be controlled by a program Types of memory are specifiable for connection to each area Output of the control signals of memory to each area Automatic wait cycle insertion to prevent data bus collisions on con...

Page 366: ...th 32 bits Byte control SRAM interface SRAM interface with byte control Connectable areas 1 and 4 Settable bus widths 32 and 16 bits PCMCIA interface Wait cycle insertion can be controlled by a program Bus sizing function for I O bus width Little endian Connectable areas 5 and 6 Settable bus widths 16 and 8 bits Function for ATA device access Figure 11 1 shows a block diagram of the LBSC ...

Page 367: ...4 to CS6 CE2A CE2B A25 to A0 BACK BS RD FRAME R W WE3 IOWR WE2 IORD WE1 WE0 REG Area control unit Legned BCR CSnBCR CSnPCR CSnWCR Bus Control Register CSn Bus Control Register n 0 to 2 4 to 6 CSn PCMCIA Control Register n 5 6 CSn Wait Control Register n 0 to 2 4 to 6 Memory control unit CSnWCR D31 to D0 CSnBCR BCR CSnPCR SuperHyway bus Module bus Figure 11 1 LBSC Block Diagram ...

Page 368: ... also be used as CE1A to CE1B of PCMCIA R W Read Write Output Data bus input output direction designation signal Also used as PCMCIA interface write designation signal RD FRAME Read Cycle Frame Output Strobe signal indicating a read cycle FRAME signal when setting MPX interface WE0 REG Data Enable 0 Output When setting SRAM interface write strobe signal for D7 to D0 When setting PCMCIA interface R...

Page 369: ...output from channel 2 to external device which has output DREQ2 11 regarding DMA transfer request DACK3 9 10 DMA channel 3 transfer end notification Output Strobe output from channel 3 to external device which has output DREQ3 11 regarding DMA transfer request Notes 1 These pins are multiplexed with the GPIO pins 2 This pin is multiplexed with the TMU RTC and GPIO pin 3 This pin is multiplexed wit...

Page 370: ...n function of the MMU For details see section 7 Memory Management Unit MMU With the LBSC various types of memory or PC cards can be connected to each of the six areas as shown in table 11 2 and accordingly output the chip select signals CS0 to CS2 CS4 to CS6 CE2A and CE2B CS0 to CS2 are asserted when accessing areas 0 to 2 individually and CS4 to CS6 are asserted when accessing areas 4 to 6 indivi...

Page 371: ... MMU on LBSC External memory space Store queue area P4 area P0 and U0 areas 256 P1 area P2 area P3 area Store queue area P4 area Notes 1 When the MMU is off MMUCR AT 0 the top 3 bits of the 32 bit address are ignored and memory is mapped onto a fixed 29 bit external address 2 3 When the MMU is on MMUCR AT 1 the P0 U0 P3 and store queue areas can be mapped onto any external space using the TLB For ...

Page 372: ...6 32 bits and 32 bytes SRAM 8 16 32 2 Burst ROM 8 16 32 2 MPX 32 2 2 4 H 0800 0000 to H 0BFF FFFF 64 Mbytes DDR SDRAM 32 8 16 32 bits and 32 bytes 3 3 H 0C00 0000 to H 0FFF FFFF 64 Mbytes DDR SDRAM 32 8 16 32 bits and 32 bytes SRAM 8 16 32 2 Burst ROM 8 16 32 2 MPX 32 2 Byte control SRAM 16 32 2 DDR SDRAM 32 4 4 5 H 1000 0000 to H 13FF FFFF 64 Mbytes PCI 32 8 16 32 bits and 32 bytes SRAM 8 16 32 2...

Page 373: ...Controller PCIC 6 With the PCMCIA interface the bus width is either 8 bits or 16 bits 7 Area 7 is a reserved area If a reserved area is accessed correct operation cannot be guaranteed 8 If 8 or 16 bytes access transfer by another LSI internal bus master module is being executed the LBSC is executing two or four times 32 bit access individually Area 0 H 0000 0000 Area 1 H 0400 0000 Area 2 H 0800 00...

Page 374: ...ther the SRAM or ROM interface is used in areas 1 to 2 and 4 to 6 a bus width of 8 16 or 32 bits can be selected through the CSn bus control register CSnBCR When the burst ROM interface is used a bus width of 8 16 or 32 bits can be selected When the byte control SRAM interface is used a bus width of 16 or 32 bits can be selected When the MPX interface is used a bus width of 32 bits should be selec...

Page 375: ...or areas 5 and 6 in the external memory space The IC memory card interface and I O card interface prescribed in JEIDA specifications version 4 2 PCMCIA2 1 are supported Both the IC memory card interface and the I O card interface are supported in areas 5 and 6 in the external memory space The PCMCIA interface is only supported in little endian mode Table 11 5 PCMCIA Interface Features Item Feature...

Page 376: ...0 A11 I Address A11 I Address A11 11 A9 I Address A9 I Address A9 12 A8 I Address A8 I Address A8 13 A13 I Address A13 I Address A13 14 A14 I Address A14 I Address A14 15 WE I Write enable WE I Write enable WE1 16 READY O Ready IREQ O Interrupt request Sensed on port 17 VCC Operation power supply VCC Operation power supply 18 VPP1 VPP Programming power supply VPP1 VPP Programming peripheral power ...

Page 377: ...I O Data D13 I O Data D13 40 D14 I O Data D14 I O Data D14 41 D15 I O Data D15 I O Data D15 42 CE2 I Card enable CE2 I Card enable CE2A or CE2B 43 RFSH VS1 I Refresh request RFSH VS1 I Refresh request Output from port 44 RSRVD Reserved IORD I I O read IORD 45 RSRVD Reserved IOWR I I O write IOWR 46 A17 I Address A17 I Address A17 47 A18 I Address A18 I Address A18 48 A19 I Address A19 I Address A1...

Page 378: ...memory space select REG 62 BVD2 O Battery voltage detection SPKR O Digital voice signal Sensed on port 63 BVD1 O Battery voltage detection STSCHG O Card status change Sensed on port 64 D8 I O Data D8 I O Data D8 65 D9 I O Data D9 I O Data D9 66 D10 I O Data D10 I O Data D10 67 CD2 O Card detection CD2 O Card detection Sensed on port 68 GND Ground GND Ground Notes 1 I O means input output on the si...

Page 379: ...S2BCR R W H FF80 2020 H 1F80 2020 32 CS4 Bus Control Register CS4BCR R W H FF80 2040 H 1F80 2040 32 CS5 Bus Control Register CS5BCR R W H FF80 2050 H 1F80 2050 32 CS6 Bus Control Register CS6BCR R W H FF80 2060 H 1F80 2060 32 CS0 Wait Control Register CS0WCR R W H FF80 2008 H 1F80 2008 32 CS1 Wait Control Register CS1WCR R W H FF80 2018 H 1F80 2018 32 CS2 Wait Control Register CS2WCR R W H FF80 20...

Page 380: ...ned Retained CS4 Bus Control Register CS4BCR H 7777 7770 Retained Retained CS5 Bus Control Register CS5BCR H 7777 7770 Retained Retained CS6 Bus Control Register CS6BCR H 7777 7770 Retained Retained CS0 Wait Control Register CS0WCR H 7777 770F Retained Retained CS1 Wait Control Register CS1WCR H 7777 770F Retained Retained CS2 Wait Control Register CS2WCR H 7777 770F Retained Retained CS4 Wait Con...

Page 381: ...register is initialized by a power on reset or a manual reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AREASEL R W R W R W R R R R R R R R R R R R R Bit Initial value R W Bit Bit Name Initial Value R W Des...

Page 382: ...00 0000 to H 13FF FFFF as the PCI memory space and other areas as the LBSC space 100 Sets areas 2 to 5 H 0800 0000 to H 17FF FFFF as the DDRIF space 101 Setting prohibited 110 Setting prohibited 111 Setting prohibited The MMSELR must be written by the CPU Writing to MMSELR the DMAC or PCIC module must be set not to access to any resources and all processing should be finished for example the SYNCO...

Page 383: ...0 0 0 0 0 1 0 DMA BST BREQ EN DACKBST 3 0 OPUP DPUP END IAN R W R W R R R W R W R W R W R W R R W R R R R W R Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ASYNC 6 0 HIZ CNT R W R W R W R W R W R W R W R R R R R R R R R W Bit Initial value R W Note The intial value of the endian bit bit 31 depends on the MODE5 pin setting Bit Bit Name Initial Value R W...

Page 384: ...ue should always be 0 24 OPUP 0 R W Control Output Pin Pull Up Resistor Control Specifies the pull up resistor state A25 to A0 BS CS0 to CS2 CS4 to CS6 RD FRAME WE R W CE2A and CE2B when the control output pins are high impedance This bit is initialized by a power on reset 0 Pull up resistors are on for control output pins A25 to A0 BS CS0 to CS2 CS4 to CS6 RD FRAME WE R W CE2A and CE2B 1 Pull up ...

Page 385: ...e transfers by the DMAC When this bit is cleared to 0 the priority is as follows bus release DMAC burst mode CPU DMAC PCIC When this bit is set to 1 the bus release is not performed until completion of the DMAC burst transfer This bit is initialized at a power on reset 0 DMAC burst mode transfer priority setting off 1 DMAC burst mode transfer priority setting on 15 0 R Reserved This bit is always ...

Page 386: ...tinue to drive the data bus immediately after the read signal is inactivated Therefore a data bus collision may occur when there is consecutive memory access to different areas or writing to a memory immediately after reading This LSI automatically inserts the number of idle cycles set by CSnBCR to prevent data bus collision CSnBCR is initialized to H 7777 7770 by a power on reset but is not initi...

Page 387: ...erted 010 2 idle cycles inserted 011 3 idle cycles inserted 100 4 idle cycles inserted 101 5 idle cycles inserted 110 6 idle cycles inserted 111 7 idle cycles inserted 27 0 R Reserved This bit is always read as 0 The write value should always be 0 26 to 24 IWRWD 111 R W Idle Cycles between Read Write to Different Spaces Specify the number of idle cycles to be inserted after an access to a memory c...

Page 388: ...erted 010 2 idle cycles inserted 011 3 idle cycles inserted 100 4 idle cycles inserted 101 5 idle cycles inserted 110 6 idle cycles inserted 111 7 idle cycles inserted 19 0 R Reserved This bit is always read as 0 The write value should always be 0 18 to 16 IWRRD 111 R W Idle Cycles between Read Read to Different Spaces Specify the number of idle cycles to be inserted after an access to a memory co...

Page 389: ... section 11 5 8 Wait Cycles between Accesses 000 No idle cycle inserted 001 1 idle cycle inserted 010 2 idle cycles inserted 011 3 idle cycles inserted 100 4 idle cycles inserted 101 5 idle cycles inserted 110 6 idle cycles inserted 111 7 idle cycles inserted 11 10 BST 01 R W Burst Length When a burst ROM interface is used these bits specify the number of accesses in a burst The MPX interface is n...

Page 390: ...timing When setting this bit to 1 specify the number of RD negation CSn negation delay cycles as 1 or more by setting the RDH bit in CSnWCR Also the RD negation CSn negation delay cycle is reduced by 1 cycle when this bit is set to 1 Available only when the SRAM interface or byte control SRAM interface 0 No hold cycle inserted 1 1 hold cycle inserted 6 to 4 BW 111 R W Burst Pitch When the burst RO...

Page 391: ...selected Note The MPX bit in CS0BCR is read only 2 to 0 TYPE 000 R W Memory Type Setting Specify the type of memory connected to the space 000 SRAM Initial value 001 SRAM with byte control 1 010 Burst ROM burst at read SRAM at write 011 Reserved Setting prohibited 100 PCMCIA 2 101 Reserved Setting prohibited 110 Reserved Setting prohibited 111 Reserved Setting prohibited Note 1 Setting possible on...

Page 392: ...RDH RDS ADH ADS R W R W R W R R W R W R W R R W R W R W R R W R W R R W Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 1 1 1 1 0 0 0 0 1 1 1 0 1 1 0 1 IW 3 0 BSH WTH WTS R W R W R W R W R W R W R W R R W R W R W R W R W R W R R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 0 R Reserved This bit is always read as 0 The write value should always be 0 30 to 28 ADS...

Page 393: ...inserted 001 1 cycle inserted 010 2 cycles inserted 011 3 cycles inserted 100 4 cycles inserted 101 5 cycles inserted 110 6 cycles inserted 111 7 cycles inserted 23 0 R Reserved This bit is always read as 0 The write value should always be 0 22 to 20 RDS 111 R W RD Setup Cycle CSn Assertion RD Assertion Delay Cycle Specify the number of cycles to be inserted form CSn assertion to RD assertion Avai...

Page 394: ... cycle inserted 001 1 cycle inserted 010 2 cycles inserted 011 3 cycles inserted 100 4 cycles inserted 101 5 cycles inserted 110 6 cycles inserted 111 7 cycles inserted 15 0 R Reserved This bit is always read as 0 The write value should always be 0 14 to 12 WTS 111 R W WE Setup Cycle CSn Assertion WE Assertion Delay Cycle Specify the number of cycles to be inserted from CSn assertion to WE asserti...

Page 395: ...erted 001 1 cycle inserted 010 2 cycles inserted 011 3 cycles inserted 100 4 cycles inserted 101 5 cycles inserted 110 6 cycles inserted 111 7 cycles inserted 7 0 R Reserved This bit is always read as 0 The write value should always be 0 6 to 4 BSH 000 R W BS Hold Cycle Specify the number of cycles for the BS assertion Total access cycle number is not change by setting these bits This setting is v...

Page 396: ...nserted 1100 15 cycles inserted 0101 5 cycles inserted 1101 17 cycles inserted 0110 6 cycles inserted 1110 21 cycles inserted 0111 7 cycles inserted 1111 25 cycles inserted When the MPX interface is selected the following cycles are inserted by the setting value of IW 2 0 and then IW3 setting is invalid And the external wait cycle insertion by using the RDY pin monitor can be used in all the follo...

Page 397: ...ulse widths of OE and WE assertion for the first half of area 5 and 6 are set using the IW bits in CSnWCR CSnPCR is initialized to H 7700 0000 by a power on reset but is not initialized by a manual reset 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 1 1 1 0 1 1 0 1 PCIW PCWA PCWB SAB SAA R W R W R W R W R W R W R W R W R W R W R W R R W R W R R W Bit Initial value R W 0 1 2 3 4 5...

Page 398: ... 23 22 PCWA 00 R W PCMCIA Wait A Wait cycle for low speed PCMCIA The number of wait cycles specified by these bits is added to the number designated by the IW bits in CSnWCR These bits are valid when the access area of PCMCIA interface is first half of area n n 5 and 6 00 No wait cycle inserted 01 15 wait cycles inserted 10 30 wait cycles inserted 01 50 wait cycles inserted 21 20 PCWB 00 R W PCMCI...

Page 399: ... 0001 1 cycle inserted 0010 2 cycles inserted 0011 3 cycles inserted 0100 4 cycles inserted 0101 5 cycles inserted 0110 6 cycles inserted 0111 7 cycles inserted 1000 8 cycles inserted 1001 9 cycles inserted 1010 11 cycles inserted 1011 13 cycles inserted 1100 15 cycles inserted 1101 17 cycles inserted 1110 21 cycles inserted 1111 25 cycles inserted Note Specify the number of wait cycle designated ...

Page 400: ...inserted 101 9 wait cycles inserted 110 12 wait cycles inserted 111 15 wait cycles inserted 11 0 R Reserved This bit is always read as 0 The write value should always be 0 10 to 8 TEDB 000 R W OE WE Assert Delay B These bits set the delay time from address output to OE WE assertion for the access of second half area of PCMCIA interface area n n 5 and 6 000 No wait cycle inserted 001 1 wait cycle i...

Page 401: ...wait cycles inserted 100 6 wait cycles inserted 101 9 wait cycles inserted 110 12 wait cycles inserted 111 15 wait cycles inserted 3 0 R Reserved This bit is always read as 0 The write value should always be 0 2 to 0 TEHB 000 R W OE WE Negation Address Delay B These bits set the delay time from OE WE negation to address hold for the access of second half area of PCMCIA interface area n n 5 and 6 0...

Page 402: ...data bus width is smaller than the access size multiple bus cycles are automatically generated to reach the access size In this case access is performed by incrementing the addresses corresponding to the bus width For example when a longword access is performed at the area with an 8 bit width in the SRAM interface each address is incremented one by one and then access is performed four times In th...

Page 403: ...sert Word 4n 1 Data 15 to 8 Data 7 to 0 Assert Assert 4n 2 1 Data 15 to 8 Data 7 to 0 Assert Assert Longword 4n 1 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Assert Assert Assert Assert Table 11 10 16 Bit External Device Big Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3 WE2 WE1 WE0 Byte 2n 1 Data 7 to...

Page 404: ...n Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3 WE2 WE1 WE0 Byte n 1 Data 7 to 0 Assert Word 2n 1 Data 15 to 8 Assert 2n 1 2 Data 7 to 0 Assert Longword 4n 1 Data 31 to 24 Assert 4n 1 2 Data 23 to 16 Assert 4n 2 3 Data 15 to 8 Assert 4n 3 4 Data 7 to 0 Assert ...

Page 405: ...sert Word 4n 1 Data 15 to 8 Data 7 to 0 Assert Assert 4n 2 1 Data 15 to 8 Data 7 to 0 Assert Assert Longword 4n 1 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Assert Assert Assert Assert Table 11 13 16 Bit External Device Little Endian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3 WE2 WE1 WE0 Byte 2n 1 Data 7...

Page 406: ...ian Access and Data Alignment Operation Data Bus Strobe Signals Access Size Address No D31 to D24 D23 to D16 D15 to D8 D7 to D0 WE3 WE2 WE1 WE0 Byte n 1 Data 7 to 0 Assert Word 2n 1 Data 7 to 0 Assert 2n 1 2 Data 15 to 8 Assert Longword 4n 1 Data 7 to 0 Assert 4n 1 2 Data 15 to 8 Assert 4n 2 3 Data 23 to 16 Assert 4n 3 4 Data 31 to 24 Assert ...

Page 407: ...n be inserted in each bus cycle through the external wait pin RDY When the insert number is 0 the RDY signal is ignored When the burst ROM interface is used the number of transfer cycles for a burst cycle is selected from a range of 2 to 9 according to the number of wait cycles The setup time and hold time cycle number of the address and CS0 signals to the read and write strobe signals can be set ...

Page 408: ... this area are the SRAM burst ROM MPX and DDR SDRAM interfaces When the SRAM interface is used a bus width of 8 16 or 32 bits is selectable with bits SZ in CS2BCR When the MPX interface is used a bus width of 32 bits should be selected through bits SZ in CS2BCR When area 2 is accessed the CS2 signal is asserted except for DDR SDRAM area In the case where the SRAM interface is set the RD signal whi...

Page 409: ...where the SRAM interface is set the RD signal which can be used as OE and write control signals WE0 to WE3 are asserted For the number of bus cycles 0 to 25 wait cycles inserted by CS4WCR can be selected Any number of wait cycles can be inserted in each bus cycle through the external wait pin RDY When the insert number is 0 the RDY signal is ignored The setup time and hold time cycle number of the...

Page 410: ...be signals can be set within a range of 0 to 7 cycles by CS5WCR The BS hold cycles can be set within a range of 0 to 1 when the number for the read and write strobe setup wait is 1 or more For the PCMCIA interface the setup time of addresses to the read write strobe signals CE1A and CE2A can be specified within a range from 0 to 15 cycles through bits TEDA B2 to TEDA B0 and TEDA B to TEHA B in CS5...

Page 411: ...it cycles can be specified within a range from 0 to 50 cycles by bits PCWA B1 and PCWA B0 The number of wait cycles specified by CS6PCR is added to the value specified by IW3 to IW0 in CS6WCR or PCIW3 to PCIW0 in CS6PCR 11 5 3 SRAM interface 1 Basic Timing The strobe signals for the SRAM interface of this LSI are output primarily based on the SRAM connection Figure 11 4 shows the basic timing of t...

Page 412: ...362 of 1286 REJ09B0158 0100 accesses are performed in wraparound method according to the set bus width The bus is not released during this transfer T1 CLKOUT A25 to A0 CSn R W RD D31 to D0 read WE D31 to D0 write BS T2 RDY DACK Figure 11 4 Basic Timing of SRAM Interface ...

Page 413: ...show examples of the connection to SRAM with data width of 32 16 and 8 bits A16 A0 CS OE I O7 I O0 WE A18 A2 CSn RD D31 D24 WE3 D23 D16 WE2 D15 D8 WE1 D7 D0 WE0 SH7780 128 K 8 bit SRAM A16 A0 CS OE I O7 I O0 WE A16 A0 CS OE I O7 I O0 WE A16 A0 CS OE I O7 I O0 WE Figure 11 5 Example of 32 Bit Data Width SRAM Connection ...

Page 414: ...roller LBSC Rev 1 00 Dec 13 2005 Page 364 of 1286 REJ09B0158 0100 A16 A0 CS OE I O7 I O0 WE A17 SH7780 A1 CSn RD D15 D8 WE1 D7 D0 WE0 A16 A0 CS OE I O7 I O0 WE 128 K 8 bit SRAM Figure 11 6 Example of 16 Bit Data Width SRAM Connection ...

Page 415: ...ocal Bus State Controller LBSC Rev 1 00 Dec 13 2005 Page 365 of 1286 REJ09B0158 0100 A16 A0 CSn RD D7 D0 WE0 A16 A0 CS OE I O7 I O0 WE SH7780 128 K 8 bit SRAM Figure 11 7 Example of 8 Bit Data Width SRAM Connection ...

Page 416: ... 0 a software wait is inserted in accordance with the wait control bits For details see section 11 4 4 CSn Wait Control Register CSnWCR A specified number of Tw cycles is inserted as wait cycles in accordance with the CSnWCR setting The insertion timing of the wait cycle is shown in figure 11 8 T1 CLKOUT A25 to A0 CSn R W RD D31 to D0 read WE D31 to D0 write BS Tw T2 RDY DACK Figure 11 8 SRAM Inte...

Page 417: ... cycle is specified as a software wait The RDY signal is sampled at the transition from the Tw state to the T2 state Therefore the assertion of the RDY signal has no effect in the T1 cycle or in the first Tw cycle The RDY signal is sampled on the rising edge of the clock T1 CLKOUT A25 to A0 CSn R W RD read D31 to D0 read WE write D31 to D0 write BS Tw Twe T2 RDY DACK Figure 11 9 SRAM Interface Wai...

Page 418: ...ead Strobe Negate Timing When the SRAM interface is used the negation timing of the strobe signal during a read operation can be specified through the RDSPL bit in CSnBCR For details of settings see section 11 4 3 CSn Bus Control Register CSnBCR Clear the RDSPL bit to 0 when using a byte control SRAM ...

Page 419: ...CSn Negation delay cycle RD Hold cycle CSnWCR RDH 0 to 7 cycles TAS1 Address Setup cycle CSnWCR ADS 0 to 7 cycles TW Insert wait cycle CSnWCR IW 0 to 25 cycles TAH1 Address Hold cycle CSnWCR ADH 0 to 7 cycles TS1 CSn assertion WE assertion delay cycle WE Setup cycle CSnWCR WTS 0 to 7 cycles TAS1 Address Setup cycle CSnWCR ADS 0 to 7 cycles TW Insert wait cycle CSnWCR IW 0 to 25 cycles CLKOUT CLKOU...

Page 420: ... or 16 accesses can be set when 32 bit ROM is used 4 or 8 accesses can be set The RDY signal is always sampled when one or more wait cycles are set Even when no wait is specified in the burst ROM settings two access cycles are inserted in the second and subsequent accesses as shown in figure 11 12 A writing operation for this interface is performed in the same way as for the SRAM interface In a 32...

Page 421: ... REJ09B0158 0100 T1 TB1 TB2 TB1 TB2 TB1 TB2 T2 CLKOUT A25 to A5 A4 to A0 CSn R W RD D31 to D0 read BS RDY Figure 11 11 Burst ROM Basic Timing T1 Twe TB2 TB1 Tw TB2 Tw Tw TB1 TB2 Tw T2 TB1 CLKOUT A25 to A5 A4 to A0 CSn R W RD D31 to D0 read BS RDY Figure 11 12 Burst ROM Wait Timing ...

Page 422: ...ig endian mode is not explicitly stipulated in the JEIDA PCMCIA standard this LSI supports the PCMCIA interface only in little endian mode through little endian mode setting The PCMCIA interface can select the space property from among 8 bit common memory 16 bit common memory 8 bit attribute memory 16 bit attribute memory 8 bit I O space 16 bit I O space dynamic I O bus sizing and ATA complement m...

Page 423: ... there was an access request and the remaining accesses are performed in wraparound method according to the set bus width The bus is not released during this transfer ATA complement mode is to access the ATA device register connected to this LSI The Device Control Register Alternate Status Register Data Register and Data Port can be accessed in ATA complement mode To access the Device Control Regi...

Page 424: ...of DMA transfer times 4 DMA transfer size word 16 bit xx 1A 1B 2A 2B Figure 11 14 CExx and DACK Output of ATA Complement Mode in DMA Transfer Figure 11 15 shows an example of PCMCIA card connection to this LSI To enable hot insertion of PCMCIA cards i e insertion or removal while system power is being supplied a three state buffer must be connected between this LSI bus interface and the PCMCIA car...

Page 425: ...L H Invalid Upper write data Odd 16 Read 8 Even H L L Invalid Read data Odd L H H Read data Invalid 16 Even L L L Upper read data Lower read data Odd Write 8 Even H L L Invalid Write data Odd L H H Write data Invalid 16 Even L L L Upper write data Lower write data Odd Read 8 Even L H L L Invalid Read data Odd L L H H Read data Invalid Dynamic Bus Sizing 2 16 Even L L L L Upper read data Lower read...

Page 426: ...Upper read data Lower read data read does not output DACK Odd 8 Even L H L Invalid Write data Odd 16 Even H L L Upper write data Lower write data write does not output DACK Odd 8 Even H H L Invalid Read data Odd H H L Read data Invalid 16 Even H H H Upper read data Lower read data read outputs DACK Odd 8 Even H H L Invalid Write data Odd H H L Write data Invalid 16 Even H H H Upper write data Lowe...

Page 427: ...IOWR IOIS16 WAIT A25 to A0 D15 to D0 CD1 CD2 CE1 CE2 OE WE PGM WAIT A25 to A0 D15 to D0 R W CE2B CE2A RD WE1 CE1B CS6 CE1A CS5 IORD IOWR RDY IOIS16 G DIR D7 to D0 D15 to D8 D7 to D0 D15 to D8 G DIR G G G DIR G DIR REG REG REG PC card Memory I O PC card Memory Card detection circuit Card detection circuit SH7780 Figure 11 15 Example of PCMCIA Interface ...

Page 428: ...sic Timing Figure 11 16 shows the basic timing for the PCMCIA memory card interface and figure 11 17 shows the wait timing for the PCMCIA memory card interface CLKOUT Tpcm1 Tpcm2 A25 to A0 CExx R W D15 to D0 read D15 to D0 write RD read WE1 write BS RDY DACK REG WE0 Figure 11 16 Basic Timing for PCMCIA Memory Card Interface ...

Page 429: ...1 00 Dec 13 2005 Page 379 of 1286 REJ09B0158 0100 CLKOUT Tpcm0 A25 to A0 R W CExx RD WE1 BS RDY REG WE0 read D15 to D0 read D15 to D0 write write DACK Tpcm0w Tpcm1 Tpcm1w Tpcm1we Tpcm2 Tpcm2w Figure 11 17 Wait Timing for PCMCIA Memory Card Interface ...

Page 430: ...IOIS16 signal is high during the word size I O bus cycle the I O port is recognized as eight bits in bus width In this case a data access for only eight bits is performed in the I O bus cycle being executed and this is automatically followed by a data access for the remaining eight bits Dynamic bus sizing is also performed for byte size access to address 2n 1 Figure 11 20 shows the basic timing fo...

Page 431: ...00 Dec 13 2005 Page 381 of 1286 REJ09B0158 0100 CLKOUT A25 to A0 R W CExx IORD read IOWR write DACK D15 D0 read D15 to D0 write BS RDY IOIS16 Tpci0 Tpci0w Tpci1 Tpci1we Tpci1w Tpci2 Tpci2w REG WE0 Figure 11 19 Wait Timing for PCMCIA I O Card Interface ...

Page 432: ...2 of 1286 REJ09B0158 0100 Tpci Tpci0 Tpci1w Tpci2 Tpci2w Tpci0 Tpci Tpci2 Tpci1w Tpci2w CLKOUT A25 to A1 A0 R W IORD WE2 read IOWR WE3 write D15 to D0 write D15 to D0 read BS IOIS16 CExx REG WE0 RDY DACK Figure 11 20 Dynamic Bus Sizing Timing for PCMCIA I O Card Interface ...

Page 433: ... cycle does not occur in the case of minimum pitch access The FRAME signal is asserted at the rising edge in Tm1 and negated at the start of the last data transfer cycle in the data phase Therefore an external device for the MPX interface must internally store the address information and access size output in the address phase and perform data input output for the data phase For details see sectio...

Page 434: ...terface timing is shown below When the MPX interface is used for areas 1 2 and 4 to 6 a bus size of 32 bits should be specified by CSnBCR In wait control either waits by CSnWCR or waits by the RDY pin can be inserted In a read one wait cycle is automatically inserted after address output even if CSnWCR is cleared to 0 Tm1 CLKOUT RD FRAME CSn R W D31 to D0 BS Tmd1w Tmd1 RDY DACK D0 A Figure 11 22 M...

Page 435: ...0100 Tm1 CLKOUT RD FRAME CSn R W D31 to D0 BS Tmd1w Tmd1we Tmd1 RDY DACK D0 A Figure 11 23 MPX Interface Timing 2 Single Read IW 0 One External Wait Inserted Tm1 CLKOUT RD FRAME CSn R W D31 to D0 BS Tmd1 RDY DACK D0 A Figure 11 24 MPX Interface Timing 3 Single Write Cycle IW 0 No External Wait ...

Page 436: ... Tmd1w Tmd1we Tmd1 RDY DACK D0 A Figure 11 25 MPX Interface Timing 4 Single Write Cycle IW 1 One External Wait Inserted Tm1 CLKOUT RD FRAME CSn R W D31 to D0 BS Tmd1w Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 RDY DACK D2 D3 D4 D6 D7 D8 D5 D1 A Figure 11 26 MPX Interface Timing 5 Burst Read Cycle IW 0 No External Wait 32 Byte Data Transfer ...

Page 437: ...Tmd3 Tmd7 Tmd8we Tmd8 RDY DACK D7 D8 D2 D3 D1 A Figure 11 27 MPX Interface Timing 6 Burst Read Cycle IW 0 External Wait Control 32 Byte Data Transfer Tm1 CLKOUT RD FRAME CSn R W D31 to D0 BS Tmd1 Tmd2 Tmd3 Tmd4 Tmd5 Tmd6 Tmd7 Tmd8 RDY DACK D1 D2 D3 D4 D5 D6 D7 D8 A Figure 11 28 MPX Interface Timing 7 Burst Write Cycle IW 0 No External Wait 32 Byte Data Transfer ...

Page 438: ... 13 2005 Page 388 of 1286 REJ09B0158 0100 Tm1 CLKOUT RD FRAME CSn R W D31 to D0 BS Tmd1w Tmd1 Tmd2we Tmd2 Tmd3 Tmd7 Tmd8we Tmd8 RDY DACK D3 D2 D1 D7 D8 A Figure 11 29 MPX Interface Timing 8 Burst Write Cycle IW 1 External Wait Control 32 Byte Data Transfer ...

Page 439: ... only the WE signal for the byte being read is asserted Assertion is synchronized with the falling edge of the CLKOUT clock in the same way as for the WE signal while negation is synchronized with the rising edge of the CLKOUT clock in the same way as for the RD signal In 32 byte transfer a total of 32 bytes are transferred continuously according to the set bus width The first access is performed ...

Page 440: ... 11 Local Bus State Controller LBSC Rev 1 00 Dec 13 2005 Page 390 of 1286 REJ09B0158 0100 T1 T2 CLKOUT A25 to A0 CSn R W RD D31 to D0 read BS DACK RDY WE Figure 11 31 Byte Control SRAM Basic Read Cycle No Wait ...

Page 441: ...Bus State Controller LBSC Rev 1 00 Dec 13 2005 Page 391 of 1286 REJ09B0158 0100 T1 Tw T2 CLKOUT A25 to A0 CSn R W RD D31 to D0 read BS DACK RDY WE Figure 11 32 Byte Control SRAM Basic Read Cycle One Internal Wait Cycle ...

Page 442: ...e Controller LBSC Rev 1 00 Dec 13 2005 Page 392 of 1286 REJ09B0158 0100 T1 Tw Twe T2 CLKOUT A25 to A0 CSn R W RD D31 to D0 read BS DACK RDY WE Figure 11 33 Byte Control SRAM Basic Read Cycle One Internal Wait One External Wait ...

Page 443: ...n when the next access is started The process for wait cycle insertion consists of inserting idle cycles between the access cycles as shown in section 11 4 3 CSn Bus Control Register CSnBCR If bits IWW IWRWD IWRWS IWRRD and IWRRS in CSnBCR n 0 to 2 and 4 to 6 are used to set the number of idle cycles between accesses the number of inserted idle cycles is only the specified number of idle cycles mi...

Page 444: ...8 0100 T1 CLKOUT CSm CSn A25 to A0 BS R W RD D31 to D0 T2 Twait T1 T2 Twait T1 T2 Area m space read Area m n access wait specification m n m n 0 to 2 4 to 6 Area n inter access wait specification Area n space read Area n space write IWRRD IWRWS Figure 11 34 Wait Cycles between Access Cycles ...

Page 445: ...tput buffer on the side receiving the bus simultaneously with respect to the bus control signals it is possible to eliminate the signal high impedance period It is not necessary to provide the pull up resistors usually inserted in these control signal lines to prevent incorrect operation due to external noise in the high impedance state Bus transfer is executed between bus cycles When the bus rele...

Page 446: ... 13 2005 Page 396 of 1286 REJ09B0158 0100 CLKOUT BREQ BACK CSn RD WE A25 to A0 BS D31 to D0 write R W HiZ HiZ HiZ HiZ HiZ HiZ HiZ Master access Master access Slave access Asserted for least 2 cycles Negated within 2 cycles Figure 11 35 Arbitration Sequence ...

Page 447: ... high impedance state These bus control signals are negated no later than one cycle before going to high impedance Bus request signal sampling is performed on the rising edge of the clock The sequence for re acquiring the bus from the slave is as follows As soon as BREQ negation is detected on the rising edge of the clock BACK is negated and bus control signal driving is started Driving of the add...

Page 448: ...that the source address is out of the LBSC space and the destination address is in the LBSC space and the LCKN bit in CHCR is cleared to 0 the bus is released in the cycle between read access and write access CSn BREQ BACK DMAC CHCR LCKN 0 Source address LBSC space Destination address LBSC space DMA read access to the LBSC space DMA write access to the LBSC space CSn BREQ BACK DMAC CHCR LCKN 0 Sou...

Page 449: ...hen designing an application system that includes the SH7780 all control including initialization and low power consumption control are supposed to be carried out by the SH7780 In a power on reset the SH7780 will not accept bus requests from the slave until the BREQ enable bit BCR BREQEN is set to 1 To ensure that the slave processor does not access memory requiring initialization before use write...

Page 450: ...Section 11 Local Bus State Controller LBSC Rev 1 00 Dec 13 2005 Page 400 of 1286 REJ09B0158 0100 ...

Page 451: ...h of two Connectable memory sizes 256 Mbits 512 Mbits 1 Gbit and 2 Gbits Address bit width bits of supported memory configurations are as listed below DDR SDRAM data bus width is 32 bits Parallel connection of two 128 Mbit DDR SDRAMs 16 Total Size 256 Mbits Parallel connection of two 256 Mbit DDR SDRAMs 16 Total Size 512 Mbits Parallel connection of two 512 Mbit DDR SDRAMs 16 Total Size 1 Gbit Par...

Page 452: ...timing register SuperHyway bus interface DDR controller DDR I O Transfer request controller Command write data output and control register Control register Read data register controller SCR SDMR MIM SDR STR DBK Control register synchronizer Synchronizing for internal process MCLK From CPG module DDRIF Read data register synchronizer SuperHyway bus internal bus SuperHyway request receiver SuperHywa...

Page 453: ...is set high the clock signal is active When this pin is set low the clock signal is inactive MCS Chip select Output Chip select output MWE Write enable Output Write enable output MA13 to MA0 Address Output Row column address BA1 BA0 Bank address Output Bank address output MD31 to MD0 Data I O Data I O MDQS3 to MDQS0 I O data strobe I O I O data strobe MDQM3 to MDQM0 Data mask Output I O data mask ...

Page 454: ...in MMSELR for the 29 bit address mode gives the DDRIF control of not only area 3 but also areas 2 4 and 5 which are also within the 29 bit address range The DDRIF can control a total of 4 areas with a maximum capacity of 256 Mbytes as the external DDR SDRAM memory space In the case of the 32 bit address extended mode the DDRIF controls not only area 3 and with some settings area 2 4 and 5 within t...

Page 455: ...RIF 3 DDRIF 1 DDRIF 2 DDRIF 3 DDRIF 1 DDRIF 0 DDRIF 2 DDRIF 3 DDRIF 0 DDRIF 2 DDRIF 1 DDRIF 3 DDRIF 0 DDRIF 1 DDRIF 0 DDRIF 2 DDRIF 3 DDRIF 1 DDRIF 2 DDRIF 3 DDRIF 1 DDRIF 0 DDRIF 2 DDRIF 3 DDRIF 0 DDRIF 2 DDRIF 1 DDRIF 3 DDRIF 0 DDRIF 1 DDRIF 0 DDRIF 2 DDRIF 3 DDRIF 1 DDRIF 2 DDRIF 3 DDRIF 1 DDRIF 0 DDRIF 2 DDRIF 3 DDRIF 0 DDRIF 2 DDRIF 1 DDRIF 3 DDRIF 0 DDRIF 1 Undefined DDR SDRAM DDRIF Shadow P...

Page 456: ...e access at address 7 Bit 7 to 0 Word access at address 0 Bit 15 to 8 Bit 7 to 0 Word access at address 2 Bit 15 to 8 Bit 7 to 0 Word access at address 4 Bit 15 to 8 Bit 7 to 0 Word access at address 6 Bit 15 to 8 Bit 7 to 0 Longword access at address 0 Bit 31 to 24 Bit 23 to 16 Bit 15 to 8 Bit 7 to 0 Longword access at address 4 Bit 31 to 24 Bit 23 to 16 Bit 15 to 8 Bit 7 to 0 Quadword access at ...

Page 457: ...12 H C Bit 31 to 24 Bit 23 to 16 Bit 15 to 8 Bit 7 to 0 32 byte access at address 0 fourth round from address 8 Bit 31 to 24 Bit 23 to 16 Bit 15 to 8 Bit 7 to 0 32 byte access at address 0 fifth round from address 20 H 14 Bit 31 to 24 Bit 23 to 16 Bit 15 to 8 Bit 7 to 0 32 byte access at address 0 sixth round from address 16 H 10 Bit 31 to 24 Bit 23 to 16 Bit 15 to 8 Bit 7 to 0 32 byte access at a...

Page 458: ...access at address 6 Bit 15 to 8 Bit 7 to 0 Longword access at address 0 Bit 31 to 24 Bit 23 to 16 Bit 15 to 8 Bit 7 to 0 Longword access at address 4 Bit 31 to 24 Bit 23 to 16 Bit 15 to 8 Bit 7 to 0 Quadword access at address 0 first round from address 0 Bit 63 to 56 Bit 55 to 48 Bit 47 to 40 Bit 39 to 32 Quadword access at address 0 second round from address 4 Bit 31 to 24 Bit 23 to 16 Bit 15 to ...

Page 459: ...Bit 15 to 8 Bit 7 to 0 32 byte access at address 0 sixth round from address 20 H 14 Bit 31 to 24 Bit 23 to 16 Bit 15 to 8 Bit 7 to 0 32 byte access at address 0 seventh round from address 24 H 18 Bit 31 to 24 Bit 23 to 16 Bit 15 to 8 Bit 7 to 0 32 byte access at address 0 eighth round from address 28 H 1C Bit 31 to 24 Bit 23 to 16 Bit 15 to 8 Bit 7 to 0 Bit 31 Time sequence Example of memory addre...

Page 460: ...ten to the register will be reflected correctly A longword read from the register will contain the value in the corresponding half of the register at the time of reading Whether the current endian is big or little specify the address listed below to access bits 63 to 32 To access bits 31 to 0 specify the address listed below 4 Table 12 4 Register Configuration Register Name Abbreviation R W P4 Add...

Page 461: ...SCR H 0000 0000 0000 0000 H 0000 0000 0000 0000 Retained DDR SDRAM timing register STR H 0000 0000 0000 0000 H 0000 0000 0000 0000 Retained DDR SDRAM row attribute register SDR H 0000 0000 0000 0100 H 0000 0000 0000 0100 Retained DDR SDRAM mode register SDMR DDR SDRAM back up register DBK H 0000 0000 0000 000x 2 H 0000 0000 0000 000x 2 Retained Notes 1 The initial value of bit 8 ENDIAN bit depends...

Page 462: ... R R R R R Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W 32 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 BOMODE PC KE SEL FS RM ODE R R W R R R R R R R R R R R W R R W R W Bit Initial value R W Note Depends on the setting of external pin MODE5 Bit Bit Name Initial Value R W Description 63 to 48 All 0 R Reserved These bits are always read as 0 The...

Page 463: ...or details see section 12 5 5 2 Power Down Mode when CKE Goes Low Note that the SMS bits in SCR should be set so that the CKE pin is enabled when the SDRAM is in its initial state 43 to 35 All 0 R Reserved These bits are always read as 0 The write value should always be 0 34 SELFS 0 R Self Refresh Decision Indicates whether the DDR SDRAM is or is not in the self refresh state 0 Not self refresh st...

Page 464: ... in the controller and auto refreshing is performed Note that the counter is cleared to 0 on the match after which incrementation begins again A single instance of the internally generated request for auto refresh is recorded if the DCE and DRE bits are set to 1 and the RMODE bit is cleared to 0 the auto refresh request is not cleared until auto refreshing has been performed When setting these bit...

Page 465: ...ays be cleared to 0 6 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 DLLEN 0 R W DLL Enable Sets whether the DLL for generating the read timing for the DDR SDRAM is valid or invalid When this bit is set to 1 the DLL is enabled and read access to memory is possible 2 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 D...

Page 466: ... 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SMS R W R W R W R R R R R R R R R R R R R Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W 32 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R ...

Page 467: ...ction 12 5 2 DDR SDRAM Initialization Sequence After the DDR SDRAM has been initialized normal operation 000 is specified 000 Normal operation 001 A NOP command is issued only valid if the DCE bit in MIM is set to 1 010 A PREALL command is issued only valid if the DCE bit in MIM is set to 1 011 The CKE pin is enabled At that time the DESELECT command is issued only valid if the DCE bit in MIM is s...

Page 468: ...SCL SRC SRAS SRRD SWR SRFC R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W 32 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 63 to 20 All 0 R Reserved These bits are always read as 0 The writ...

Page 469: ...r of cycles between the following access operations in a given bank the corresponding time is tRFC 1 From auto refresh to issuing the ACT command 2 From auto refresh to auto refresh 000 11 cycles 001 12 cycles 010 13 cycles 011 14 cycles 100 15 cycles Other than above Setting prohibited 12 SWR 0 R W PRE PREALL Command Issuing Cycle Within write cycles specifies the number of cycles from the last p...

Page 470: ...cles Other than above Setting prohibited 7 to 5 SRC 000 R W Auto Refresh ACT Command Issuance Cycle These bits specify the number of cycles between the following access operations in a given bank the corresponding time is tRC 1 From issuing the ACT command to auto refresh 2 From issuing one ACT command to issuing the next ACT command 000 6 cycles 001 7 cycles 010 8 cycles 011 9 cycles 100 10 cycle...

Page 471: ...d to a subsequent ACT command the corresponding time is tRP 0 3 cycles 1 4 cycles 12 4 4 SDRAM Row Attribute Register SDR 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 ...

Page 472: ...is shown in section 12 5 6 Address Multiplexing 7 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 12 4 5 SDRAM Mode Register SDMR SDMR refers to the mode register and extended mode register of the DDR SDRAM Since the SDMR is physically within the SDRAM rather than the DDRIF reading the registers is invalid Only the address bits have any meaning for the DDR ...

Page 473: ...0 14 0 13 0 12 0 11 0 10 0 9 1 8 1 7 0 6 0 5 0 4 0 3 1 2 0 1 0 0 0 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 BA0 BA1 CS RAS CAS WE H L L L L H H L L L L L L L L L L L L L MCS MARS MCAS MWE Figure 12 4 Relationship between Write Values in SDMR and Output Signals to Memory Pins For example to release the DLL from the reset state set a CAS latency of 2 5 cycles sequential burst sequ...

Page 474: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SDBUP R R R R R R R R R R R R R R R R Bit Initial value R W Note Depends on the setting of external pin BKPRST 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W 32 47 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R ...

Page 475: ...pply reference voltage and clock signals maintain the current state for at least 200 µs 3 Perform a dummy read to any DDR SDRAM address 4 Write H A500 0000 to the P4 address H FE80 0604 big endian H FE80 0600 little endian or the area 7 address H 1E80 0604 big endian H 1E80 0600 little endian with 32 bit access Note The initial value of this address field is H A500 0002 and the writing value is re...

Page 476: ...able by DDRIF Function Symbol CKEn 1 CKEn CS RAS CAS WE MA13 to MA11 AP MA10 BA1 and BA0 MA9 to MA0 Device deselect DESELECT H X H X X X X X X X No operation NOP H X L H H H X X X X Read READ H X L H L H V L V V Read with auto precharge READA H X L H L H V H V V Write WRITE H X L H L L V L V V Write with auto precharge WRITEA H X L H L L V H V V Bank activate ACT H X L L H H V V V V Precharge sele...

Page 477: ...ank is unlikely to be the target of consecutive memory accesses 12 5 5 Power Down Modes 1 Self Refresh Mode The self refresh mode is a standby state in which the SDRAM generates its own refresh timing and refresh addresses Once the self refresh mode has been set by setting the DRE and RMODE bits in MIM to 1 the self refresh state is retained even if the CPU enters the sleep mode If an interrupt th...

Page 478: ...t an appropriate interval After the recovery wait for the time required by the SDRAM before accessing the SDRAM the time depends on the DDR SDRAM for example the requirements might be for 130 ns before issuing a command other than a read command and 200 clock cycles before issuing a read command 4 When access becomes possible use the SMS bits in SCR to issue the REFA auto refresh command so that a...

Page 479: ...setting not specified in table 12 7 is used correct operation is not guaranteed Table 12 7 Relationship between SPLIT Bits and Address Multiplexing SPLIT 3 0 ROW COL BA1 BA0 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MA0 128 Mbit 2 0001 12 9 ROW 13 12 11 24 23 22 21 20 19 18 17 16 15 14 8 M 16 bit 2 COL 13 12 AP 10 9 8 7 6 5 4 3 2 256 Mbit 2 0011 13 9 ROW 13 12 11 25 24 23 22 21 20 19...

Page 480: ... in the SDRAM timing register STR must set up timing that is within the specifications of the DDR SDRAM Note that the only CAS latency supported by the DDRIF is 2 5 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 tRCD SRCD 1 CL 2 5 ACT MCLK MCS MRAS MCAS MWE MCLK CKE Command MA13 11 MA9 0 MA10 BA1 0 MDQS MDQM MDA READ PRE Row Bank Bank D0 D1 Hi Z Hi Z Row Bank Col 0 Figure 12 5 DDRIF Basic Timing 1 2 4 8 Byte S...

Page 481: ...9B0158 0100 T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 ACT MCLK MCS MRAS MCAS MWE MCLK CKE Command MA13 11 MA9 0 MA10 BA1 0 MDQS MDQM MDA Row WRITE Col 0 PRE Row Bank Bank Bank D0 D1 Hi Z Hi Z tRCD SRCD 1 Figure 12 6 DDRIF Basic Timing 1 2 4 8 Byte Single Burst Write without Auto Precharge ...

Page 482: ...T4 T5 T6 T7 T8 T9 T10 CL 2 5 ACT MCLK MCS MRAS MCAS MWE MCLK CKE Command MA13 11 MA9 0 MA10 BA1 0 MDQS MDQM MDA READA ACT Row Bank Bank Bank Row Col 0 Row Row D0 D1 Hi Z Hi Z tRC SRC 011 tRCD SRCD 1 tRP SRP 0 tRAS SRAS 000 Figure 12 7 DDRIF Basic Timing 1 2 4 8 Byte Single Burst Read with Auto Precharge ...

Page 483: ... T5 T6 T7 T8 T9 T10 ACT MCLK MCS MRAS MCAS MWE MCLK CKE Command MA13 11 MA9 0 MA10 BA1 0 MDQS MDQM MDA Row WRITEA Col 0 ACT Row Bank Row Row Bank Bank D0 D1 Hi Z Hi Z tRC SRC 101 tRCD SRCD 1 tWR SWR 0 tRP SRP 0 tRAS SRAS 010 Figure 12 8 DDRIF Basic Timing 1 2 4 8 Byte Single Burst Write with Auto Precharge ...

Page 484: ...6 T7 T8 T9 T10 tRCD SRCD 1 CL 2 5 ACT MCLK MCS MRAS MCAS MWE MCLK CKE Command MA13 11 MA9 0 MA10 BA1 0 MDQS MDQM MDA Row READ READ READ READ PRE Col 2 Col 0 Col 4 Col 6 Row Bank Bank Bank Bank Bank Bank D0 D1 D2 D3 D4 D5 D6 D7 Hi Z Hi Z Figure 12 9 DDRIF Basic Timing 4 Burst Read 32 byte without Auto Precharge ...

Page 485: ...5 T6 T7 T8 T9 tRCD SRCD 1 ACT MCLK MCS MRAS MCAS MWE MCLK CKE Command MA13 11 MA9 0 MA10 BA1 0 MDQS MDQM MDA Row WRITE WRITE WRITE WRITE PRE Col 2 Col 0 Col 4 Col 6 Row Bank Bank Bank Bank Bank Bank Hi Z Hi Z D1 D2 D3 D4 D5 D6 D7 D0 Figure 12 10 DDRIF Basic Timing 4 Burst Write 32 byte without Auto Precharge ...

Page 486: ... 2005 Page 436 of 1286 REJ09B0158 0100 T0 T1 T2 T3 T4 tRP SRP 1 PREALL MCLK MCS MRAS MCAS MWE MCLK CKE Command MA13 11 MA9 0 MA10 BA1 0 MDQS MDQM MDA ACT Row Bank Hi Z Hi Z Row Figure 12 11 DDRIF Basic Timing from Precharging All Banks to Bank Activation ...

Page 487: ...T0 T1 T2 T3 MRS Notes 1 Operating mode or other setting 2 Mode register setting BA1 Low BA0 Low Extended mode register setting BA1 Low BA0 High MCLK MCS MRAS MCAS MWE MCLK CKE Command MA13 11 MA9 0 MA10 BA1 0 MDQS MDQM MDA 1 Hi Z Hi Z 1 2 Figure 12 12 DDRIF Basic Timing Mode Register Setting ...

Page 488: ...e 438 of 1286 REJ09B0158 0100 REFA T0 T1 T0 T1 REFA MCLK MCS MRAS MCAS MWE MCLK CKE Command MA13 11 MA9 0 BA1 0 Row ACT Bank Row MA10 tRFC 11 to 15 cycles Auto refresh tRFC 11 to 15 cycles Figure 12 13 DDRIF Basic Timing Enter Auto Refresh Exit to Bank Activation ...

Page 489: ... refresh interval conditions of the SDRAM in use 2 These parameters must satisfy the refresh interval specification of the SDRAM tXSNR is for all commands other than read commands tXSRD is for read commands and is usually at least 200 clock cycles MCLK CKE T0 T1 T0 T1 Command MA9 0 MA13 11 MA10 BA1 0 Any Command 1 Self refresh Figure 12 14 DDRIF Basic Timing Enter Self Refresh Exit to Command Issu...

Page 490: ...the SDRAM will be lost To prevent this software should place the SDRAM in the self refresh state before supply of the clock signal is stopped For details on making the SDRAM enter and leave the self refresh mode see section 12 5 5 1 Self Refresh Mode 12 7 3 Using SCR to Issue REFA Command Outside the Initialization Sequence The DDR SDRAM bank is automatically opened by the DDRIF access read from o...

Page 491: ...cted by the value of the DRI bits before the new setting was made However the second and subsequent auto refresh intervals take on the value corresponding to the new setting for the DRI bits To avoid this situation clear the DRE bit to 0 whenever you change the settings of the DRI bits When the DRE bit is subsequently set to 1 and the same DRI setting is repeated auto refreshing proceeds with the ...

Page 492: ...Section 12 DDR SDRAM Interface DDRIF Rev 1 00 Dec 13 2005 Page 442 of 1286 REJ09B0158 0100 ...

Page 493: ...erHyway bus The PCIC supports both the host bus bridge mode and normal mode non host mode In host busbridge mode PCI bus arbitration control is available and in normal mode arbitration is executed by the external PCI bus arbiter 13 1 Features The PCIC has the following features Supports subset of PCI Local Bus Specification Revision 2 2 PCI bus operating speeds of 33 MHz 66 MHz 32 bit data bus PCI...

Page 494: ...xternal interrupt inputs INTD to INTA in host bus bridge mode Supports one external interrupt output INTA in normal mode Supports both big endian and little endian formats for the SuperHyway bus the PCI bus operates in the little endian format The PCIC does not support the following PCI functions Cache support no SBO or SDONE pin Address wrap around mechanism PCI JTAG other modules in this LSI can...

Page 495: ...ntrol PCI local bus PCIRESET PCI standard signal Figure 13 1 PCIC Block Diagram The PCIC comprises two blocks the PCI bus interface and SuperHyway bus interface block The PCI bus interface block comprises the PCI configuration register local register PCI master and PCI target controller The functions of the PCI bus interface are transaction control on the PCI local bus The SuperHyway bus interface...

Page 496: ...s AD 31 0 and CBE 3 0 PCICLK CLK Input PCI Clock Provides timing for all transactions on the PCI bus PCIFRAME FRAME I O STRI PCI Frame Current initiator drives this signal which indicates the start and duration or end of a transaction TRDY TRDY I O STRI PCI Target Ready Selected target drives this signal which indicates the target is ready to execute a transaction During a write this signal indica...

Page 497: ... is requesting an interrupt input in host bus bridge mode This signal is used to request an interrupt output O D in normal mode REQ3 to REQ1 4 REQ 3 1 Input PCI Bus Request Available only in host bus bridge mode GNT3 to GNT1 4 GNT 3 1 Output TRI PCI Bus Grant Available only in host bus bridge mode REQ0 REQOUT REQ0 I O TRI PCI Bus Request Functions as an input or an output in host bus bridge mode a...

Page 498: ... tri state O D Open Drain Notes 1 These pins are multiplexed with the GPIO pins port A to D 2 This pin is multiplexed with the SCIF channel 0 and GPIO pins 3 These pins are multiplexed with the DMAC H UDI and GPIO pins 4 These pins are multiplexed with the GPIO pins 5 This pin is multiplexed with the INTC and FLCTL pins ...

Page 499: ...1E04 0008 8 PCI program interface register PCIPIF R W R H FE04 0009 H 1E04 0009 8 PCI sub class code register PCISUB R W R H FE04 000A H 1E04 000A 8 PCI base class code register PCIBCC R W R H FE04 000B H 1E04 000B 8 PCI cacheline size register PCICLS R R H FE04 000C H 1E04 000C 8 PCI latency timer register PCILTM R W R W H FE04 000D H 1E04 000D 8 PCI header type register PCIHDR R R H FE04 000E H ...

Page 500: ... H 1E04 0100 32 PCI local space register 0 PCILSR0 R W R H FE04 0104 H 1E04 0104 32 PCI local space register 1 PCILSR1 R W R H FE04 0108 H 1E04 0108 32 PCI local address register 0 PCILAR0 R W R H FE04 010C H 1E04 010C 32 PCI local address register 1 PCILAR1 R W R H FE04 0110 H 1E04 0110 32 PCI interrupt register PCIIR R WC R H FE04 0114 H 1E04 0114 32 PCI interrupt mask register PCIIMR R W R H FE...

Page 501: ...E04 01F4 H 1E04 01F4 32 PCI I O bank register PCIIOBR R W H FE04 01F8 H 1E04 01F8 32 PCI I O bank master register PCIIOBMR R W H FE04 01FC H 1E04 01FC 32 PCI cache snoop control register 0 PCICSCR0 R W H FE04 0210 H 1E04 0210 32 PCI cache snoop control register 1 PCICSCR1 R W H FE04 0214 H 1E04 0214 32 PCI cache snoop address register 0 PCICSAR0 R W H FE04 0218 H 1E04 0218 32 PCI cache snoop addre...

Page 502: ... line size register PCICLS H 20 Retained Retained PCI latency timer register PCILTM H 00 Retained Retained PCI header type register PCIHDR H 00 Retained Retained PCI BIST register PCIBIST H 00 Retained Retained PCI I O base address register PCIIBAR H 0000 0001 Retained Retained PCI Memory base address register 0 PCIMBAR0 H 0000 0000 Retained Retained PCI Memory base address register 1 PCIMBAR1 H 0...

Page 503: ...CI interrupt register PCIIR H 0000 0000 Retained Retained PCI interrupt mask register PCIIMR H 0000 0000 Retained Retained PCI error address information register PCIAIR H xxxx xxxx Retained Retained PCI error command information register PCICIR H xx00 000x Retained Retained PCI arbiter interrupt register PCIAINT H 0000 0000 Retained Retained PCI arbiter interrupt mask register PCIAINTM H 0000 0000...

Page 504: ...k register PCIIOBR H 0000 0000 Retained Retained PCI I O bank master register PCIIOBMR H 0000 0000 Retained Retained PCI cache snoop control register 0 PCICSCR0 H 0000 0000 Retained Retained PCI cache snoop control register 1 PCICSCR1 H 0000 0000 Retained Retained PCI cache snoop address register 0 PCICSAR0 H 0000 0000 Retained Retained PCI cache snoop address register 1 PCICSAR1 H 0000 0000 Retai...

Page 505: ...3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ENBL R W R R R R R R R R R R R R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 ENBL 0 R W PCI Enable Bit Enable the PCIC 0 PCIC disable The access from both the CPU and external PCI devices to the PCIC is invalid incl...

Page 506: ... R R R R R R R R PCI R W Bit Bit Name Initial Value R W Description 15 to 0 VID H 1912 SH R PCI R PCI Vender ID Indicates the PCI device manufacture identifier vender ID that is allocated by PCI SIG Renesas Technology s vendor ID is H 1912 2 PCI Device ID Register PCIDID This register uniquely identifies this LSI amongst PCI devices manufactured by the vendor 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 ...

Page 507: ...to 10 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 9 FBBE 0 SH R PCI R PCI Fast Back to Back Enable Controls whether or not a master can do fast back to back transactions to different device 0 Fast back to back transactions are only allowed to the same target 1 Master is allowed to generate fast back to back transactions to different targets not supp...

Page 508: ... invalidate command is executable not supported 3 SC 0 SH R PCI R PCI Special Cycles Indicates whether or not to support the special cycle operations in a target access 0 Special cycles ignored 1 Special cycles monitored not supported 2 BM 0 SH R W PCI R W PCI Bus Master Control Controls a bus master 0 Bus master function disabled 1 Bus master function enabled 1 MS 0 SH R W PCI R W PCI Memory Spac...

Page 509: ...For instance to clear bit 14 and not affect any other bits write the value of B 0100 0000 0000 0000 to the register 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 CL 66C FBBC MDPE DEVSEL STA RTA RMA DPE SSE 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 R R R R R R W R W R R WC R R R WC R WC R WC R WC R WC Bit Initial value SH R W R R R R R R R R R WC R R R WC R WC R WC R WC R WC PCI R W Bit Bit Name Initial Value R W De...

Page 510: ...been terminated with a target abort 11 STA 0 SH R WC PCI R WC Target Abort Execution Status Indicates that the PCIC has terminated a transaction with a target abort when the PCIC functions as a target 0 PCIC has not terminated a transaction with a target abort 1 PCIC has terminated a transaction with target abort 10 9 DEVSEL 01 SH R PCI R DEVSEL Timing Status Indicate the response timing status of...

Page 511: ...ed 1 Fast back to back transactions to different agents supported 6 0 SH R W PCI R Reserved These bits are always read as 0 The write value should always be 0 5 66C 0 SH R W PCI R 66MHz Operation Capable Status Indicates whether or not the PCIC is capable of running at 66MHz 0 PCIC runs at 33 MHz 1 PCIC runs at 66 MHz 4 CL 1 SH R PCI R PCI Power Management Optional Function Indicates whether or no...

Page 512: ...CIC and it may be changed in the future 6 PCI Program Interface Register PCIPIF This register is the programming interface for the IDE controller class code For details of the class code refer to PCI Local Bus Specification Revision 2 2 Appendix D R R R R R R R R PCI R W 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 OMP PIP OMS PIS MIDED R W R W R W R W R R R R W Bit Initial value SH R W Bit Bit Name Initial Va...

Page 513: ...writing is ignored This bit is readable 2 OMS 0 SH R W PCI R PCI Operating Mode Secondary When the CFINIT bit in PCICR is 0 this bit is writable When the CFINIT bit in PCICR is 1 writing is ignored This bit is readable 1 PIP 0 SH R W PCI R PCI Programmable Indicator Primary When the CFINIT bit in CR is 0 this bit is writable When the CFINIT bit in PCICR is 1 writing is ignored This bit is readable...

Page 514: ...Bit Bit Name Initial Value R W Description 7 to 0 SUB H 00 SH R W PCI R Sub Class Code Indicate the sub class code The initial value is H 00 8 PCI Base Class Code Register PCIBCC This register identifies the base class code For details of the class code refer to PCI Local Bus Specification Revision 2 2 Appendix D 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 BCC R W R W R W R W R W R W R W R W Bit Initial value...

Page 515: ...mory target does not support a cache SDON and SBO are ignored 10 PCI Latency Timer Register PCILTM This register specifies in units of PCI bus clocks the value of latency timer for this PCI bus master 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 LTM R W R W R W R W R W R W R W R W Bit Initial value SH R W R W R W R W R W R W R W R W R W PCI R W Bit Bit Name Initial Value R W Description 7 to 0 LTM H 00 SH R W ...

Page 516: ...to 0 HDR H 00 SH R PCI R Configuration Layout Indicates the layout type of configuration registers H 00 Type 00h layout supported H 01 Type 01h layout supported not supported 12 PCI BIST Register PCIBIST R R R R R R R R PCI R W 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 BISTC R R R R R R R R Bit Initial value SH R W Bit Bit Name Initial Value R W Description 7 BISTC 0 SH R PCI R This bit is used to control t...

Page 517: ...OB upper 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value SH R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W PCI R W Bit Bit Name Initial Value R W Description 31 to 8 IOB upper H 000000 SH R W PCI R W I O Space Base Address upper 24 bits Specifies the upper 24 bits of I O base address that corresponds the PCIC lo...

Page 518: ...W R W R W R W R W R W R W R W R W Bit Initial value SH R W R R R R R W R W R W R W R W R W R W R W R W R W R W R W PCI R W Bit Bit Name Initial Value R W Description 31 to 20 MBA upper H 000 SH R W PCI R W Memory Space 0 Base Address upper 12 bits Specifies the upper 12 bits of memory base address that corresponds the local address space 0 SuperHyway bus address space of this LSI Update value PCIL...

Page 519: ...e 1 I O space 15 PCI Memory Base Address Register 1 PCIMBAR1 This register packages the memory space base address register of the PCI configuration register that is prescribed with PCI local bus specification Refer to Section 13 4 4 1 Accessing This LSI Address Space 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 ASI LAT LAP MBA lower 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Init...

Page 520: ... 1111 1111 256 Mbytes 31 28 1 1111 1111 512 Mbytes 31 29 19 to 4 MBA lower H 0000 SH R PCI R Memory Space 1 Base Address lower 16 bits These bits are fixed H 0000 by hardware 3 LAP 0 SH R PCI R Prefetch Control Indicates whether or not local address space 1 is prefetchable 0 Not prefetchable 1 Prefetchable Not supported 2 1 LAT 00 SH R PCI R Memory Type Indicates the memory type of local address s...

Page 521: ...fied during initializing PCIC registers PCICR CFINIT 0 but cannot be modified after initialized PCIC register PCICR CFINIT 1 even if writing this field 17 PCI Subsystem ID Register PCISID Refer to section about miscellaneous registers of PCI local bus specification Revision 2 2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 SSID 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R ...

Page 522: ...Description 7 to 0 CP H 40 SH R PCI R Capabilities pointer The offset address of the expansion function register 19 PCI Interrupt Line Register PCIINTLINE 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 INTLINE R W R W R W R W R W R W R W R W Bit Initial value SH R W R W R W R W R W R W R W R W R W PCI R W Bit Bit Name Initial Value R W Description 7 to 0 INTLINE H 00 SH R W PCI R W PCI Interrupt Line PCI interru...

Page 523: ...n the PCIC outputs interrupt request H 00 Does not connect INTD to INTA H 01 INTA is used to request an interrupt H 02 INTB is used to request an interrupt H 03 INTC is used to request an interrupt H 04 INTD is used to request an interrupt H 05 to H FF Reserved 21 PCI Minimum Grant Register PCIMINGNT This register is not programmable 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 MINGNT R R R R R R R R Bit Initi...

Page 524: ...ter device to the bus acquisition not supported 23 PCI Capability Identifier Register PCICID When H 01 is read by system software it indicates that the data structure currently being pointed to is the PCI power management data structure Each function of a PCI device may have only one item in its capability list with PCICID set to H 01 0 1 2 3 4 5 6 7 1 0 0 0 0 0 0 0 CID R R R R R R R R Bit Initial...

Page 525: ...n of the next item in the function s capability list 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 NIP R R R R R R R R Bit Initial value SH R W R R R R R R R R PCI R W Bit Bit Name Initial Value R W Description 7 to 0 NIP H 00 SH R PCI R Next Item Pointer Specifies the offset to the next expansion function H 00 Power management function is listed as the last item ...

Page 526: ...it Name Initial Value R W Description 15 to 11 PMCS 00000 SH R PCI R PME_SUPPORT This 5 bit field indicates the power states in which the function may assert PME A value of 0b for any bit indicates that the function is not capable of asserting the PME signal while in that power state Bit11 xxxx1 PME can be asserted from D0 Bit12 xxx1x PME can be asserted from D1 Bit13 xx1xx PME can be asserted fro...

Page 527: ...ation 0 Does not require the specific initialization 4 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 3 PMEC 1 SH R W PCI R PCI PME clock Specifies whether or not the device requires the clock to support PME generation 1 Requires the clock to support PME generation Note This LSI dose not have the PME pin 2 to 0 PMV 010 SH R W PCI R Version Specifies the ve...

Page 528: ...on 15 PMES 0 SH R PCI R PME Status Indicates the state of the PME signal Not supported Note This LSI dose not have the PME pin 14 13 DSC 00 SH R PCI R Data Scale Specify the scaling of data field Not supported 12 to 9 DSL 0000 SH R PCI R Data Select Specify the data output in the data filed 8 PMEEN 0 SH R PCI R PME Enable Controls the PME output Not supported Note This LSI dose not have the PME pi...

Page 529: ...the power state bits in bridge s PCIPMCSR cannot be used by the system software to control the power or clock of the bridge s secondary bus 6 B2B3N 0 SH R PCI R The state of this bit determines the action that is to occur as a direct result of programming the function to the D3 hot state 0 Indicates that when the bridge function is set to the D3 hot state its secondary bus will have its power remo...

Page 530: ...pation For details refer to PCI Bus Power Management Interface Specification Revision 1 1 Chapter 3 PCI Power Management Interface 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 PCDD R W R W R W R W R W R W R W R W Bit Initial value SH R W R R R R R R R R PCI R W Bit Bit Name Initial Value R W Description 7 to 0 PCDD H 00 SH R W PCI R This register is used to report the state dependent data requested by the PCIP...

Page 531: ... 0 0 0 0 0 Bit Initial value 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 RST CTL CFI NIT IOCS R W 0 SERR BMAM TBS PFE FTO PFCS Bit Initial value Bit Bit Name Initial Value R W Description 31 to 24 H 00 SH R W PCI R Reserved Set these bits to H A5 only when writing to bits 11 to 8 6 and 3 to 0 These bits are always read as 0 23 to 12 All 0 SH R PCI R Reserved These bits are alwa...

Page 532: ...e 0 Fixed mode PCIC device0 device1 device2 device3 1 Pseudo round robin the most recently granted device is assigned the lowest priority 5 4 Undefined SH R PCI R Reserved These bits are always read as an undefined value The write value should always be 0 3 SERR 0 SH R W PCI R SERR Output Controls the SERR output by software This bit is valid only in normal mode do not use in host bus bridge mode ...

Page 533: ... are completed Setting this bit enables accesses from the PCI bus During initialization in host bus bridge mode the bus is not given to the device on the PCI bus In normal mode the PCIC returns RETRY when it is accessed from the PCI bus 0 During initialization 1 Initialization completed 2 PCI Local Space Register 0 PCILSR0 Refer to Section 13 4 4 1 Accessing This LSI Address Space SH R W PCI R W R...

Page 534: ... in these bits must be the size minus 1 Mbytes Setting all the bits to 0 ensures 1 Mbyte space 0 0000 0000 1 Mbyte 0 0000 0001 2 Mbytes 0 0000 0011 4 Mbytes 0 0000 0111 8 Mbytes 0 0000 1111 16 Mbytes 0 0001 1111 32 Mbytes 0 0011 1111 64 Mbytes 0 0111 1111 128 Mbytes 0 1111 1111 256 Mbytes 1 1111 1111 512 Mbytes Other than above Setting prohibited 19 to 1 All 0 SH R PCI R Reserved These bits are al...

Page 535: ...Initial Value R W Description 31 to 29 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 28 to 20 LSR 0 0000 0000 SH R W PCI R Size of Local Address Space 1 9 bits Specify the size of local address space 1 SuperHyway bus address space of this LSI in units of Mbyte The value set in these bits must be the size minus 1 Mbytes Setting all the bits to 0 ensure...

Page 536: ... R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 20 LAR H 000 SH R W PCI R Local Address 12 bits Specify bits 31 to 20 of the start address in local address space 0 The effective bits of LAR depend on the capacity of local address space 0 as specified...

Page 537: ...7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 20 LAR H 000 SH R W PCI R Local Address 12 bits Specify bits 31 to 20 of the start address in local address space 1 The effective bits of LAR depend on the capacity of local address space 1 as specified in PCILSR1 The effective bits are as follows PCILSR1 LS1 28 20 0 0000 0000 Effective bits are 31 20 PCILSR...

Page 538: ...DI APE DI MDEI TMT OI TTA DI R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 15 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 14 TTADI 0 SH R WC PCI R Target Target Abort Interrupt Indicates that the ...

Page 539: ...of memory read operations 0 Target memory read retry timeout interrupt does not occur Clear condition Write 1 to this bit write clear 1 Target memory read retry timeout interrupt occurs Set condition When a target memory read retry timeout interrupt occurs 8 MDEI 0 SH R WC PCI R Master Function Disable Error Interrupt The PCIC attempted a master access when such accesses are disabled that is when ...

Page 540: ...6 SEDI 0 SH R WC PCI R SERR Detection Interrupt Indicates that the assertion of the SERR signal has been detected when the PCIC operates in host bus bridge mode 0 SERR detection interrupt does not occur Clear condition Write 1 to this bit write clear 1 SERR detection interrupt occurs Set condition When a SERR detection interrupt occurs 5 DPEITW 0 SH R WC PCI R Data Parity Error Interrupt for Targe...

Page 541: ...tection interrupt occurs 3 TADIM 0 SH R WC PCI R Target Abort Detection Interrupt for Master When the PCIC functions as a master it has detected a target abort that is the transaction is terminated 0 Target abort interrupt does not occur Clear condition Write 1 to this bit write clear 1 Target abort interrupt occurs Set condition When a target abort interrupt occurs 2 MADIM 0 SH R WC PCI R Master ...

Page 542: ...ur Clear condition Write 1 to this bit write clear 1 Master write PERR interrupt occurs Set condition When a master write PERR interrupt occurs 0 MRDPEI 0 SH R WC PCI R Master Read Data Parity Error Interrupt Indicates that a data parity error has been detected during a master read access only detected when PCICMD PER is set to 1 when the PCIC functions as a master 0 Master read data perity error ...

Page 543: ... 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 15 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 14 TTADIM 0 SH R W PCI R Target Target Abort Interrupt Mask 0 PCIIR TTADI disabled masked 1 PCIIR TTADI enabled not masked 13 to 10 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always b...

Page 544: ...ion Interrupt Mask for Target Read 0 PCIIR PEDITR disabled masked 1 PCIIR PEDITR enabled not masked 3 TADIMM 0 SH R W PCI R Target Abort Interrupt Mask for Master 0 PCIIR TADIM disabled masked 1 PCIIR TADIM enabled not masked 2 MADIMM 0 SH R W PCI R Master Abort Interrupt Mask for Master 0 PCIIR MADIM disabled masked 1 PCIIR MADIM enabled not masked 1 MWPDIM 0 SH R W PCI R Master Write Data Parity...

Page 545: ... 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R AIL R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R AIL 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 0 AIL Undefined SH R PCI R Address Information Log This register holds address information the sta...

Page 546: ... 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 MTEM Undefined SH R PCI R Master Error Indicates that an error has occurred during a master access 0 Master error does not occur 1 Master error occurs 30 to 27 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 26 RWTET Undefined SH R PCI R Target Error Indicates that an error has oc...

Page 547: ...R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R WC R WC R WC R WC R R R R R R R R WC R WC R WC R R R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WD PEI RD PEI MAI TAI MB TOI TB TOI MBI 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 14 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 13 M...

Page 548: ... to the 2nd 0 Target bus time out interrupt does not occur Clear condition Write 1 to this bit write clear 1 Target bus time out interrupt occurs Set condition When a target bus time out interrupt occurs 11 MBTOI 0 SH R WC PCI R Master Bus Time Out Interrupt An interrupt is detected when the IRDY signal is not asserted within 8 clock cycles 0 Master bus time out interrupt does not occur Clear cond...

Page 549: ...Master Abort Interrupt Indicates that a transaction is terminated with a master abort when a device other than the PCIC functions as a bus master 0 Master abort interrupt does not occur Clear condition Write 1 to this bit write clear 1 Master abort interrupt occurs Set condition When a master abort interrupt occurs 1 RDPEI 0 SH R WC PCI R Read Parity Error Interrupt The PERR assertion is detected ...

Page 550: ...s detected by the PERR assertion 11 PCI Arbiter Interrupt Mask Register PCIAINTM This register is the mask register for PCIAINT SH R W PCI R W SH R W PCI R W 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R R R R R R R R W R W R W R R R R R R R R R R R R R R R R R R 0 ...

Page 551: ...BTOI disabled masked 1 PCIAINT MBTOI enabled not masked 10 to 4 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 3 TAIM 0 SH R WC PCI R Target Abort Interrupt Mask 0 PCIAINT TAI disabled masked 1 PCIAINT TAI enabled not masked 2 MAIM 0 SH R WC PCI R Master Abort Interrupt Mask 0 PCIAINT MAI disabled masked 1 PCIAINT MAI enabled not masked 1 RDPEIM 0 SH R...

Page 552: ... R R R R R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 REQ0 BME REQ1 BME REQ2 BME REQ3 BME REQ4 BME 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 5 All 0 SH R PCI R Reserved These bits are always read as 0 The write value should always be 0 4 REQ4BME Undefined SH R PCI R REQ4 Error An error occurs when the PCIC functions as a bus m...

Page 553: ... R W R W R W R W R W R W R W R W R W R W R W 0 0 CRA FN DN 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 CCIE 1 SH R PCI Configuration Cycle Issue Enable Enables a configuration cycle to be issued 1 Indicates the configuration cycle generation enable 30 to 24 All 0 SH R PCI Reserved These bits are always read as 0 The write value should alway...

Page 554: ...iven to low level Device No IDSEL Device No IDSEL H 0 AD 16 high level H 8 AD 24 high level H 1 AD 17 high level H 9 AD 25 high level H 2 AD 18 high level H A AD 26 high level H 3 AD 19 high level H B AD 27 high level H 4 AD 20 high level H C AD 28 high level H 5 AD 21 high level H D AD 29 high level H 6 AD 22 high level H E AD 30 high level H 7 AD 23 high level H F AD 31 high level Other than abo...

Page 555: ...ays read as 0 The write value should always be 0 3 PMD3H 0 SH R WC PCI PCI Power Management D3 Hot Status Transition Interrupt 0 Interrupt request for a transition to D3 is not detected 1 Interrupt request for a transition to D3 is detected 2 PMD2 0 SH R WC PCI PCI Power Management D2 Status Transition Interrupt 0 Interrupt request for a transition to D2 is not detected 1 Interrupt request for a t...

Page 556: ... Initial Value R W Description 31 to 4 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 3 PMD3HM 0 SH R W PCI PCI Power Management D3 Hot Status Transition Interrupt Mask 0 PCIPINT PM D3H disabled masked 1 PCIPINT PM D3H enabled not masked 2 PMD2M 0 SH R W PCI PCI Power Management D2 Status Transition Interrupt Mask 0 PCIPINT PMD2 disabled masked 1 PCIPINT...

Page 557: ...25 26 27 28 29 31 30 Bit Initial value R R R W R W R R R R R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMSBA0 R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 18 PMSBA0 H 0000 SH R W PCI PCI Memory Space 0 Bank Address Specify the bank address in PCI m...

Page 558: ...R R R R R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSBAM0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 24 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 23 to 18 MSBAM0 000000 SH R W PCI PCI Memory Space 0 Bank Address Mask 0000 00 256 Kbytes 0000 01 512 Kbytes 0000 11 1 Mby...

Page 559: ...25 26 27 28 29 31 30 Bit Initial value R R R W R W R R R R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMSBA1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 18 PMSBA1 All 0 SH R W PCI PCI Memory Space 1 Bank Address Specify the bank address in PCI me...

Page 560: ...R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MSBAM1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 26 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 25 to 18 MSBAM1 All 0 SH R W PCI PCI Memory Space 1 Bank Address Mask 8 bits 00 0000 00 256 Kbytes 00 0000 01 512 Kbytes 00 0000 11 1 Mbyte 00 0001 11 2 M...

Page 561: ...25 26 27 28 29 31 30 Bit Initial value R R R W R W R R R R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PMSBA2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 18 PMSBA2 All 0 SH R W PCI PCI Memory Space 2 Bank Address Specify the bank address in PCI me...

Page 562: ...2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 29 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 28 to 18 MSBAM2 All 0 SH R W PCI PCI Memory Space 2 Bank Address Mask 0 0000 0000 00 256 Kbytes 0 0000 0000 01 512 Kbytes 0 0000 0000 11 1 Mbyte 0 0000 0001 11 2 Mbytes 0 0000 0011 11 4 Mbytes 0 0000 0111 ...

Page 563: ... 27 28 29 31 30 Bit Initial value R R R W R W R R R R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PIOSBA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 18 PIOSBA All 0 SH R W PCI PCI I O Space Bank Address 14 bits Specify the bank address in PCI I O ...

Page 564: ...0 0 R R R R R R R R R R R R R R R W R W R W R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOBAMR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 21 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 20 to 18 IOBAMR All 0 SH R W PCI PCI I O Space Bank Address Mask 3 bits 000 256 Kbytes 001 512 K...

Page 565: ...MD RANGE R W R R R R R R R R R R R R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 5 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 4 to 2 RANGE All 0 SH R W PCI Address Range to be Compared Specify the address range of PCICSAR0 to be ...

Page 566: ...r PCICSAR0 Specify if PCICSAR0 is compared with address requested by an external device Also specify how snoop function is executed when PCICSAR0 is compared 00 PCICSAR0 not compared 01 Reserved setting prohibited 10 PCICSAR0 compared If hit snoop function is not executed otherwise executed 11 PCICSAR0 compared If hit snoop function is executed otherwise not executed ...

Page 567: ...MD RANGE R W R R R R R R R R R R R R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 5 All 0 SH R PCI Reserved These bits are always read as 0 The write value should always be 0 4 to 2 RANGE All 0 SH R W PCI Address Range to be Compared Specify the address range of PCICSAR1 to be ...

Page 568: ...r PCICSAR1 Specify if PCICSAR1 is compared with address requested by an external device Also specify how snoop function is executed when PCICSAR1 is compared 00 PCICSAR1 not compared 01 Reserved setting prohibited 10 PCICSAR1 compared If hit snoop function is not executed otherwise executed 11 PCICSAR1 compared If hit snoop function is executed otherwise not executed ...

Page 569: ...16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W CADR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W CADR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 0 CADR All 0 SH R W PCI Add...

Page 570: ...16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W CADR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W CADR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value Bit Bit Name Initial Value R W Description 31 to 0 CADR All 0 SH R W PCI Add...

Page 571: ...Configuration Space Access SH R W PCI R W SH R W PCI R W 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 Bit Initial value PDR PDR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R W Description 31 to 0 PDR Undefined SH R W PCI PCI PIO Data Register A read from or write to this register will cause a ...

Page 572: ...emory read Yes Yes 0111 Memory write Yes Yes 1000 Reserved 1001 Reserved 1010 Configuration read Yes 1 Yes 2 1011 Configuration write Yes 1 Yes 2 1100 Memory read multiple No Partially yes 3 1101 Dual address cycle No No 1110 Memory read line No Partially yes 3 1111 Memory write and invalidate No Partially yes 4 Legend 0 Low level 1 High level Notes 1 Only the host bus bridge mode is supported 2 S...

Page 573: ... will read 0 none of the registers can be modified and any access to the PCI bus will not be executed To initialize the PCIC first setting the enable bit in the PCIECR to 1 The PCIC s internal configuration registers and local registers must be initialized before setting the CFINIT bit in the PCICR to 1 while the CFINIT bit is cleared to 0 On completion of initialization set the CFINIT bit to 1 Wh...

Page 574: ...ss extended mode H C000 0000 to H DFFF FFFF 512 Mbytes PCI memory space 0 H FD00 0000 to H FDFF FFFF H FD00 0000 to H FDFF FFFF 16 Mbytes Control register H FE00 0000 to H FE03 FFFF H FE00 0000 to H FE03 FFFF 256 Kbytes PCIC internal register configuration and local registers H FE04 0000 to H FE07 FFFF H FE04 0000 to H FE07 FFFF 256 Kbytes Reserved H FE08 0000 to H FE1F FFFF H FE08 0000 to H FE1F ...

Page 575: ...PCIMBR and PCI memory bank mask register PCIMBMR These registers should have an address space ranging from 16 Mbytes to 512 Mbytes PCI addresses can be allocated to by software The PCIC supports burst transfers to memory transfer Consecutive accesses with the SuperHyway load 32 byte or SuperHyway store 32 byte command result in a burst transfer of 32 byte or more 64 byte 96 byte etc The PCI memory...

Page 576: ...uperHyway bus address are replaced with bits 31 to 24 in PCI memory bank register 0 PCIMBR0 31 31 24 23 18 17 0 0 24 23 18 17 PCIMBMR0 mask SH address MSBAM0 31 24 23 18 17 0 31 24 23 18 17 0 PCIMBR0 PCI address PMSBA0 Figure 13 3 SuperHyway Bus to PCI Local Bus Address Translation PCI Memory Space 0 For PCI memory space 1 accesses bits 25 to 18 of a SuperHyway address are controlled by PCI memory...

Page 577: ...MR2 PCIMBMR2 28 18 B 1 1111 1111 11 PCI address 28 18 SH address 28 18 PCIMBMR2 28 18 B 0 1111 1111 11 PCI address 28 18 PCIMBR2 28 SH address 27 18 PCIMBMR2 28 18 B 0 0000 0000 01 PCI address 28 18 PCIMBR2 28 19 SH address 18 PCIMBMR2 28 18 B 0 0000 0000 00 PCI address 28 18 PCIMBR2 28 18 The upper three bits 31 29 of a SuperHyway bus address are replaced with bits 31 to 29 in PCI memory bank reg...

Page 578: ... PCIIOBMR Note In the following item and figure SH means the SuperHyway bus of this LSI and PCI means the PCI local bus PCIIOMR0 20 18 B 111 PCI address 20 18 SH address 20 18 PCIIOMR0 20 18 B 011 PCI address 20 18 PCIIOBR 20 SH address 19 18 PCIIOMR0 20 18 B 001 PCI address 20 18 PCIIOBR 20 19 SH address 18 PCIIOMR0 20 18 B 000 PCI address 20 18 PCIIOBR 20 18 The upper 11 bits 31 21 of a SuperHyw...

Page 579: ...pported 5 Endian The PCIC of this LSI supports both the big endian and little endian formats Since PCI local bus is inherently little endian the PCIC supports both byte swapping and non byte swapping The endian format is specified by the setting of the TBS bit in the PCI control register PCICR at a reset Note In the following figures SH means the SuperHyway bus of this LSI and PCI means the PCI lo...

Page 580: ...D Buffer data A B C D A B C D A B C D PCI Address 2 1 PCI Address 2 0 MSByte 31 0 LSByte MSByte LSByte SH data PCI data Note PCI Address 2 AD 2 address 2 Big Endian A B C D A B C D Buffer data A B C D A B C D A B C D PCI Address 2 0 PCI Address 2 1 Figure 13 7 Endian Conversion from SuperHyway Bus to PCI Local bus Non Byte Swapping TBS 0 ...

Page 581: ...ddress 2 1 PCI Address 2 0 MSByte 31 0 LSByte MSByte LSByte D C B A D C B A A B C D A B C D A B C D PCI Address 2 1 PCI Address 2 0 SH data PCI data 1 Little Endian Buffer data SH data PCI data 2 Big Endian Buffer data Note PCI Address 2 AD 2 address Figure 13 8 Endian Conversion from SuperHyway Bus to PCI Local bus Byte Swapping TBS 1 ...

Page 582: ... modes 1 Accessing This LSI Address Space Accesses to the address space of this LSI by an external PCI bus master are described here H 0000 0000 Memory base 0 Local address space 0 base 0 Local address space 1 base 1 I O space 4 Mbytes Memory base 1 I O base 1 PCI I O space PCI local bus address space 4 Gbytes SuperHyway bus address space 4 Gbytes H FFFF FFFF H 0000 0000 H FFFF FFFF H FE00 0000 H ...

Page 583: ...pace used by the PCI device The PCILAR0 1 specifies the starting address of the local address space 0 1 The PCILSR0 1 expresses the size of the memory used by the PCI device Address translation from PCI local bus to SuperHyway bus For the PCIMBAR0 1 and PCILAR0 1 the more significant address bits that are higher than the memory size set in the PCILSR0 1 becomes valid The more significant address b...

Page 584: ... to the SuperHyway bus without translation Data prefetching for memory read commands is supported When a PCI burst read is performed 8 bytes or 32 bytes of data block is prefetched this depends on the settings of the PFE and PFCS bits in PCICR 2 Accessing PCIC I O Space Allocate a 256 byte area to the I O address space Address translation from PCI local bus to SuperHyway bus The lower 8 bits 7 0 a...

Page 585: ...rminated to end the transaction Local Registers Access the local registers using an offset from a PCI local register space base address with the I O read or I O write command Only a single longword access is performed If a burst transfer is attempted it is terminated to end the transaction Control Register PCIECR Do not read or write access to the PCIECR from the PCI local bus 4 Access to this LSI...

Page 586: ...ce lock does not occur Another on chip module can access the PCIC during a lock transfer 6 Endian This LSI supports both the big and little endian formats Since the PCI local bus is inherently little endian the PCIC supports both byte swapping and non byte swapping The endian format is specified by the setting of the TBS bit in the PCI control register PCICR Note In the following figures MSByte me...

Page 587: ...ittle Endian A B C D A B C D Buffer data A B C D A B C D A B C D PCI Address 2 1 PCI Address 2 0 31 0 PCI data SH data A B C D A B C D Buffer data A B C D A B C D A B C D PCI Address 2 0 PCI Address 2 1 2 Big Endian Note PCI Address 2 AD 2 address Figure 13 12 Endian Conversion from PCI Local Bus to SuperHyway bus Non Byte Swapping TBS 0 ...

Page 588: ...C D D B C D A B C D PCI Address 2 1 PCI Address 2 0 31 0 D C B A D C B A D C B A D C B A A B C D PCI Address 2 0 PCI Address 2 1 PCI data SH data 1 Little Endian Buffer data PCI data SH data Buffer data 2 Big Endian Note PCI Address 2 AD 2 address Figure 13 13 Endian Conversion from PCI Local Bus to SuperHyway bus Non Byte Swapping TBS 1 ...

Page 589: ...xecute memory read or write after flush purge request issued to the CPU cache in the access of cache hit It reduces PCI bus transfer speed and CPU performance When using this function do not use the prefetch function Do not set PFE bit in the PCICR to 1 Do not use this function when the CPU is sleep state If cache hit occurs in sleep state it becomes an error access on the SuperHyway bus and memor...

Page 590: ...EJ09B0158 0100 PCI address SuperHyway address Cache snoop address register Cache snoop control register Set issue the flush purge issue the read write Issue the read write compare Hit No hit Figure 13 14 Cache Flush Purge Execution Flow for PCI local Bus to SuperHyway Bus ...

Page 591: ... outputs to external masters 0 to 3 Including the PCIC arbitration of up to five masters is possible 2 Configuration Space Access The PCIC supports configuration mechanism 1 The PCI PIO address register PCIPAR and PCI PIO data register PCIPDR correspond to the configuration address register and configuration data register respectively When PCIPDR is read from or written to after PCIPAR has been se...

Page 592: ...to the PCIPDR 4 Arbitration In host bus bridge mode the PCI bus arbiter in the PCIC is activated The PCIC supports four external masters i e four REQ and GNT pairs If use of the bus is simultaneously requested by more than one device the bus is granted to the device with the highest priority The PCI bus arbiter supports two modes to determine the priority of devices fixed priority and pseudo round...

Page 593: ...the PCIC operates normal mode INTA output is available to the host device on the PCI bus The INTA pin is specified assert or negate by the IOCS bit in the PCICR Table 13 6 Interrupt Priority Signal Interrupt Source Priority PCISERR SERR assertion detected in host bus bridge mode High PCIINTA PCI interrupt A INTA detected in host bus bridge mode PCIINTB PCI interrupt B INTB detected in host bus bri...

Page 594: ...ter that performing bus parking is different from the next transaction master the bus will be high impedance state for minimum one clock cycle before the address phase In normal mode the GNT0 GNTIN pin is used for the grant input signal to the PCIC and the REQ0 REQOUT pin is used for the request output signal from the PCIC 13 4 7 Power Management The PCIC supports PCI power management revision 1 1...

Page 595: ... detects a transition from the power state D0 D1 D2 to D3 Interrupt masks can be set for each interrupt No power state D0 interrupt is generated at a power on reset The following cautions should be noted when the PCIC is operating in normal mode and a power down interrupt is received from the host In PCI power management the PCI local bus clock stops within a minimum of 16 clocks after the host de...

Page 596: ... burst read cycle in normal mode Note that the response speed of DEVSEL and TRDY differs according to the connected target device In host bus bridge mode master accesses always use single read write cycles The issuing of configuration transfers is only possible in host bus bridge mode PCICLK AD 31 0 PAR CBE 3 0 C BE 3 0 PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL REQ GNT Legend Addr AP Com Dn DPn BEn PCI...

Page 597: ...0 PCICLK AD 31 0 PAR PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL REQ GNT D0 DP0 Addr AP BE0 Com CBE 3 0 C BE 3 0 Legend Addr AP Com Dn DPn BEn PCI space address Address parity Command nth data nth data parity nth data byte enable Figure 13 18 Master Read Cycle in Host Bus Bridge Mode Single ...

Page 598: ...K AD 31 0 PAR PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL REQ GNT AP Com Addr D0 D1 Dn BE0 BE1 BEn DP0 DPn DPn 1 CBE 3 0 C BE 3 0 Legend Addr AP Com Dn DPn BEn PCI space address Address parity Command nth data nth data parity nth data byte enable Figure 13 19 Master Write Cycle in Normal Mode Burst ...

Page 599: ...K AD 31 0 PAR PCIFRAME IRDY DEVSEL TRDY LOCK IDSEL REQ GNT AP Com Addr D0 D1 Dn BE0 BE1 BEn DP0 DPn DPn 1 CBE 3 0 C BE 3 0 Legend Addr AP Com Dn DPn BEn PCI space address Address parity Command nth data nth data parity nth data byte enable Figure 13 20 Master Read Cycle in Normal Mode Burst ...

Page 600: ...is completely written to the local memory if reading the target write data immediately after write access Only single transfers are supported in the case of target accesses of the configuration space and I O space If there is a burst access request the external master is disconnected on completion of the first transfer Note that the DEVSEL response speed is fixed at 2 clocks Medium in the case of ...

Page 601: ...PCIFRAME IRDY DEVSEL TRDY STOP LOCK IDSEL REQOUT GNTIN Addr AP D0 DP0 Com Locked At configuration access Disconnect BE0 CBE 3 0 C BE 3 0 Legend Addr AP Com Dn DPn BEn PCI space address Address parity Command nth data nth data parity nth data byte enable Figure 13 21 Target Read Cycle in Normal Mode Single ...

Page 602: ...CIFRAME IRDY DEVSEL TRDY STOP LOCK IDSEL REQOUT GNTIN Addr AP D0 DP0 Com BE0 CBE 3 0 C BE 3 0 Legend Addr AP Com Dn DPn BEn PCI space address Address parity Command nth data nth data parity nth data byte enable Locked At configuration access Disconnect Figure 13 22 Target Write Cycle in Normal Mode Single ...

Page 603: ...AME IRDY DEVSEL TRDY STOP LOCK IDSEL REQ GNT Addr AP D0 DP0 Com BE0 D1 Dn BEn DPn DPn 1 BE1 CBE 3 0 C BE 3 0 Legend Addr AP Com Dn DPn BEn PCI space address Address parity Command nth data nth data parity nth data byte enable Locked Disconnect Figure 13 23 Target Memory Read Cycle in Host Bus Bridge Mode Burst ...

Page 604: ...ME IRDY DEVSEL TRDY STOP LOCK IDSEL REQ GNT Addr AP D0 DP0 Com BE0 D1 Dn BEn DPn DPn 1 BE1 CBE 3 0 C BE 3 0 Legend Addr AP Com Dn DPn BEn PCI space address Address parity Command nth data nth data parity nth data byte enable Locked Disconnect Figure 13 24 Target Memory Write Cycle in Host Bus Bridge Mode Burst ...

Page 605: ...ed logic level in one clock When the PCIC operates as the host bus bridge mode it is recommended to use this function for the issuance of configuration transfers Figure 13 25 is an example of burst memory write cycle with stepping Figure 13 26 is an example of target burst read cycle with stepping PCICLK AD 31 0 PAR PCIFRAME IRDY DEVSEL TRDY Addr D0 Dn Com BE0 BEn AP DP0 DPn DPn 1 D1 BE1 CBE 3 0 C...

Page 606: ...31 0 PAR PCIFRAME IRDY DEVSEL TRDY Addr D1 D0 Com BE0 BEn AP Dn DPn DP0 DPn 1 BE1 CBE 3 0 C BE 3 0 Legend Addr AP Com Dn DPn BEn PCI space address Address parity Command nth data nth data parity nth data byte enable Figure 13 26 Target Memory Read Cycle in Host Bus Bridge Mode Burst with stepping ...

Page 607: ...e Transfer requests External request channel 0 to 3 peripheral module request channel 0 to 5 or auto request can be selected The following modules can issue an peripheral module request SCIF0 SCIF1 HAC HSPI SIOF SSI FLCTL and MMCIF Selectable bus modes Cycle steal mode normal mode and intermittent mode or burst mode can be selected Selectable channel priority levels The channel priority levels are...

Page 608: ...11 n 0 1 2 3 for channels 0 to 5 6 7 8 9 for channels 6 to 11 Note The half end interrupt request is available in channels 0 to 3 CHCRm DARBn DARm DMAE DMAOR0 and DMAOR1 DMA channel control register DMA destination address register B DMA destination address register DMA Address error interrupt request DMA operation registers 0 and 1 DMARS0 to DMARS2 DMINTm SARBn SARm TCRBn TCRm DMA extended resour...

Page 609: ...ion Output Strobe output from channel 0 to external device which has output regarding DMA transfer request DREQ1 1 6 DMA transfer request Input DMA transfer request input from external device to channel 1 DRAK1 2 7 DREQ1 acceptance confirmation Output Notifies acceptance of DMA transfer request and start of execution from channel 1 to external device 1 DACK1 2 8 DMA transfer end notification Outpu...

Page 610: ...pin 5 This pin is multiplexed with MODE0 input pin and port L3 GPIO output pin 6 This pin is multiplexed with port K6 GPIO input output pin 7 This pin is multiplexed with MODE7 input pin and port L0 GPIO output pin 8 This pin is multiplexed with MODE1 input pin and port L2 GPIO output pin 9 This pin is multiplexed with INTB PCIC input pin AUDATA0 H UDI output pin and port K5 GPIO input output pin ...

Page 611: ...SAR2 R W H FC80 8040 H 1C80 8040 32 DMA destination address register 2 DAR2 R W H FC80 8044 H 1C80 8044 32 DMA transfer count register 2 TCR2 R W H FC80 8048 H 1C80 8048 32 DMA channel control register 2 CHCR2 R W 1 H FC80 804C H 1C80 804C 32 3 DMA source address register 3 SAR3 R W H FC80 8050 H 1C80 8050 32 DMA destination address register 3 DAR3 R W H FC80 8054 H 1C80 8054 32 DMA transfer count...

Page 612: ...000 H 1C80 9000 16 2 3 DMA extended resource selector 1 DMARS1 R W H FC80 9004 H 1C80 9004 16 4 5 DMA extended resource selector 2 DMARS2 R W H FC80 9008 H 1C80 9008 16 6 DMA source address register 6 SAR6 R W H FC81 8020 H 1C81 8020 32 DMA destination address register 6 DAR6 R W H FC81 8024 H 1C81 8024 32 DMA transfer count register 6 TCR6 R W H FC81 8028 H 1C81 8028 32 DMA channel control regist...

Page 613: ...ter B6 SARB6 R W H FC81 8120 H 1C81 8120 32 DMA destination address register B6 DARB6 R W H FC81 8124 H 1C81 8124 32 DMA transfer count register B6 TCRB6 R W H FC81 8128 H 1C81 8128 32 7 DMA source address register B7 SARB7 R W H FC81 8130 H 1C81 8130 32 DMA destination address register B7 DARB7 R W H FC81 8134 H 1C81 8134 32 DMA transfer count register B7 TCRB7 R W H FC81 8138 H 1C81 8138 32 8 DM...

Page 614: ...s register 2 DAR2 Undefined Undefined Retained Retained DMA transfer count register 2 TCR2 Undefined Undefined Retained Retained DMA channel control register 2 CHCR2 H 4000 0000 H 4000 0000 Retained Retained 3 DMA source address register 3 SAR3 Undefined Undefined Retained Retained DMA destination address register 3 DAR3 Undefined Undefined Retained Retained DMA transfer count register 3 TCR3 Unde...

Page 615: ...d Retained Retained DMA transfer count register B2 TCRB2 Undefined Undefined Retained Retained 3 DMA source address register B3 SARB3 Undefined Undefined Retained Retained DMA destination address register B3 DARB3 Undefined Undefined Retained Retained DMA transfer count register B3 TCRB3 Undefined Undefined Retained Retained 0 1 DMA extended resource selector 0 DMARS0 H 0000 0000 H 0000 0000 Retai...

Page 616: ...register 9 TCR9 Undefined Undefined Retained Retained DMA channel control register 9 CHCR9 H 4000 0000 H 4000 0000 Retained Retained 6 to 11 DMA operation register 1 DMAOR 1 Undefined Undefined Retained Retained 10 DMA source address register 10 SAR10 Undefined Undefined Retained Retained DMA destination address register 10 DAR10 Undefined Undefined Retained Retained DMA transfer count register 10...

Page 617: ... Undefined Undefined Retained Retained DMA destination address register B9 DARB9 Undefined Undefined Retained Retained DMA transfer count register B9 TCRB9 Undefined Undefined Retained Retained 14 3 1 DMA Source Address Registers 0 to 11 SAR0 to SAR11 SAR are 32 bit readable writable registers that specify the source address of a DMA transfer During a DMA transfer these registers indicate the next...

Page 618: ...4 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W SARB SARB 14 3 3 DMA Destination Address Registers 0 to 11 DAR0 to DAR11 DAR are 32 bit readable writable registers that specify the destination address of a DMA transfer During a DMA transfer t...

Page 619: ...set DARB address that differs from DAR address write data to DARB after DAR To transfer data in word or in longword units specify the address with word or longword address boundary When transferring data in 16 byte or in 32 byte units a 16 byte or 32 byte boundary must be set for the source address value The initial value is undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 ...

Page 620: ... set and 16 777 216 the maximum when H 00000000 is set During a DMA transfer these registers indicate the remaining transfer count The upper eight bits of TCR bits 31 to 24 are always read as 0 and the write value should always be 0 The initial value is undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit Initial value R W Bit Initial value R W R W R ...

Page 621: ...nters values of SAR and DAR are updated after the value of the bits 7 to 0 became 0 and then the value of the bits 23 to 16 of TCRB are loaded to the bits 7 to 0 In bits 23 to 16 set the number of transfers which starts reloading In reload mode a value from H FF 255 times to H 01 1 time can be specified to the bits 23 to 16 and 7 to 0 of TCRB and set the same number in both bits 23 to 16 and bits ...

Page 622: ...alue R W Bit Initial value R W LCKN RPT 2 0 DO RL TS2 HE HIE AM AL DM 1 0 SM 1 0 RS 3 0 DL DS TB TS 1 0 IE TE DE Bit Bit Name Initial Value R W Descriptions 31 0 R Reserved This bit is always read as 0 The write value should always be 0 30 LCKN 1 R W Bus Lock Signal Disable Specifies whether enable or disable the bus lock signal output when a read instruction for the SuperHyway bus This bit is eff...

Page 623: ...ad mode SAR DAR used as reload area 110 Reload mode DAR used as reload area 111 Reload mode SAR used as reload area 24 0 R Reserved This bit is always read as 0 The write value should always be 0 23 DO 0 R W DMA Overrun Selects whether DREQ is detected by overrun 0 or by overrun 1 This bit is valid only in CHCR0 to CHCR3 0 Detects DREQ by overrun 0 1 Detects DREQ by overrun 1 22 RL 0 R W Request C...

Page 624: ...fer destination is a register of an peripheral module that access size is designated the transfer size for the register should be the same value of its access size For the transfer source or destination address specified by SAR or DAR an address boundary should be set according to the transfer data size TS 2 0 000 Byte units transfer 001 Word 2 byte units transfer 010 Longword 4 byte units transfe...

Page 625: ...mum number H 0000 0000 The HE bit is not set when transfers are ended by an NMI interrupt or address error or by clearing the DE bit or the DME bit in DMAOR before the number of transfers is decreased to half of the TCR value set preceding the transfer The HE bit is kept set when the transfer ends by an NMI interrupt or address error or clearing the DE bit bit 0 or the DME bit in DMAOR after the H...

Page 626: ...the half end of the transfer execute a dummy read of the destination space and issue the SYNCO instruction Clear this bit to 0 while reload mode is set This bit is valid in CHCR0 to CHCR3 and CHCR6 to CHCR9 0 Disables the half end interrupt 1 Enables the half end interrupt 17 AM 0 R W Acknowledge Mode Selects whether DACK is output in data read cycle or in data write cycle This bit is valid only i...

Page 627: ...10 Destination address is decremented 1 in byte units transfer 2 in word units transfer 4 in longword units transfer Setting prohibited in 16 32 byte units transfer 11 Setting prohibited 13 12 SM 1 0 00 R W Source Address Mode 1 0 Specify whether the DMA source address is incremented decremented or left fixed 00 Fixed source address 01 Source address is incremented 1 in byte units transfer 2 in wo...

Page 628: ...nal request can be selected in CHCR4 to CHCR11 DMA extended resource selector is valid only in CHCR0 to CHCR5 7 6 DL DS 0 0 R W R W DREQ Level and DREQ Edge Select Specify the detecting method of the DREQ pin input and the detecting level These bits are valid only in CHCR0 to CHCR3 In channels 0 to 3 also if the transfer request source is specified as a peripheral module or if an auto request is s...

Page 629: ...errupt request is disabled 1 Interrupt request is enabled 1 TE 0 R W Transfer End Flag Shows that DMA transfer ends The TE bit is set to 1 when TCR becomes to 0 and the DMAC starts executing the final DMA transfer The TE bit is not set to 1 in either of the following cases DMA transfer ends due to an NMI interrupt or DMA address error before TCR is cleared to 0 DMA transfer is ended by clearing th...

Page 630: ...time all of the bits TE NMIF and AE in DMAOR must be 0 In an external request or peripheral module request DMA transfer starts if DMA transfer request is generated by the devices or peripheral modules after setting the bits DE and DME to 1 In this case however all of the bits TE NMIF and AE must be 0 which is the same as in the case of auto request mode Clearing the DE bit to 0 can terminate the D...

Page 631: ...value R W Bit Bit Name Initial Value R W Descriptions 15 14 All 0 R Reserved These bits are always read as 0 The write value should always be 0 13 12 CMS 1 0 00 R W Cycle Steal Mode Select 1 0 Select either normal mode or intermittent mode in cycle steal mode It is necessary that all channels 0 to 5 DMAOR0 or 6 to 11 DMAOR1 bus modes are set to cycle steal mode to make valid intermittent mode 00 N...

Page 632: ...e in channels 0 to 5 or 6 to 11 respectively 7 to 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 AE 0 R W Address Error Flag Indicates that an address error occurred during DMA transfer This bit is set under following conditions The value set in SAR or DAR does not match to the transfer size boundary The transfer source or transfer destination is invalid sp...

Page 633: ...terrupt was input 0 No NMI interrupt Clearing condition Writing NMIF 0 after NMIF 1 read 1 NMI interrupt occurs 0 DME 0 R W DMA Master Enable Enables or disables DMA transfers on all channels 0 to 5 DMAOR0 or 6 to 11 DMAOR1 If the DME bit and the DE bit in CHCR are set to 1 transfer is enabled In this time all of the bits TE in CHCR NMIF and AE in DMAOR must be 0 If this bit is cleared during tran...

Page 634: ...DMARS is valid only when the resource select bits RS 3 0 has been set to B 1000 for CHCR0 to CHCR5 registers Otherwise even if DMARS has been set transfer request source is not accepted DMARS0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W C1MID 5 0 C1RID 1 0 C0MID 5 0 C0RID 1 0 Bit Bit Nam...

Page 635: ... 0 C3RID 1 0 C2MID 5 0 C2RID 1 0 Bit Bit Name Initial Value R W Descriptions 15 to 10 C3MID 5 0 000000 R W Transfer request module ID5 to ID0 for DMA channel 3 MID See table 14 4 9 8 C3RID 1 0 00 R W Transfer request register ID1 and ID0 for DMA channel 3 RID See table 14 4 7 to 2 C2MID 5 0 000000 R W Transfer request module ID5 to ID0 for DMA channel 2 MID See table 14 4 1 0 C2RID 1 0 00 R W R W ...

Page 636: ... 5 0 C5RID 1 0 C4MID 5 0 C4RID 1 0 Bit Bit Name Initial Value R W Descriptions 15 to 10 C5MID 5 0 000000 R W Transfer request module ID5 to ID0 for DMA channel 5 MID See table 14 4 9 8 C5RID 1 0 00 R W Transfer request register ID1 and ID0 for DMA channel 5 RID See table 14 4 7 to 2 C4MID 5 0 000000 R W Transfer request module ID5 to ID0 for DMA channel 4 MID See table 14 4 1 0 C4RID 1 0 00 R W Tr...

Page 637: ... SCIF0 H 22 B 001000 B 10 Receive H 29 B 01 Transmit SCIF1 H 2A B 001010 B 10 Receive H 41 B 01 Transmit HAC H 42 B 010000 B 10 Receive H 45 B 01 Transmit HSPI H 46 B 010001 B 10 Receive H 51 B 01 Transmit SIOF H 52 B 010100 B 10 Receive SSI H 73 B 011100 B 11 Transmit and receive H 83 B 100000 B 11 Transmit and receive the data part FLCTL H 87 B 100001 B 11 Transmit and receive the control code p...

Page 638: ...When there is no transfer request signal from an external source as in a memory to memory transfer or a transfer between memory and an on chip module unable to request a transfer auto request mode allows the DMAC to automatically generate a transfer request signal internally Specify B 0100 to the RS 3 0 bits in CHCRn n 0 to 11 of the using DMA channel When the DE bit in CHCR for corresponding chan...

Page 639: ...en performed as requests Overrun 1 Transfer is aborted after transfers have been performed for the number of requests plus 1 times The DO bit in CHCR selects this overrun 0 or overrun 1 Table 14 6 Selecting External Request Detection with DO Bit CHCR DO External Request 0 Overrun 0 initial value 1 Overrun 1 Peripheral module Request Mode In this mode a transfer is performed at the transfer request...

Page 640: ...quest of the SCIF0 is set as the transfer request the transfer destination must be the SCIF0 s transmit data register Likewise when receive data full transfer request of the SCIF0 is set as the transfer request the transfer source must be the SCIF0 s receive data register These conditions also apply to the SCIF1 HAC HSPI SIOF SSI and MMCIF ...

Page 641: ...smitter Transmit data Any SPTBR Cycle steal 010001 10 HSPI receiver Receive data SPRBR Any Cycle steal 01 SIOF transmitter TXI transmit FIFO data empty interrupt Any SITDR Cycle steal 010100 10 SIOF receiver RXI receive FIFO data full interrupt SIRDR Any Cycle steal SSI transmitter Transmit mode DMRQ 1 Transmit data empty request Any SSITDR Cycle steal 011100 11 SSI receiver Receive mode DMRQ 1 Re...

Page 642: ...e priority levels among the channels remain fixed There are two kinds of fixed modes as follows Channels 0 to 5 CH0 CH1 CH2 CH3 CH4 CH5 CH0 CH2 CH3 CH1 CH4 CH5 Channels 6 to 11 CH6 CH7 CH8 CH9 CH10 CH11 CH6 CH8 CH9 CH7 CH10 CH11 These are selected by the bits PR 1 0 in DMAOR0 and DMAOR1 Round Robin Mode In round robin mode each time data of one transfer unit byte word longword 16 byte or 32 byte u...

Page 643: ...y The priority of channels 0 and 1 which were higher than channel 2 are also shifted If immediately after there is a request to transfer channel 5 only channel 5 becomes bottom priority and the priority of channels 3 and 4 which were higher than channel 5 are also shifted Channel 1 becomes bottom priority The priority of channel 0 which was higher than channel 1 is also shifted Channel 0 becomes b...

Page 644: ...west priority 5 At this point channel 1 has a higher priority than channel 3 so the channel 1 transfer begins channel 3 waits for transfer 6 When the channel 1 transfer ends channel 1 becomes lowest priority 7 The channel 3 transfer begins 8 When the channel 3 transfer ends channels 3 and 2 shift downward in priority so that channel 3 becomes the lowest priority Transfer request Waiting channel s ...

Page 645: ...e At this time transfer data is temporarily stored in the DMAC In the transfer between external memories as shown in figure 14 4 data is read to the DMAC from one external memory in a data read cycle and then that data is written to the other external memory in a write cycle Data buffer Address bus Data bus Address bus Data bus Memory Transfer source module Transfer destination module Memory Trans...

Page 646: ... output in read cycle or write cycle Figure 14 5 shows an example of DMA transfer timing in dual address mode CLKOUT A25 to A0 Note In transfer between external memories with DACK output in the read cycle DACK output timing is the same as that of CSn D31 to D0 WE RD DACK Low active CSn Transfer source address Transfer destination address Data read cycle Data write cycle 1st cycle 2nd cycle Figure ...

Page 647: ...r unit When that transfer ends the bus mastership is passed to the other bus master This is repeated until the transfer end conditions are satisfied In cycle steal normal mode transfer areas are not affected regardless of settings of the transfer request source transfer source and transfer destination Figure 14 6 shows an example of DMA transfer timing in cycle steal normal mode Transfer condition...

Page 648: ...64 clocks in Bck count and obtains the bus mastership from other bus master The DMAC then transfers data of one transfer unit and returns the bus mastership to other bus master These operations are repeated until the transfer end condition is satisfied It is thus possible to make lower the ratio of bus occupation by DMA transfer than cycle steal normal mode When the DMAC issues again the transfer ...

Page 649: ...n burst mode CPU CPU CPU DMAC DMAC DMAC DMAC DMAC DMAC CPU DREQ Read Read Read Write Write Write SuperHyway bus cycle Figure 14 9 DMA Transfer Timing Example in Burst Mode DREQ Low Level Detection DMA Transfer Matrix Table 14 8 shows the DMA transfer matrix in auto request mode and table 14 9 shows the DMA transfer matrix in external request mode and table 14 10 shows the peripheral module request...

Page 650: ...he transfer size should be the same value of its access size 2 Transfer is available when the AM bit in CHCR is cleared to 0 3 Transfer is available when the AM bit in CHCR is set to 1 4 Transfer is available when the AM bit in CHCR is set to 1 and the destination address of the PCIC is H FD00 0000 to H FDFF FFFF PCI memory space 0 5 Transfer is available when the AM bit in CHCR is cleared to 0 an...

Page 651: ...pheral module the transfer is available in channel 0 to 5 Bus Mode and Channel Priority When the priority is set in fixed mode CH0 CH1 and channel 1 is transferring in burst mode if there is a transfer request to channel 0 with a higher priority the transfer of channel 0 will begin immediately At this time if channel 0 is also operating in burst mode the channel 1 transfer will continue after the ...

Page 652: ...peration register DMAOR and DMA extended resource selectors DMARS are set the DMAC transfers data according to the following procedure 1 Checks to see if transfer is enabled DE 1 DME 1 TE 0 AE 0 NMIF 0 2 When a transfer request occurs while transfer is enabled the DMAC transfers one transfer unit of data depending on the TS0 and TS1 settings In auto request mode the transfer begins automatically w...

Page 653: ...rupt request IE 1 NMIF 1 or AE 1 or DE 0 or DME 0 HIE 0 or HE 1 TCR TCRB 2 Yes Yes Yes TCR 0 Repeat mode NMIF 1 or AE 1 or DE 0 or DME 0 HE 1 DMINT interrupt request HIE 1 Notes 1 In repeat mode a transfer request is acceptted with TE 1 when HIE 1 and HE 0 half end interrupt is enable and clear the HE to 0 after HE is set to 1 2 In auto request mode transfer starts when bits NMIF AE and TE are all...

Page 654: ... area Bit HIE B 1 TCR 2 interrupt generated Bits DM 1 0 B 01 DAR incremented Bits SM 1 0 B 00 SAR fixed Bit IE B 1 Interrupt enabled Bit DE B 1 DMA transfer enabled Set such as bits TB and TS 2 0 according to use conditions Set bits CMS 1 0 and PR 1 0 in DMAOR according to use conditions and set the DME bit to B 1 2 Voice data is received and then transferred by SIOF DMAC 3 TCR is decreased to hal...

Page 655: ...alue set in SARB DARB is set to SAR DAR and the value of bits TCRB 23 16 is set in bits TCRB 7 0 at each transfer set in the bits TCRB 7 0 and the transfer is repeated until TCR becomes 0 without specifying the transfer settings again A reload mode transfer is effective when repeating data transfer with specific area Figure 14 12 shows the operation of reload mode transfer DMAC Bits RPT 2 0 SHwy b...

Page 656: ...tarted 1st acceptance 2nd acceptance Non sensitive period DMAC Figure 14 13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection CPU CPU DMAC CLKOUT CPU CPU DMAC CLKOUT DREQ Overrun 0 Low level DACK Low active DRAK Low active DRAK Low active Bus cycle Acceptance started 1st acceptance 2nd acceptance DREQ Overrun 1 Low level DACK Low active Bus cycle Acceptance started 1st acceptance ...

Page 657: ...REQ Input Detection in Burst Mode Edge Detection CPU DMAC CLKOUT CPU CLKOUT DREQ Overrun 0 Low level DRAK Low active Bus cycle Acceptance started 1st acceptance DREQ Overrun 1 Low level DRAK Low active DACK Low active DACK Low active Bus cycle 1st acceptance 3rd acceptance Acceptance started Acceptance started Non sensitive period 2nd acceptance 2nd acceptance DMAC DMAC Figure 14 16 Example of DRE...

Page 658: ...rror is occurred after execute the following procedure and then start a transfer 1 Dummy read for the below listed registers BCR LBSC PCIECR PCIC MIM DDRIF INTC2B3 INTC 2 Issue the SYNCO instruction 3 Set registers of all channels again If the AE bit in DMAOR0 is set to 1 channels 0 to 5 should be set again If the AE bit in DMAOR1 is set to 1 channels 6 to 11 should be set again 14 5 3 Notes on Bu...

Page 659: ...s negated between bus cycles the DREQ signal is not sampled correctly and malfunction may occur Notes 1 When a DMA transfer is performed with larger transfer size than the bus width For example performing the 16 32 byte transfer to the 8 16 32 bit bus width LBSC space longword 32 bit transfer to the 8 16 bit bus width LBSC space or word 16 bit transfer to the 8 bit bus width LBSC space Note that e...

Page 660: ...er destination are the LBSC spaces does not apply this Table 14 11 to 14 14 shows the register settings that whether or not the negation of the DACK output with the number of bus cycle generation of the DMA transfer The DACK is not negated when the number of the bus cycle that generated in the DMA transfer is 1 Note that in the following settings when either the transfer source or the transfer des...

Page 661: ...is not negated Bus Width bit DMA Transfer Access Size Bus Cycle Number CSnBCR IWRRD IWRRS or IWW CSnWCR ADS and ADH Byte 1 Any Any Word 2 Any B 000 Longword 4 Any B 000 16 Byte 16 B 000 B 000 8 32 Byte 32 Any B 000 Byte 1 Any Any Word 1 Any Any Longword 2 Any B 000 16 Byte 8 B 000 B 000 16 32 Byte 16 Any B 000 Byte 1 Any Any Word 1 Any Any Longword 1 Any Any 16 Byte 4 B 000 B 000 32 32 Byte 8 Any ...

Page 662: ... Any 16 Byte 8 B 000 16 32 Byte 16 Any Table14 13 Register Settings for MPX Interface Read Access Register Settings of CSn is not negated Bus Width bit DMA Transfer Access Size Bus Cycle Number CSnBCR IWRRD or IWRRS Byte 1 Any Word 1 Any Longword 1 Any 16 Byte 4 Impossible Negated 32 32 Byte 1 Any Table14 14 Register Settings for MPX Interface Write Access Register Settings of CSn is not negated B...

Page 663: ...y bus and peripheral clocks Pck which are used to interface with on chip peripheral modules Generates SH7780 external bus clocks SH7780 external bus clocks are the bus clock Bck which is used to interface with the external devices and memory clocks DDRck which are used in the DDRIF Selects two clock modes Selects a crystal resonator or an externally input clock as the CPG clock input Changes frequ...

Page 664: ...ontroller Divider 1 2 1 4 1 5 1 6 1 8 1 12 1 16 1 24 Oscillator XTAL CLKOUT Bus clock Bck CPU clock Ick SuperHyway clock SHck Peripheral clock Pck DDR clock DDRck MODE 7 MODE 2 MODE 1 MODE 0 MODE8 EXTAL PLLCR MSTPCR Bus interface Peripheral bus Legend FRQCR Frequency control register MSTPCR Standby control register see section 17 Power Down Mode PLLCR PLL control register Figure 15 1 Block Diagram...

Page 665: ...of the bus clock Bck and the clock signal output from the CLKOUT pin that is used as the external peripheral interface clock Crystal oscillator circuit Used when a crystal resonator is connected to the XTAL and EXTAL pins Use of the crystal oscillator circuit can be selected with the MODE8 pin Divider The divider generates the CPU clock Ick SuperHyway clock SHck on chip peripheral module clock Pck...

Page 666: ...nput Selects use non use of crystal resonator When MODE8 is low external clock is input from the EXTAL pin When MODE8 is high crystal resonator connected directly to the EXTAL and XTAL pins XTAL Output This pin is connected to a crystal resonator EXTAL Input This pin is connected to a crystal oscillator to input an external clock or is connected to a crystal resonator CLKOUT Clock Pins Output This...

Page 667: ...15 2 Clock Operating Modes Mode Control Pin Setting Frequency Multiplication Ratio to Input Clock Clock Operating Mode MODE7 MODE2 MODE1 MODE0 PLL1 PLL2 Ick SHck Pck DDRck Bck FRQCR Initial Value 0 Low Low Low Low On 12 6 3 2 24 5 3 H 1023 3335 1 Low Low Low High On 12 6 1 24 5 2 H 1024 4336 2 Low Low High Low On 12 6 3 2 24 5 3 2 H 1025 5335 3 Low Low High High On 12 6 1 24 5 1 H 1026 6336 12 Hig...

Page 668: ... control register MSTPCR R W H FFC8 0030 H 1FC8 0030 32 Pck Note For MSTPCR see section 17 Power Down Mode Table 15 4 Register States of CPG in Each Processing Mode Register Name Abbreviation Power on Reset by PRESET Pin Power on Reset by WDT H UDI Manual Reset by WDT Multiple Exception Sleep by Sleep Instruction Frequency control register FRQCR H 1xxx x3xx 2 H 1xxx x3xx 2 Retained Retained PLL co...

Page 669: ... R R R R R R R BIt Note The initial values of these fields after power on reset depend on the mode pins setting see table 15 2 Initial value R W Bit Bit Name Initial Value R W Description 31 to 28 0001 R Reserved These bits are always read as 0001 The write value should always be 0001 27 to 25 000 R Reserved These bits are always read as 0 The write value should always be 0 Writing to other than 0...

Page 670: ...al value of this field after power on reset depends on the mode pins setting see table 15 2 Writing is ignored 11 to 8 0011 R Reserved These bits are always read as 0011 The write value should always be 0011 7 to 4 0 Undefined Undefined Undefined R Reserved The initial value of this field after power on reset depends on the mode pins setting see table 15 2 Writing is ignored 3 2 1 0 P1FC3 P1FC2 P1...

Page 671: ... R R W R R R R R R R R R R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 31 to 16 All 0 R Reserved These bits are always read as 0 The write value should always be 0 15 to 13 All 1 R Reserved This bit is always read as 1 The write value should always be 1 Writing 0 to any of these bits the operation of this LSI is not guaranteed 12 to 2 All 0 R Reserved These bits are al...

Page 672: ...e damping resistance should be determined after consultation with the crystal resonator manufacturer EXTAL CL2 CL1 Crystal Resonator Avoid crossing signal lines Recommended values CL1 CL2 0 to 33 pF R 0 Ω Figure 15 2 Points for Attention when Using Crystal Resonator When Inputting External Clock from EXTAL Pin Make no connection to the XTAL pin When Using PLL and DLL circuit Separate each VDD PLL ...

Page 673: ...B1 Recommended values RCB1 RCB2 RCB3 4 7Ω CPB11 CPB21 CPB31 0 1µF CPB12 CPB22 CPB32 1µF RD1 RD2 20Ω CD11 CD21 0 1µF CD12 CD22 1µF 1 25V 1µF 4 7Ω 4 7 Ω 4 7 Ω CPB21 0 1µF CPB22 RCB2 1µF CPB31 0 1µF CPB32 RCB3 1µF VDD DLL1 VSS DLL1 VDD DLL2 VSS DLL2 1 25V 20 Ω 20 Ω CD11 0 1µF CD12 RD1 1µF CD21 0 1µF CD22 RD2 1µF Figure 15 3 Points for Attention when Using PLL and DLL Circuit ...

Page 674: ...Section 15 Clock Pulse Generator CPG Rev 1 00 Dec 13 2005 Page 624 of 1286 REJ09B0158 0100 ...

Page 675: ...fied intervals The watchdog timer unit generates a reset for on chip peripheral modules when a WDT overflow occurs A power on reset or a manual reset can be selectable when a manual reset is selected the MRESETOUT pin is asserted Generates the interval timer interrupt when counter overflow occurs in interval timer mode The maximum time until the watchdog timer overflows is approximately 21 seconds...

Page 676: ...2 WDTCNT WDTCSR WDTST Comparator Reset control circuit CPG Internal reset request Interrupt control circuit INTC Peripheral clock Legend WDTBCNT Watchdog timer base counter WDTBST Watchdog timer base stop time register WDTCNT Watchdog timer counter WDTCSR Watchdog timer control status register WDTST Watchdog timer stop time register WDTBCNT WDTBST Overflow Count up signal Clear Figure 16 1 Block D...

Page 677: ... on reset MRESETOUT 1 Manual reset output Output Low level output during manual reset execution STATUS1 2 Processing state 1 Indicate the processor s operating status STATUS0 3 Processing state 0 Output STATUS1 High High Low STATUS0 High Low Low Operating Status Reset Sleep mode Normal operation Notes 1 This pin is multiplexed with the DMAC H UDI and GPIO pin 2 This pin is multiplexed with the CMT...

Page 678: ... W H FFCC 0008 H 1FCC 0008 32 Pck Watchdog timer counter WDTCNT R H FFCC 0010 H 1FCC 0010 32 Pck Watchdog timer base counter WDTBCNT R H FFCC 0018 H 1FCC 0018 32 Pck Table 16 3 Register States in Each Processing Mode Register Name Abbreviation Power on Reset by PRESET Pin Power on Reset by WDT H UDI Manual Reset by WDT Multiple Exception Sleep by SLEEP Instruction Watchdog timer stop time register...

Page 679: ...value of bits 31 to 24 is always H 00 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R W R W R W R W R W R W R W R W Bit Initial value Given code R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTST R W R W R W R W R W R W R W R W R W R W R W R W R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 31 t...

Page 680: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 IOVF WOVF RSTS WT IT TME R R R R W R W R W R W R W R R R R R R R R Bit Initial value R W Given code Bit Bit Name Initial Value R W Description 31 to 24 Given code H 00 R W Reserved Given code for writing These bits are always read as H 00 To write to this register the write value must be H A5 23 to 8 All 0 R Reserved These bits are always read as 0 The write value shou...

Page 681: ...tes that WDTCNT has overflowed in interval timer mode This flag is not set in watchdog timer mode 0 An overflow has not occurred 1 An overflow on WDTCNT has occurred 2 to 0 R All 0 Reserved These bits are always read as 0 The write value should always be 0 16 3 3 Watchdog timer Base Stop Time Register WDTBST WDTBST is a readable writable 32 bit register that clears WDTBCNT Use a longword write acc...

Page 682: ... R R R R R R R R Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 WDTCNT R R R R R R R R R R R R R R R R Bit Initial value R W 16 3 5 Watchdog Timer Base Counter WDTBCNT WDTBCNT is a 32 bit read only register that comprises 18 bit counter and counts up on the peripheral clock Pck When WDTBCNT overflows WDTCNT is counted up and WDTBCNT is cleared to 0 Writ...

Page 683: ... WT IT bit in the WTCSR is 1 and the RSTS bit is 0 The H UDI reset occurs for details see section 30 User Debugging Interface H UDI Power_on_reset EXPEVT H 0000 0000 VBR H 0000 0000 SR MD 1 SR RB 1 SR BL 1 SR I0 I3 B 1111 SR FD 0 Initialize_CPU Initialize_Module PowerOn PC H A000 0000 2 Manual reset When a general exception other than a user break occurs while the BL bit is set to 1 in SR When the...

Page 684: ...w See section 16 4 5 Clearing WDT Counter for WDT counter clear method 5 When the WDTCNT overflows the WDT sets the WOVF flag in WDTCSR to 1 and generates a reset of the type specified by the RSTS bit After reset operation the WDTCNT and WDTBCNT continues counting again 16 4 3 Using Interval timer mode When the WDT is operating in interval timer mode an interval timer interrupt is generated each t...

Page 685: ...NT value Reset internal Interval timer mode WDT mode Figure 16 2 WDT Counting Up Operation 16 4 4 Time for WDT Overflow WDTBCNT is a 18 bit up counter operated on the peripheral clock Pck WDTBCNT is cleared when H 55 is set to the bits 31 to 24 in WDTBST If the peripheral clock frequency is 50 MHz the WDTBCNT overflow time is approximately 5 243 ms 2 18 bit 1 50 MHz WDTCNT is a 12 bit counter star...

Page 686: ... high level to the PRESET pin during the synchronization settling time of the PLL The PLL synchronization settling time is the total value of the PLL1 synchronization settling time and the PLL2 synchronization settling time After the PRESET pin input level is changed from low level to high level the reset state is continued during the reset holding time in the LSI The reset holding time is 20 cloc...

Page 687: ...ime Reset holding time XTAL oscillator Figure 16 3 STATUS Output during Power on PRESET input during normal operation It is necessary to ensure the PLL synchronization settling time when the PRESET input during normal operation CLKOUT output STATUS 1 0 output HH reset LL normal LL normal PLL synchronization settling time Reset holding time XTAL oscillator PRESET input Figure 16 4 STATUS Output by ...

Page 688: ...Overflow The transition time from the watchdog timer overflowed to the power on reset state watchdog timer reset setup time is 1 clock cycle of the XTAL clock and thereafter equal to or more than 5 clock cycles of the peripheral clock Pck The power on reset time watchdog timer reset holding time by the watchdog timer overflowed is 3774 clock cycles of the XTAL clock and thereafter equal to or more...

Page 689: ... WDT reset setup time WDT reset holding time XTAL oscillator Figure 16 6 STATUS Output by Watchdog timer overflow Power On Reset during Normal Operation Power On Reset by Watchdog timer Overflowed in Sleep Mode CLKOUT output STATUS 1 0 output WDT overflow signal HH reset HL sleep LL normal XTAL oscillator WDT reset setup time WDT reset holding time Figure 16 7 STATUS Output by Watchdog timer overf...

Page 690: ...timer overflowed is equal to or more than 3774 clock cycles of the XTAL clock The STATUS 1 0 pins output timing that indicates the reset state or a normal operation is asynchronous with both the XTAL clock and the CLKOUT pin output clock because the STATUS 1 0 pins output timing is synchronous with the peripheral clock Pck Manual Reset by Watchdog timer Overflowed in Normal Operation CLKOUT output...

Page 691: ...nual Reset by Watchdog timer Overflowed in Sleep Mode CLKOUT output WDT overflow signal STATUS 1 0 output HH reset HL sleep LL normal XTAL oscillator WDT reset setup time WDT reset holding time MRESETOUT output Figure 16 9 STATUS Output by Watchdog timer overflow Manual Reset during Sleep Mode ...

Page 692: ...Section 16 Watchdog Timer and Reset Rev 1 00 Dec 13 2005 Page 642 of 1286 REJ09B0158 0100 ...

Page 693: ... the RTC is held and other power supplies are turned off Supports DDR SDRAM power supply backup mode where the power supply for only the 2 5 V power supplied modules are held and other power supplies are turned off 17 1 1 Types of Power Down Modes The types and functions of power down modes are as shown below Sleep mode Module standby state RTC power supply backup mode DDR SDRAM power supply backu...

Page 694: ...ted Halted Halted Halted All modules except for the 2 5 V interfaces are in high impedance states Self refresh Power on reset RTC power supply backup 2 3 4 See section 17 7 Halted Halted Retained Halted Operated Halted All modules except for the RTC interface are in the high impedance states Undefined Refresh is not performed Power on reset Notes 1 Because power supplies 1 25 V and 3 3 V other tha...

Page 695: ...ns are multiplexed with the CMT pins 17 3 Register Descriptions Table 17 3 shows the register configuration for power down mode Table 17 4 shows the register states in each processing mode Table 17 3 Register configuration Register Name Abbreviation R W P4 Address Area 7 Address Access Size Sync clock Standby control register MSTPCR R W H FFC8 0030 H 1FC8 0030 32 Pck Table 17 4 Register States in ...

Page 696: ...STP21 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 R R R R R R W R R R R R R R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 22 All 0 R Reserved These bits are always read as 0 The write value should always be 0 21 MSTP21 0 R W Module Stop Bit 21 To make a transition to the DMAC module standby mode confirm that the DME bits in DMA opera...

Page 697: ... The write value should always be 0 5 to 0 MSTP 5 0 All 0 R W Module Stop Bit 5 0 0 Supplies the clock to the corresponding module 1 Stops the clock supply to the corresponding module 5 SCIF channel 0 4 SCIF channel 1 3 SIOF 2 HSPI 1 SSI 0 HAC Note If the sleep instruction is issued or the operating frequency is changed note the below 1 and 2 when the DMAC module proceed to its module standby mode...

Page 698: ...ATUS1 pin and a low level signal at the STATUS0 pin 17 4 2 Cancellation of Sleep Mode The sleep mode is canceled by an interrupt NMI IRQ IRL 7 0 or on chip modules and a reset Since an interrupt is accepted in sleep mode even if the BL bit in SR is set to 1 save the contents of SPC and SSR to the stack before executing the SLEEP instruction when necessary Cancellation by Interrupt The sleep mode c...

Page 699: ...n to the module standby state The registers keep the contents before halted and the external pins keep the functions before halted At waking up from the module standby state operation is restarted from the condition immediately before the registers and external pins have halted Note Make sure to set the MSTP bit to 1 while the modules have completed the operation and are in an idle state with no i...

Page 700: ...e DRE bit in MIM to 1 causes the DDRIF to start the sequence for a transition to the self refresh mode For details see section 12 5 5 1 Self Refresh Mode SMS Bits Bits 2 to 0 in SCR SMS B 011 These bits are used to assert the CKE signal high and to cancel the self refresh mode with the DESL command BKPRST Signal To prevent the CKE signal from being unstable when turning on or off the LSI power sup...

Page 701: ... automatically issued and the CKE signal will be driven to low by the DDRIF After that the DDR SDRAM will automatically enter the power down mode D The SELFS bit in MIM is set to 1 E Drive the BKPRST signal from high to low Immediately after the system power supply is turned off the CKE output may be unstable Before turning off the system power supply use the external BKPRST signal to keep the CKE...

Page 702: ...ALL and REFA commands Set MIM to issue self refresh command Set MIM SELFS 1 Drive BKPRST high to low Turn off system power supply Time Processing Command REFA NOP PREALL REFA REFS Low High CKE SDRAM State Performs auto refresh at regular intervals Enters idle state after refreshing once Performs self refresh Figure 17 2 Sequence for Turning Off System Power Supply in Self Refresh Mode ...

Page 703: ...upply backup mode is cancelled by a power on reset Even if an interrupt occurs during the RTC power supply backup mode it is invalid because of the power on reset The cancellation procedure is as follows 1 The PRESET signal is low before the VDD power supply starts 2 Negate the XRTCSTBI signal after the VDD becomes stable and ensure the power on oscillation settling time to prevent the LSI from be...

Page 704: ...D XRTCSTBI PRESET 1 1 Power on oscillation settling time 2 Internal reset delay time to the RTC 2 System power supply turned off System power supply turned on RTC power supply backup canceled Power on reset canceled min 1 ms min 1 ms Figure 17 3 Sequence for Turning System Power Supply On Off ...

Page 705: ...0100 17 8 Mode Transitions Figure 17 4 shows the mode transitions Power off state Multiplication ratio change Sleep Normal operation 1 Power on oscillation settling time Module standby DDR SDRAM power supply backup RTC power supply backup 1 1 Figure 17 4 Mode Transition Diagram ...

Page 706: ... Pin Change Timing 17 9 1 In Reset Refer to section 16 5 Status Pin Change Timing during Reset 17 9 2 In Sleep Figure 17 5 shows the state of output pins in sleep mode Interrupt request LL Normal HL Sleep LL Normal CLKOUT IRQOUT STATUS 1 0 Figure 17 5 Status Pins Output from Sleep to Interrupt ...

Page 707: ...rnal clock is selected or input capture function is used for each channel 32 bit timer constant register for auto reload use readable writable at any time and 32 bit down counter provided for each channel Selection of seven counter input clocks Channel 0 to 2 RTC clock RTCCLK and five peripheral clocks Pck 4 Pck 16 Pck 64 Pck 256 and Pck 1024 Pck is the peripheral clock Selection of six counter in...

Page 708: ... Pck TCR TSTR0 TCOR TCR TCOR TCOR TCPR TSTR1 TCNT TCOR TCPR TCR TOCR TSTR0 TSTR1 Timer counter Timer constant register Input capture register 2 only in channel 2 Timer control register Timer output control register Timer start register TOCR TCR TCNT TCNT TCNT Channel 0 1 Channel 2 Channel 3 4 5 TCLK controller Clock controller Interrupt controller Clock controller Interrupt controller Clock contro...

Page 709: ...able 18 1 shows the TMU pin configuration Table 18 1 Pin Configuration Pin Name Function I O Description TCLK Clock input output I O Channel 0 1 and 2 external clock input pin channel 2 input capture control input pin RTC output pin shared with RTC Note This pin is multiplexed with the LBSC and GPIO pins ...

Page 710: ... 32 Pck 1 Timer control register 1 TCR1 R W H FFD8 001C H 1FD8 001C 16 Pck Timer constant register 2 TCOR2 R W H FFD8 0020 H 1FD8 0020 32 Pck Timer counter 2 TCNT2 R W H FFD8 0024 H 1FD8 0024 32 Pck Timer control register 2 TCR2 R W H FFD8 0028 H 1FD8 0028 16 Pck 2 Input capture register 2 TCPR2 R H FFD8 002C H 1FD8 002C 32 Pck 3 4 5 Common Timer start register 1 TSTR1 R W H FFDC 0004 H 1FDC 0004 ...

Page 711: ... TCR1 H 0000 H 0000 Retained Retained Timer constant register 2 TCOR2 H FFFF FFFF H FFFF FFFF Retained Retained Timer counter 2 TCNT2 H FFFF FFFF H FFFF FFFF Retained Retained Timer control register 2 TCR2 H 0000 H 0000 Retained Retained 2 Input capture register 2 TCPR2 Retained Retained Retained Retained 3 4 5 Common Timer start register 1 TSTR1 H 00 H 00 Retained Retained Timer constant register...

Page 712: ... 0 0 0 0 0 0 TCOE R W R R R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 7 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 TCOE 0 R W Timer Clock Pin Control Specifies whether timer clock pin TCLK is used as the external clock or input capture control input pin or as the on chip RTC output clock output pin 0 Timer clock pin TCL...

Page 713: ...al Value R W Description 7 to 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 STR2 0 R W Counter Start 2 Specifies whether TCNT2 is operated or stopped 0 TCNT2 count operation is stopped 1 TCNT2 performs count operation 1 STR1 0 R W Counter Start 1 Specifies whether TCNT1 is operated or stopped 0 TCNT1 count operation is stopped 1 TCNT1 performs count operat...

Page 714: ... as 0 The write value should always be 0 2 STR5 0 R W Counter Start 5 Specifies whether TCNT5 is operated or stopped 0 TCNT5 count operation is stopped 1 TCNT5 performs count operation 1 STR4 0 R W Counter Start 4 Specifies whether TCNT4 is operated or stopped 0 TCNT4 count operation is stopped 1 TCNT4 performs count operation 0 STR3 0 R W Counter Start 3 Specifies whether TCNT3 is operated or sto...

Page 715: ...e R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 BIt Initial value R W 18 3 4 Timer Counter TCNTn n 0 to 5 The TCNT registers are 32 bit readable writable registers Each TCNT counts down on the input clock selected by the TPSC2 to TPSC0 bits in TCR When a TCNT counter underflows while counting down the UNF flag is set in TCR of the corresponding channel At the same time the TCOR value is set in TCNT an...

Page 716: ...al value R W TCR2 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TPSC0 TPSC1 TPSC2 CKEG0 CKEG1 UNIE ICPE0 ICPE1 UNF ICPF R W R W R W R W R W R W R W R W R W R W R R R R R R BIt Initial value R W Bit Bit Name Initial Value R W Description 15 to 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 ICPF 1 0 R W Input Capture Interrupt Flag St...

Page 717: ...ng prohibited 10 Input capture function is used but interrupt due to input capture TICPI2 is not enabled Data transfer request is sent to the DMAC in the event of input capture 11 Input capture function is used and interrupt due to input capture TICPI2 is enabled 5 UNIE 0 R W Underflow Interrupt Control Controls enabling or disabling of interrupt generation when the UNF status flag is set to 1 ind...

Page 718: ...1 initial value is 0 and can only be read 2 Writing 1 does not change the value the previous value is retained 3 Do not set in channels 3 4 and 5 18 3 6 Input Capture Register 2 TCPR2 TCPR2 is a 32 bit read only register for use with the input capture function provided only in channel 2 The input capture function is controlled by means of the ICPE and CKEG bits in TCR2 When input capture occurs th...

Page 719: ...nting Channel 2 also has an input capture function 18 4 1 Counter Operation When one of bits STR0 to STR2 in TSTR is set to 1 the TCNT for the corresponding channel starts counting When TCNT underflows the UNF flag in TCR is set If the UNIE bit in TCR is set to 1 at this time an interrupt request is sent to the CPU At the same time the value is copied from TCOR into TCNT and the count down continu...

Page 720: ...t enabled state is set without clearing the flag another interrupt will be generated Select the count clock with the TPSC2 to TPSC0 bits in TCR When the external clock TCLK is selected specify the external clock edge with the CKEG1 and CKEG0 bits in TCR Specify whether an interrupt is to be generated on TCNT underflow with the UNIE bit in TCR When the input capture function is used set the ICPE bi...

Page 721: ...n TCNT on underflow Time Figure 18 3 TCNT Auto Reload Operation 3 TCNT Count Timing Operating on internal clock Any of five count clocks Pck 4 Pck 16 Pck 64 Pck 256 or Pck 1024 scaled from the peripheral clock can be selected as the count clock by means of the TPSC2 to TPSC0 bits in TCR Figure 18 4 shows the timing in this case Internal clock Pck TCNT N 1 N N 1 Figure 18 4 Count Timing when Operat...

Page 722: ...selected with the CKEG1 and CKEG0 bits in TCR Figure 18 5 shows the timing for both edge detection External clock input pin Pck TCNT N 1 N N 1 Figure 18 5 Count Timing when Operating on External Clock Operating on on chip RTC output clock The on chip RTC output clock can be selected as the timer clock by means of the TPSC2 to TPSC0 bits in TCR Figure 18 6 shows the timing for both edge detection R...

Page 723: ...this function is used 3 Use bits CKEG1 and CKEG0 in TCR to specify whether the rising or falling edge of the TCLK pin is to be used to set the TCNT value in TCPR2 When input capture occurs the TCNT2 value is set in TCPR2 only when the ICPF bit in TCR2 is 0 A new DMAC transfer request is not generated until processing of the previous request is finished Figure 18 7 shows the operation timing when t...

Page 724: ... and the interrupt enable bit UNIE for that channel are set to 1 When the input capture function is used and an input capture request is generated an interrupt is requested if the ICPF bit in TCR2 is 1 and the input capture control bits ICPE1 and ICPE0 in TCR2 are both set to 11 The TMU interrupt sources are summarized in table 18 4 Table 18 4 TMU Interrupt Sources Channel Interrupt Source Descrip...

Page 725: ...not to change the values of bits other than those being cleared 18 6 2 Reading from TCNT Reading from TCNT is performed synchronously with the timer count operation Note that when the timer count operation is performed simultaneously with reading from a register the synchronous processing causes the TCNT value before the count down operation to be read as the TCNT value 18 6 3 Reset RTC Frequency ...

Page 726: ...Section 18 Timer Unit TMU Rev 1 00 Dec 13 2005 Page 676 of 1286 REJ09B0158 0100 ...

Page 727: ...r channels 16 bit timer counter mode that operates as four channels timer or counter individually 19 1 Features 32 bit free running timer mode Four channels free running timer Two channels of output compare or input capture channel 0 and 1 16 bit timer counter mode Four channels 16 bit timer Two channels of output compare or input capture channel 0 and 1 Up counter channel 0 and 1 Updown counter o...

Page 728: ...T Control register Channeln timer counter n 3 to 0 Channeln stop time register n 1 0 Channeln time register n 3 to 0 CMTCFG CMTCTL CMTFRT CMTIRQS CMTCHn CMTCHn CMTI Bus interface CMTCHn CMTCHn Legend CMTCHn Channel 0 1 Mode controller Clock controller Clock controller Clock controller Pin controller Interrupt detection Interrupt detection Interrupt controller Channel 2 3 32 bit timer Prescaler Per...

Page 729: ...ock Configuration register CMTCFG R W H FFE3 0000 H 1FE3 0000 32 Pck Free running timer CMTFRT R H FFE3 0004 H 1FE3 0004 32 Pck Control register CMTCTL R W H FFE3 0008 H 1FE3 0008 32 Pck Common Interrupt status register CMTIRQS R W H FFE3 000C H 1FE3 000C 32 Pck Channel 0 time register CMTCH0T R W H FFE3 0010 H 1FE3 0010 32 Pck Channel 0 stop time register CMTCH0ST R W H FFE3 0020 H 1FE3 0020 32 P...

Page 730: ...ined Retained Channel 0 time register CMTCH0T H 0000 0000 H 0000 0000 Retained Retained Channel 0 stop time register CMTCH0ST H 0000 0000 H 0000 0000 Retained Retained 0 Channel 0 timer counter CMTCH0C H 0000 0000 H 0000 0000 Retained Retained Channel 1 time register CMTCH1T H 0000 0000 H 0000 0000 Retained Retained Channel 1 stop time register CMTCH1ST H 0000 0000 H 0000 0000 Retained Retained 1 ...

Page 731: ...t Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T01 FRTM ED0 ED1 R W R W R R R R W R R R W R W R W R W R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 17 All 0 R Reserved These bits are always read as 0 The write value should always be 0 16 ROT0 0 R W Channel 0 1 Rotation Enable Updown counter mode T01 11 0 Counting up by CMT...

Page 732: ...0 Setting prohibited 01 High level is output from CMT_CTR1 pin during active period 10 Low level is output from CMT_CTR1 pin during active period 11 Setting prohibited 9 8 ED0 All 0 R W Channel 0 Pin Active Control Input capture mode 00 Setting prohibited 01 Edge detection on rising edge of CMT_CTR0 pin input 10 Edge detection on falling edge of CMT_CTR0 pin input 11 Edge detection on either edge ...

Page 733: ...ters 0 16 bit timer counter mode channel 0 1 16 bit timer mode channel 2 3 1 32 bit free running timer FRT mode When setting to 1 clear the T01 bit to 00 4 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 0 T01 All 0 R W Timer 0 1 Configuration Specifies the channel 0 and channel 1 operation mode Clear to 00 in 32 bit free running timer mode FRTM 1 00 Time...

Page 734: ... 0 0 0 0 0 0 0 0 0 0 0 Bit Bit Name Initial Value R W Description 31 to 0 FRT All 0 R Free Running Timer These bits indicate the current value of the free running timer FRT 19 3 3 Control Register CMTCTL CMTCTL is a 32 bit readable writable register that controls interrupts makes settings for the clocks and selects the operating mode 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 0 0 0 0 0 0 0 0 ...

Page 735: ...n interrupt to be generated when the relevant IOn bit is set in CMTIRQS register 0 Interrupt generation disabled 1 Interrupt generation enabled n 3 to 0 23 22 21 20 ICE3 ICE2 ICE1 ICE0 0 0 0 0 R W R W R W R W Channel 3 to 0 Interrupt Compare Enable These bits enable an interrupt to be generated when the relevant ICn bit is set in the CMTIRQS register 0 Interrupt generation disabled 1 Interrupt gen...

Page 736: ... 00 Clock for timer 2 is 1 32 of peripheral clock Pck 01 Clock for timer 2 is 1 128 of peripheral clock Pck 10 Clock for timer 2 is 1 512 of peripheral clock Pck 11 Clock for timer 2 is 1 1024 of peripheral clock Pck The clock which divided from the peripheral clock Pck is the timer counter resolution 11 10 CC1 All 0 R W Timer Clock Control Channel 1 These bits specify the clock input for the 16 b...

Page 737: ... R W Channel 1 to 0 Stop Ignore For the channel n these bits determine whether in output compare mode with 32 bit free running timer mode the output remains active for half the maximum time or until the stop value is reached 0 Output remains active until the channel n stop time value is reached 1 Output remains active for half the total time of the FRT n 0 1 3 2 1 0 OP3 OP2 OP1 OP0 0 0 0 0 R W R W...

Page 738: ... 11 10 9 8 IO3 IO2 IO1 IO0 0 0 0 0 R W R W R W R W Channel 3 to 0 Interrupt Overflow A bit for each channel indicates if the up counters or updown counters have wrapped i e overflowed from H FFFF to H 0000 or underflowed from H 0000 to H FFFF 0 The counter is not overflowed or underflowed 1 The counter is overflowed or underflowed 7 6 5 4 IC3 IC2 IC1 IC0 0 0 0 0 R W R W R W R W Channel 3 to 0 Inte...

Page 739: ...R W R W R W R W R W R W Note n 3 to 0 R W Channel n time 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 Bit Initial value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19 3 6 Channels 0 to 1 Stop Time Registers CMTCH0ST to CMTCH1ST In output compare mode these registers specify the value to be compared with the free running timer When clearing the STCn bit in CMTCTL the output state that ...

Page 740: ...o this register it can be set the timer counter When reading this register the timer counter value is not affected 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 R R R R R R R R R R R R R R R R Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 Channel n counter 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W...

Page 741: ...channel 19 4 1 Edge Detection The timers and counters are based on edge detection on the input pins An active edge can be selectable by setting CMTCFG to be a rising edge falling edge or both edges In addition the edge detection logic can operate in rotary switch operation where the combination of two inputs indicates whether the switch has been turned right or left and the updown counter is incre...

Page 742: ...Then the IEn flag in CMTIRQS is set to 1 and the interrupt is generated when the IEEn bit in CMTCTL is set to 1 CMT_CTRn CMTI Peripheral bus Common between channels Edge detection Edge control Channel time register 32 bit free running timer Clock generation Multiplexer Figure 19 3 32 Bit Timer Mode Input Capture channel 1 and channel 0 Pck FRT operation clock CMTFRT CMT_CTRn input CMTCHnT IEn flag...

Page 743: ...l channels 19 4 3 32 Bit Timer Output Compare When the value of the CMTFRT matches value of CMTCHnT plus 1 while the timer CMTFRT is operating the CMT_CTR output state becomes equal to the setting of the ED1 and ED0 bits in CMTCFG Then the ICn flag in CMTIRQS is set to 1 and the interrupt is generated when the ICEn bit in CMTCTLis set to 1 The CMT_CTR output is being asserted until the value of CM...

Page 744: ...Rn output ICn flag STCn bit Output remains active until the channel n stop time value is reached Output remains active for half the total time of the FRT Figure 19 5 CMT_CTRn Assert Timing channel 0 and 1 CMT_CTRn 32 bit FRT Channel time CMTI Common between channels 32 bit free running timer Clock generation Channel time register Figure 19 6 32 Bit Timer Mode Output Compare channel 1 and channel 0...

Page 745: ...T ICn flag N N 1 N 1 N 2 N Figure 19 7 32 bit Timer Mode Output Compare Operation Timing Example of High output in Active and Not Active by CMTCHnST Pck CMTFRT CMTCHnT N FRT operation clock CMT_CTRn output N H 8000 0000 N H 8000 0001 Figure 19 8 32 bit Timer Mode Output Compare Operation Timing Example of High output in Active and Not Active by CMTFRT ...

Page 746: ... o 12 All 0 11 to 8 Arbitrary value pin setting of each channel 7 6 All 0 5 1 32 bit free running timer 4 to 0 All 0 CMTCTL 31 to 24 All 0 23 to 20 Arbitrary value compare interrupt setting of each channel 19 t o 10 All 0 9 8 Arbitrary value clock setting of FRT 7 6 All 0 5 4 Arbitrary value active state setting of each channel 3 to 0 All 1 out put compare mode setting of all channels ...

Page 747: ...n bit in CMTCTL is set to 1 Each channel timer overflowed after the timer is counting up at H FFFF that is the value of CMTCHnC n 1 0 Then the IOn flag in CMTIRQS is set to 1 and the interrupt is generated when the IOEn bit in CMTCTL is set to 1 The 16 bit timer CMTCHnC n 1 0 is initialized to H 0000 when the TEn n 1 0 bit in CMTCL is cleared to 0 or an input capture occurs CMT_CTRn CMTI Common be...

Page 748: ...31 t o 12 All 0 11 to 8 Arbitrary value pin setting of each channel 7 6 All 0 5 0 16 bit timer counter 4 to 0 All 0 16 bit timer mode setting of all channels CMTCTL 31 30 All 0 29 28 All 1 counter enable of all channels 27 26 All 0 25 24 Arbitrary value overflow interrupt setting of each channel 23 to 18 All 0 17 16 Arbitrary value edge interrupt setting of each channel 15 t o 10 Same clock settin...

Page 749: ...hannel timer overflowed after the timer is counting up at H FFFF that is the value of CMTCHnC n 3 to 0 Then the IOn flag in CMTIRQS is set to 1 and the interrupt is generated when the IOEn bit in CMTCTL is set to 1 The 16 bit timer CMTCHnC n 3 to 0 is initialized to H 0000 when the TEn n 1 0 bit in CMTCL is cleared to 0 or a compare match occurs Note that channels 2 and 3 do not have the output pi...

Page 750: ...mpare Setting Register Bit Settings CMTCFG 31 t o 16 All 0 15 to 8 All 0 7 6 All 0 5 0 16 bit timer counter 4 to 0 All 0 16 bit timer mode setting of all channels CMTCTL 31 to 28 All 1 counter enable of all channels 27 to 24 Arbitrary value overflow interrupt setting of each channel 23 to 20 Arbitrary value compare interrupt setting of each channel 19 to 16 All 0 15 to 8 Arbitrary value clock sett...

Page 751: ...CMTIRQS is set to 1 and the interrupt is generated when the IEEn bit in CMTCTL is set to 1 And each channel counter overflowed the IOn flag in CMTIRQS is set to 1 and the interrupt is generated when the IOEn bit in CMTCTL is set to 1 The counter CMTCHnC n 1 0 is initialized to H 0000 when the TEn n 1 0 bit in CMTCL is cleared to 0 or an input capture occurs CMTI CMT_CTRn Edge detection Up counter ...

Page 752: ...ting of each channel 7 6 All 0 5 0 16 bit timer counter 4 to 2 All 0 1 0 10 Up counter mode setting of all channels CMTCTL 31 30 All 0 29 28 All 1 counter enable of all channels 27 26 All 0 25 24 Arbitrary value overflow interrupt setting of each channel 23 t o 18 All 0 17 16 Arbitrary value edge interrupt setting of each channel 15 to 12 All 0 11 to 8 Arbitrary value clock setting of each channel...

Page 753: ...t in CMTCTL is set to 1 If both the count up pin CMT_CTR0 and count down pin CMT_CTR1 detect rising edge or falling edge the counter value is not updated but the IEn bit in CMTIRQS is set to 1 And the counter CMTCH0C overflowed or underflowed the IO0 flag in CMTIRQS is set to 1 and the interrupt is generated when the IOE0 bit in CMTCTL is set to 1 The counter CMTCH0C is initialized to H 0000 when ...

Page 754: ...ue pin setting of each channel 7 6 All 0 5 0 16 bit timer counter 4 to 2 All 0 1 0 11 Updown counter mode setting of channel 0 CMTCTL 31 to 29 All 0 28 1 counter enable of channel 0 27 to 25 All 0 24 Arbitrary value overflow interrupt setting of channel 0 23 t o 18 All 0 17 16 Arbitrary value edge interrupt setting of each channel 15 to 10 All 0 9 8 Arbitrary value clock setting of channel 0 7 to ...

Page 755: ...TIRQS is set to 1 or the timer is counted down the IE1 flag in CMTIRQS is set to 1 and the interrupt is generated when the IEEn bit in CMTCTL is set to 1 If both the count up and count down are detected both the IE0 and the IE1 flags are set to 1 and the counter CMTCH0C is updated by the most recently detected edge Pck CMTCH0C N CMTCH0T operation clock CMT_CTR1 input CMT_CTR0 input Channel 0 Edge ...

Page 756: ...e interrupt setting of each channel 15 to 10 All 0 9 8 Arbitrary value clock setting of channel 0 7 to 0 All 0 19 4 9 Interrupts The CMT has three interrupt sources the overflow compare and edge However only one interrupt request is assigned for the CMT it cannot be identified by the request Table 19 11 CMT Interrupt Setting Interrupt source Operation Mode Overflow Compare Edge 32 bit timer Input ...

Page 757: ...inary display The 64 Hz counter register indicates a state of 64 Hz to 1 Hz within the RTC frequency divider Start stop function 30 second adjustment function Alarm interrupts Comparison with second minute hour day of week day month or year can be selected as the alarm interrupt condition Periodic interrupts An interrupt period of 1 256 second 1 64 second 1 16 second 1 4 second 1 2 second 1 second...

Page 758: ...64CNT 16 384 kHz 32 768 kHz 128 Hz AT EXTAL2 XTAL2 I PRI CUI RCR1 RCR2 RCR3 RYRCNT RYRAR RMONCNT RWKCNT RDAYCNT RHRCNT RMINCNT RSECCNT RSECAR RMINAR RHRAR RDAYAR RWKAR RMONAR Prescaler RTC crystal oscillator RTC operation control unit Counter unit Interrupt control unit To registers Bus interface peripheral bus RTCCLK Figure 20 1 Block Diagram of RTC ...

Page 759: ... RTC oscillator crystal pin Output Connects crystal to RTC oscillator TCLK 1 TMU clock input RTC clock output I O TMU external clock input pin input capture control input pin RTC output pin shared with TMU VDD RTC Dedicated RTC power supply RTC oscillator power supply pin 2 VSS RTC Dedicated RTC GND pin RTC oscillator GND pin 2 Notes 1 This pin is multiplexed with the LBSC and GPIO pins 2 Power mu...

Page 760: ...E80010 8 Pck Day counter RDAYCNT R W H FFE80014 H 1FE80014 8 Pck Month counter RMONCNT R W H FFE80018 H 1FE80018 8 Pck Year counter RYRCNT R W H FFE8001C H 1FE8001C 16 Pck Second alarm register RSECAR R W H FFE80020 H 1FE80020 8 Pck Minute alarm register RMINAR R W H FFE80024 H 1FE80024 8 Pck Hour alarm register RHRAR R W H FFE80028 H 1FE80028 8 Pck Day of week alarm register RWKAR R W H FFE8002C ...

Page 761: ...ndefined 1 Initialized 1 Retained Retained Minute alarm register RMINAR Undefined 1 Initialized 1 Retained Retained Hour alarm register RHRAR Undefined 1 Initialized 1 Retained Retained Day of week alarm register RWKAR Undefined 1 Initialized 1 Retained Retained Day alarm register RDAYAR Undefined 1 Initialized 1 Retained Retained Month alarm register RMONAR Undefined 1 Initialized 1 Retained Reta...

Page 762: ...is not initialized by a power on or manual reset Bit 7 is always read as 0 and cannot be modified 0 1 2 3 4 5 6 7 0 64 Hz 32 Hz 16 Hz 8 Hz 4 Hz 2 Hz 1 Hz R R R R R R R R BIt Initial value R W 20 3 2 Second Counter RSECCNT RSECCNT is an 8 bit readable writable register used as a counter for setting and counting the BCD coded second value in the RTC It counts on the carry transition of the R64CNT 1H...

Page 763: ...alid but the write value should always be 0 0 1 2 3 4 5 6 7 0 1 minute units 10 minute units R W R W R W R W R W R W R W R BIt Initial value R W 20 3 4 Hour Counter RHRCNT RHRCNT is an 8 bit readable writable register used as a counter for setting and counting the BCD coded hour value in the RTC It counts on the carry generated once per hour by the minute counter The setting range is decimal 00 to...

Page 764: ...tting range is decimal 0 to 6 The RTC will not operate normally if any other value is set Write processing should be performed after stopping the count with the START bit in RCR2 or by using the carry flag RWKCNT is not initialized by a power on or manual reset Bits 7 to 3 are always read as 0 A write to these bits is invalid but the write value should always be 0 0 1 2 3 4 5 6 7 0 0 0 0 0 Day of ...

Page 765: ...performed after stopping the count with the START bit in RCR2 or by using the carry flag RDAYCNT is not initialized by a power on or manual reset The setting range for RDAYCNT depends on the month and whether the year is a leap year so care is required when making the setting Taking the year counter RYRCNT value as the year leap year calculation is performed according to whether or not the value i...

Page 766: ... bits is invalid but the write value should always be 0 0 1 2 3 4 5 6 7 0 10 month unit 0 0 1 month units R W R W R W R W R W R R R BIt Initial value R W 20 3 8 Year Counter RYRCNT RYRCNT is a 16 bit readable writable register used as a counter for setting and counting the BCD coded year value in the RTC It counts on the carry generated once per year by the month counter The setting range is decim...

Page 767: ...ialized by a power on or manual reset 0 1 2 3 4 5 6 7 0 1 second units 10 second units ENB R W R W R W R W R W R W R W R W BIt Initial value R W 20 3 10 Minute Alarm Register RMINAR RMINAR is an 8 bit readable writable register used as an alarm register for the RTC s BCD coded minute value counter RMINCNT When the ENB bit is set to 1 the RMINAR value is compared with the RMINCNT value Comparison b...

Page 768: ...ialized by a power on or manual reset Bit 6 is always read as 0 A write to this bit is invalid but the write value should always be 0 0 1 2 3 4 5 6 7 0 0 1 hour units 10 hour units ENB R W R W R W R W R W R W R R W BIt Initial value R W 20 3 12 Day of Week Alarm Register RWKAR RWKAR is an 8 bit readable writable register used as an alarm register for the RTC s BCD coded day of week value counter R...

Page 769: ...ison between the counter and the alarm register is performed for those registers among RSECAR RMINAR RHRAR RWKAR RDAYAR and RMONAR in which the ENB bit is set to 1 and the RCR1 alarm flag is set when the respective values all match The setting range is decimal 01 to 31 ENB bit The RTC will not operate normally if any other value is set The setting range for RDAYAR depends on the month and whether ...

Page 770: ...er on or manual reset Bits 6 and 5 are always read as 0 A write to these bits is invalid but the write value should always be 0 0 1 2 3 4 5 6 7 0 10 month unit 0 0 1 month units ENB R W R W R W R W R W R R R W BIt Initial value R W 20 3 15 Year Alarm Register RYRAR RYRAR is the alarm register for the RTC s BCD coded year value counter RYRCNT When the YENB bit of RCR3 is set to 1 the RYRCNT value i...

Page 771: ...Undefined R W Carry Flag This flag is set to 1 on generation of a second counter carry or a 64 Hz counter carry when the 64 Hz counter is read The count register value read at this time is not guaranteed and so the count register must be read again 0 No second counter carry or 64 Hz counter carry when 64 Hz counter is read Clearing condition When 0 is written to CF 1 Second counter carry or 64 Hz ...

Page 772: ...AF flag is set to 1 1 Alarm interrupt is generated when AF flag is set to 1 2 Undefined R Reserved The initial value of these bits is undefined A write to these bits is invalid but the write value should always be 0 1 CRF Undefined R Carry Ready Flag Indicates whether or not RSECCNT second counter is in the state of the carry ready period This flag is set to 1 when the second counter value is to b...

Page 773: ...larm registers in which the ENB bit is set to 1 and counter values match Note Writing 1 does not change the value 20 3 17 RTC Control Register 2 RCR2 RCR2 is an 8 bit readable writable register used for periodic interrupt control 30 second adjustment and frequency divider RESET and RTC count control RCR2 is basically initialized to H 09 by a power on reset except that the value of the PEF bit is u...

Page 774: ...fied by bits PES2 PES0 When 1 is written to PEF 6 to 4 PES 2 0 All 0 R W Periodic Interrupt Enable These bits specify the period for periodic interrupts 000 No periodic interrupt generation 001 Periodic interrupt generated at 1 256 second intervals 010 Periodic interrupt generated at 1 64 second intervals 011 Periodic interrupt generated at 1 16 second intervals 100 Periodic interrupt generated at...

Page 775: ...1 30 second adjustment performed 1 RESET 0 R W Reset The frequency divider circuits are initialized by writing 1 to this bit When 1 is written to the RESET bit the frequency divider circuits RTC prescaler and R64CNT are reset and the RESET bit is automatically cleared to 0 i e does not need to be written with 0 0 Normal clock operation 1 Frequency divider circuits are reset 0 START 1 R W Start Bit...

Page 776: ...unction of RYRCNT that is the RTC s BCD coded year value counter When the YENB bit of RCR3 is set to 1 the RYRCNT value is compared with the RYRAR value RCR3 is initialized by a power on reset Bits 6 to 0 of RCR3 are always read as 0 A write to these bits is invalid If a value is written to these bits it should always be 0 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 YENB R R R R R R R R W BIt Initial value R W ...

Page 777: ...lear carry flag Write to counter register Carry flag 1 No Yes Figure 20 2 Examples of Time Setting Procedures The procedure for setting the time after stopping the clock is shown in figure 20 2 a The programming for this method is simple and it is useful for setting all the counters from second to year The procedure for setting the time while the clock is running is shown in figure 20 2 b This met...

Page 778: ...s read out from the second counter register that should be changed to H 00 and the read out value of the minute counter register should be added to 1 as a carry processing The hour counter day of week day month and year counters may be necessary to do carry processing Read RCR1 register and check CF bit Clear carry flag Read counter register Disable carry interrupts Clear carry flag Enable carry i...

Page 779: ...alarm interrupts Set alarm time Clear alarm flag Enable alarm interrupts Clear RCR1 AIE to prevent erroneous interrupts Be sure to reset the flag as it may have been set during alarm time setting Set RCR1 AIE to 1 Figure 20 4 Example of Use of Alarm Function An alarm can be generated by the second minute hour day of week day month or year value or a combination of these Write 1 to the ENB bit in t...

Page 780: ...and the periodic interrupt flag PEF is set to 1 A carry interrupt request CUI is generated when the carry flag CF in RCR1 is set to 1 while the carry interrupt enable bit CIE is also set to 1 20 6 Usage Notes 20 6 1 Register Initialization After powering on and making the RCR1 register settings reset the frequency divider by setting RCR2 RESET to 1 and make initial settings for all the other regis...

Page 781: ...l oscillation stabilization time depends on the mounted circuit constants floating capacitance etc and should be decided after consultation with the crystal resonator manufacturer 5 Place the crystal resonator and load capacitors Cin and Cout as close as possible to the chip Correct oscillation may not be possible if there is externally induced noise in the EXTAL2 and XTAL2 pins 6 Ensure that the ...

Page 782: ...n in figure 20 6 Pck 50MHz EXTAL2 32 768kHz TCLK 16 384kHz RSECCNT 7 0 second counter register R64CNT 7 0 64Hz counter register RCR2 PEF periodical interrupt flag interrupt request signal RCR1 CF carry flag interrupt request signal RCR1 AF alarm flag interrupt request signal n 1 H 7F n carry periodical and alarm interrupt EXTAL2 4 clock cycles carry ready period H 00 Pck 2 clock cycles Pck 4 to 6 ...

Page 783: ... character Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver Transmitter UART or Asynchronous Communication Interface Adapter ACIA There is a choice of 8 serial data transfer formats Data length 7 or 8 bits Stop bit length 1 or 2 bits Parity Even odd none Receive error detection Parity framing and overrun errors Br...

Page 784: ...urces transmit FIFO data empty break receive FIFO data full and receive error that can issue requests independently The DMA controller DMAC can be activated to execute a data transfer by issuing a DMA transfer request in the event of a transmit FIFO data empty or receive FIFO data full interrupt When not in use the SCIF can be stopped by halting its clock supply to reduce power consumption In asyn...

Page 785: ...r Transmit shift register Transmit FIFO data register Serial mode register Serial control register Serial status register SCBRRn SCSPTRn SCFCRn SCTFDRn SCRFDRn SCLSRn SCRERn Bit rate register Serial port register FIFO control register Transmit FIFO data count register Receive FIFO data count register Line status register Serial error register SCRSRn SCTSRn SCSMRn SCLSRn SCTFDRn SCRFDRn SCFCRn SCFS...

Page 786: ... SCSPTR SPTRR Read from SCSPTR Note The SCIF0_RTS pin function is designated as modem control by the MCE bit in SCFCR Modem control enable signal Figure 21 2 SCIF0_RTS Pin Only in Channel 0 Reset Peripheral bus SPTRW D5 D4 R Q D CTSIO C Reset SPTRR SPTRW R Q D CTSDT C SPTRW SCIF0_CTS SCIF_CTS signal Write to SCSPTR SPTRR Read from SCSPTR Note The SCIF0_CTS pin function is designated as modem contr...

Page 787: ...ignal Serial clock output signal Serial clock input signal Serial input enable signal Note The SCIFn_CLK pin function is designated as internal clock output or external clock input by the C A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR SPTRR Figure 21 4 SCIFn_SCK Pin n 0 1 Reset Peripheral bus SPTRW R Q D D1 D0 SPB2IO C Reset SPTRW R Q D SPB2DT C SCIFn_TXD SPTRW Write to SCSPTR Transmit enabl...

Page 788: ... 21 Serial Communication Interface with FIFO SCIF Rev 1 00 Dec 13 2005 Page 738 of 1286 REJ09B0158 0100 Peripheral bus SCIFn_RXD SPTRR Serial receive data SPTRR Read from SCSPTR Figure 21 6 SCIFn_RXD Pin n 0 1 ...

Page 789: ...mission enabled SCIF0_RTS Channel 0 modem control pin I O Transmission request SCIF1_SCK Channel 1 serial clock pin I O Clock input output SCIF1_RXD Channel 1 receive data pin Input Receive data input SCIF1_TXD Channel 1 transmit data pin Output Transmit data output Notes These pins are made to function as serial pins by performing SCIF operation settings with the C A bit in SCSMR the TE RE CKE1 a...

Page 790: ...FE0 0020 16 Pck Serial port register 0 SCSPTR0 R W H FFE0 0024 H 1FE0 0024 16 Pck Line status register 0 SCLSR0 R W 2 H FFE0 0028 H 1FE0 0028 16 Pck Serial error register 0 SCRER0 R H FFE0 002C H 1FE0 002C 16 Pck 1 Serial mode register 1 SCSMR1 R W H FFE1 0000 H 1FE1 0000 16 Pck Bit rate register 1 SCBRR1 R W H FFE1 0004 H 1FE1 0004 8 Pck Serial control register 1 SCSCR1 R W H FFE1 0008 H 1FE1 000...

Page 791: ...H 0000 H 0000 Retained Retained Serial port register 0 SCSPTR0 H 0000 1 H 0000 1 Retained Retained Line status register 0 SCLSR0 H 0000 H 0000 Retained Retained Serial error register 0 SCRER0 H 0000 H 0000 Retained Retained 1 Serial mode register 1 SCSMR1 H 0000 H 0000 Retained Retained Bit rate register 1 SCBRR1 H FF H FF Retained Retained Serial control register 1 SCSCR1 H 0000 H 0000 Retained R...

Page 792: ... SCFRDR automatically SCRSR cannot be directly read from and written to by the CPU 0 1 2 3 4 5 6 7 Bit Initial value R W 21 3 2 Receive FIFO Data Register SCFRDR SCFRDR is an 8 bit FIFO register of 64 stages that stores received serial data When the SCIF has received one byte of serial data it transfers the received data from SCRSR to SCFRDR where it is stored and completes the receive operation S...

Page 793: ...R and transmission started automatically SCTSR cannot be directly read from and written to by the CPU 0 1 2 3 4 5 6 7 Bit Initial value R W 21 3 4 Transmit FIFO Data Register SCFTDR SCFTDR is an 8 bit FIFO register of 64 stages that stores data for serial transmission If SCTSR is empty when transmit data has been written to SCFTDR the SCIF transfers the transmit data written in SCFTDR to SCTSR and...

Page 794: ... R W R W R W R W R W R R R R R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 C A 0 R W Communication Mode Selects asynchronous mode or clocked synchronous mode as the SCIF operating mode 0 Asynchronous mode 1 Clocked synchronous mode 6 CHR 0 R W Character Length Selects 7 or 8 bit...

Page 795: ...0 R W Parity Mode Selects either even or odd parity for use in parity addition and checking In asynchronous mode the O E bit setting is only valid when the PE bit is set to 1 enabling parity bit addition and checking In clocked synchronous mode or when parity addition and checking is disabled in asynchronous mode the O E bit setting is invalid 0 Even parity 1 Odd parity When even parity is set par...

Page 796: ...s the start bit of the next transmit character Note 1 In transmission a single 1 bit stop bit is added to the end of a transmit character before it is sent 2 In transmission two 1 bits stop bits are added to the end of a transmit character before it is sent 2 0 R Reserved This bit is always read as 0 The write value should always be 0 1 0 CKS1 CKS0 0 0 R W R W Clock Select 1 and 0 These bits selec...

Page 797: ...cription 15 to 8 All 0 R Reserved These bits are always read as 0 The write value should always be 0 7 TIE 0 R W Transmit Interrupt Enable Enables or disables transmit FIFO data empty interrupt TXI request generation when serial transmit data is transferred from SCFTDR to SCTSR the number of data bytes in SCFTDR falls to or below the transmit trigger set number and the TDFE flag in SCFSR is set to...

Page 798: ...ed 1 Receive data full interrupt RXI request receive error interrupt ERI request and break interrupt BRI request enabled Note An RXI interrupt request can be cleared by reading 1 from the RDF or DR flag in SCFSR then clearing the flag to 0 or by clearing the RIE bit to 0 ERI and BRI interrupt requests can be cleared by reading 1 from the ER BRK or ORER flag in SCFSR then clearing the flag to 0 or ...

Page 799: ...eption format decided and the receive FIFO reset before the RE bit is set to 1 3 REIE 0 R W Receive Error Interrupt Enable Enables or disables generation of receive error interrupt ERI and break interrupt BRI requests The REIE bit setting is valid only when the RIE bit is 0 Receive error interrupt ERI and break interrupt BRI requests can be cleared by reading 1 from the ER BRK in SCFSR or ORER fla...

Page 800: ...lock is selected as the SCIF clock source CKE1 0 When an external clock is selected CKE1 1 the CKE0 bit setting is invalid The CKE1 and CKE0 bits must be set before determining the SCIF s operating mode with SCSMR Asynchronous mode 00 Internal clock SCIF_SCK pin functions as port by setting SCSPTR register 01 Internal clock SCIF_SCK pin functions as clock output 1 1x External clock SCIF_SCK pin fu...

Page 801: ...itten to flags ER TEND TDFE BRK RDF and DR Also note that in order to clear these flags they must be read as 1 beforehand The FER flag and PER flag are read only flags and cannot be modified 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 DR RDF PER FER BRK TDFE TEND ER R W R W R R R W R W R W R W R R R R R R R R Bit Initial value R W Note Only 0 can be written to clear the f...

Page 802: ...eception Setting conditions When the SCIF checks whether the stop bit at the end of the receive data is 1 when reception ends and the stop bit is 0 When in reception the number of 1 bits in the receive data plus the parity bit does not match the parity setting even or odd specified by the O E bit in SCSMR Note In 2 stop bit mode only the first stop bit is checked for a value of 1 the second stop b...

Page 803: ...n transmit data exceeding the transmit trigger set number is written to SCFTDR after reading TDFE 1 and 0 is written to TDFE When transmit data exceeding the transmit trigger set number is written to SCFTDR by the DMAC 1 The number of transmit data bytes in SCFTDR does not exceed the transmit trigger set number Initial value Setting conditions Power on reset or manual reset When the number of SCFT...

Page 804: ...r at least one frame length Note When a break is detected the receive data H 00 following detection is not transferred to SCFRDR When the break ends and the receive signal returns to mark 1 receive data transfer is resumed 3 FER 0 R Framing Error In asynchronous mode indicates whether or not a framing error has been found in the data that is to be read next from SCFRDR 0 There is no framing error ...

Page 805: ...ty error has been found in the data that is to be read next from SCFRDR 0 There is no parity error that is to be read from SCFRDR Clearing conditions Power on reset or manual reset When there is no parity error in the data that is to be read next from SCFRDR 1 There is a parity error in the receive data that is to be read from SCFRDR Setting condition When there is a parity error in the data that ...

Page 806: ...DR is read until the number of receive data bytes in SCFRDR falls below the receive trigger set number after reading RDF 1 and 0 is written to RDF When SCFRDR is read by the DMAC until the number of receive data bytes in SCFRDR falls below the receive trigger set number 1 The number of receive data bytes in SCFRDR is equal to or greater than the receive trigger set number Setting condition When SC...

Page 807: ...or has ended normally and there is no receive data left in SCFRDR Clearing conditions Power on reset or manual reset When all the receive data in SCFRDR has been read after reading DR 1 and 0 is written to DR When all the receive data in SCFRDR has been read by the DMAC 1 No further receive data has arrived Setting condition When SCFRDR contains fewer than the receive trigger set number of receive...

Page 808: ...e CPU The SCBRR setting is found from the following equation Asynchronous mode N 106 1 Pck 64 22n 1 B Clocked synchronous mode N 106 1 Pck 8 22n 1 B Where B Bit rate bit s N SCBRR setting for baud rate generator 0 N 255 Pck Peripheral module operating frequency MHz n 0 to 3 See table 21 4 for the relation between n and the clock Table 21 4 SCSMR Settings SCSMR Setting n Baud Rate Generator Input C...

Page 809: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LOOP RFCL TFCL MCE Note Reserved bit in channel 1 TTRG0 TTRG1 RTRG0 RTRG1 RST RG2 RST RG1 RST RG0 R W R W R W R W R W R W R W R W R W R W R W R R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 15 to 11 All 0 R Reserved These bits are always read as 0 The write value should always be 0 10 9 8 RSTRG2 RSTRG1 RSTRG0 0 0 0 R W R W R W SCIF0_RTS O...

Page 810: ...O Data Number Trigger These bits are used to set the number of remaining transmit data bytes that sets the TDFE flag in SCFSR The TDFE flag is set when the number of transmit data bytes in SCFTDR is equal to or less than the trigger set number shown below 00 32 32 01 16 48 10 2 62 11 0 64 Note Figures in parentheses are the number of empty bytes in SCFTDR when the flag is set 3 MCE 0 R W Modem Con...

Page 811: ...of a power on reset or manual reset 1 RFCL 0 R W Receive FIFO Data Count Register Clear Clears the transmit FIFO data count register to 0 0 Clear operation disabled 1 Clear operation enabled Note A reset operation is performed in the event of a power on reset or manual reset 0 LOOP 0 R W Loopback Test Internally connects the transmit output pin SCIF_TXD and receive input pin SCIF_RXD and the SCIF0...

Page 812: ...U 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 T0 T1 T2 T3 T4 T5 T6 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 15 to 7 All 0 R Reserved These bits are always read as 0 The write value should always be 0 6 to 0 T6 to T0 All 0 R These bits show the number of untransmitted data bytes in SCFTDR A value of H 00 indicates tha...

Page 813: ... CPU 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R0 R1 R2 R3 R4 R5 R6 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 15 to 7 All 0 R Reserved These bits are always read as 0 The write value should always be 0 6 to 0 R6 to R0 All 0 R These bits show the number of receive data bytes in SCFRDR A value of H 00 indicates that t...

Page 814: ...n the module standby state Note that when reading data via a serial port pin in the SCIF the peripheral clock value from 2 cycles before is read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 SPB2 DT SPB2 IO SCK DT SCK IO CTS DT CTS IO RTS DT RTS IO R W R W R W R W R W R W R W R W R R R R R R R R Bit Initial value R W Note Reserved bit in channel 1 Bit Bit Name Initial Value R W Des...

Page 815: ... output the value set by the CTSDT bit the MCE bit in SCFCR should be cleared to 0 0 CTSDT bit value is not output to SCIF0_CTS pin 1 CTSDT bit value is output to SCIF0_CTS pin 4 CTSDT R W Serial Port SCIF0_CTS Port Data Specifies the serial port SCIF0_CTS pin input output data Input or output is specified by the CTSIO bit In output mode the CTSDT bit value is output to the SCIF0_CTS pin The SCIF0...

Page 816: ...serial port SCIF_TXD pin output condition When actually setting the SCIF_TXD pin as a port output pin to output the value set by the SPB2DT bit the TE bit in SCSCR should be cleared to 0 0 SPB2DT bit value is not output to the SCIF_TXD pin 1 SPB2DT bit value is output to the SCIF_TXD pin 0 SPB2DT R W Serial Port Break Data Specifies the serial port SCIF_RXD pin input data and SCIF_TXD pin output d...

Page 817: ... overrun error occurred during reception causing abnormal termination 0 Reception in progress or reception has ended normally Clearing conditions Power on reset or manual reset When 0 is written to ORER after reading ORER 1 The ORER flag is not affected and retains its previous state when the RE bit in SCSCR is cleared to 0 1 An overrun error occurred during reception Setting condition When the ne...

Page 818: ...bits indicate the number of data bytes in which a parity error occurred in the receive data stored in SCFRDR After the ER bit in SCFSR is set the value indicated by bits PER5 to PER0 is the number of data bytes in which a parity error occurred If all 64 bytes of receive data in SCFRDR have parity errors the value indicated by bits PER5 to PER0 will be 0 7 6 All 0 R Reserved These bits are always r...

Page 819: ...bits in SCSCR as shown in table 21 5 Note Since the operations are the same in each channel except for the modem control the channel number n n 0 1 is omitted in the description below Asynchronous Mode Data length Choice of 7 or 8 bits LSB first for data transmission reception Choice of parity addition and addition of 1 or 2 stop bits the combination of these parameters determines the transfer for...

Page 820: ...he baud rate generator clock and a serial clock is output to external devices When external clock SCIF_SCK input clock is selected The on chip baud rate generator is not used and the SCIF operates on the input serial clock Table 21 5 SCSMR Settings for Serial Transfer Format Selection SCSMR Settings SCIF Transfer Format Bit 7 C A Bit 6 CHR Bit 5 PE Bit 3 STOP Mode Data Length Parity Bit Stop Bit L...

Page 821: ... SCSCR Settings Bit 7 C A Bit 1 CKE1 Bit 0 CKE0 Mode Clock Source SCK Pin Function 0 SCIF does not use SCIF_SCK pin 0 1 Internal Outputs clock with frequency of 16 times the bit rate 0 Inputs clock with frequency of 16 0 1 1 Asynchronous mode External times the bit rate 0 Outputs synchronization clock 0 1 Internal 0 Inputs synchronization clock 1 1 1 Clocked synchronous mode External ...

Page 822: ... In asynchronous serial communication the transmission line is usually held in the mark state high level The SCIF monitors the transmission line and when it goes to the space state low level recognizes a start bit and starts serial communication One character in serial communication consists of a start bit low level followed by transmit receive data LSB first from the lowest bit a parity bit high ...

Page 823: ...ording to the SCSMR settings Table 21 7 Serial Transfer Formats Asynchronous Mode SCSMR Settings Serial Transfer Format and Frame Length CHR PE STOP 1 2 3 4 5 6 7 8 9 10 11 12 0 0 0 S 8 bit data STOP 0 0 1 S 8 bit data STOP STOP 0 1 0 S 8 bit data P STOP 0 1 1 S 8 bit data P STOP STOP 1 0 0 S 7 bit data STOP 1 0 1 S 7 bit data STOP STOP 1 1 0 S 7 bit data P STOP 1 1 1 S 7 bit data P STOP STOP Lege...

Page 824: ...eceiving data it is necessary to clear the TE and RE bits in SCSCR to 0 then initialize the SCIF as described below When the operating mode or transfer format etc is changed the TE and RE bits must be cleared to 0 before making the change using the following procedure 1 When the TE bit is cleared to 0 SCTSR is initialized Note that clearing the TE and RE bits to 0 does not change the contents of S...

Page 825: ...to 0 Set TE and RE bits in SCSCR to 1 and set TIE RIE and REIE bits End of initialization Wait No Yes Set the clock selection in SCSCR Be sure to clear bits TIE RIE TE and RE to 0 Set the data transfer format in SCSMR Write a value corresponding to the bit rate into SCBRR Not necessary if an external clock is used Wait at least one bit interval then set the TE bit or RE bit in SCSCR to 1 Also set ...

Page 826: ...ck and transmit data write Read SCFSR and check that the TDFE flag is set to 1 then write transmit data to SCFTDR and clear the TDFE and TEND flags to 0 The number of transmit data bytes that can be written is 64 transmit trigger set number write 2 Serial transmission continuation procedure To continue serial transmission read 1 from the TDFE flag to confirm that writing is possible then write dat...

Page 827: ...in SCSCR is set to 1 at this time a transmit FIFO data empty interrupt TXI request is generated The serial transmit data is sent from the SCIF_TXD pin in the following order a Start bit One 0 bit is output b Transmit data 8 bit or 7 bit data is output in LSB first order c Parity bit One parity bit even or odd parity is output A format in which a parity bit is not output can also be selected d Stop...

Page 828: ...t Figure 21 10 Sample SCIF Transmission Operation Example with 8 Bit Data Parity One Stop Bit 4 When modem control is enabled transmission can be stopped and restarted in accordance with the SCIF0_CTS input value When SCIF0_CTS is set to 1 during transmission the line goes to the mark state after transmission of one frame When SCIF0_CTS is set to 0 the next transmit data is output starting from th...

Page 829: ...RK flags in SCFSR and the ORER flag in SCLSR to identify any error perform the appropriate error handling then clear the DR ER BRK and ORER flags to 0 In the case of a framing error a break can also be detected by reading the value of the SCIF_RXD pin 2 SCIF status check and receive data read Read SCFSR and check that RDF 1 then read the receive data in SCFRDR read 1 from the RDF flag and then cle...

Page 830: ...Yes Yes No Overrun error handling ORER 1 Yes No No No 1 Whether a framing error or parity error has occurred in the receive data that is to be read from SCFRDR can be ascertained from the FER and PER bits in SCFSR 2 When a break signal is received receive data is not transferred to SCFRDR while the BRK flag is set However note that the last data in SCFRDR is H 00 and the break data in which a fram...

Page 831: ...CRSR to SCFRDR c Overrun error check The SCIF checks that the ORER flag is 0 indicating that no overrun error has occurred d Break check The SCIF checks that the BRK flag is 0 indicating that the break state is not set If b c and d checks are passed the receive data is stored in SCFRDR Note Reception continues even when a parity error or framing error occurs 4 If the RIE bit in SCSCR is set to 1 w...

Page 832: ...l is enabled the SCIF0_RTS signal is output when SCFRDR is empty When SCIF0_RTS is 0 reception is possible When SCIF0_RTS is 1 this indicates that SCFRDR contains bytes of data equal to or more than the SCIF0_RTS output active trigger number The SCIF0_RTS output active trigger value is specified by bits 10 to 8 in the FIFO control register SCFCR For details see section 21 3 9 FIFO Control Register...

Page 833: ...hronous communication Don t care Don t care One unit of transfer data character or frame Bit 0 Serial data Synchronization clock Bit 1 Bit 3 Bit 4 Bit 5 LSB MSB Bit 2 Bit 6 Bit 7 Note High except in continuous transfer Figure 21 15 Data Format in Clocked Synchronous Communication In clocked synchronous serial communication data on the communication line is output from one fall of the synchronizati...

Page 834: ...s performed the clock is fixed high When an internal clock is selected in a receive operation only as long as the RE bit in SCSCR is set to 1 clock pulses are output until the number of receive data bytes in the receive FIFO data register reaches the receive trigger number 3 SCIF Initialization Clocked Synchronous Mode Before transmitting and receiving data it is necessary to clear the TE and RE b...

Page 835: ...tion almost ends Be sure to clear the TIE RIE TE and RE bits to 0 Set the CKE1 and CKE0 bits Set the data transfer format in SCSMR Write a value corresponding to the bit rate into SCBRR This is not necessary if an external clock is used Wait at least one bit interval after this write before moving to the next step Set the external pins to be used Set SCIF_RXD input for reception and SCIF_TXD outpu...

Page 836: ... data write Read SCFSR and check that the TDFE flag is set to 1 then write transmit data to SCFTDR and clear the TDFE flag to 0 The transition of the TDFE flag from 0 to 1 can also be identified by a TXI interrupt 2 Serial transmission continuation procedeure To continue serial transmission read 1 from the TDFE flag to confirm that writing is possible them write data to SCFTDR and then clear the T...

Page 837: ...nsmit data is sent from the SCIF_TXD pin in the LSB first order 3 The SCIF checks the SCFTDR transmit data at the timing for sending the last bit If data is present the data is transferred from SCFTDR to SCTSR and then serial transmission of the next frame is started If there is no transmit data the TEND flag in SCFSR is set to 1 after the last bit is sent and the transmit data pin SCIF_TXD pin re...

Page 838: ... Clear RE bit in SCSCR to 0 End of reception Yes No Yes Yes No No Error handling 1 Receive error handling Read the ORER flag in SCLSR to identify any error perform the appropriate error handling then clear the ORER flag to 0 Transmission reception cannot be resumed while the ORER flag is set to 1 2 SCIF status check and receive data read Read SCFSR and check that RDF 1 then read the receive data i...

Page 839: ...ceived data is stored in SCRSR in LSB to MSB order After receiving the data the SCIF checks whether the receive data can be transferred from SCRSR to SCFRDR If this check is passed the receive data is stored in SCFRDR If an overrun error is detected in the error check reception cannot continue 3 If the RIE bit in SCSCR is set to 1 when the RDF flag changes to 1 a receive FIFO data full interrupt R...

Page 840: ...onization clock Serial data RDF ORER Data read from SCFRDR and RDF flag cleared to 0 by RXI interrupt handler One frame Bit 7 LSB RXI interrupt request MSB Bit 0 Bit 6 Bit 7 Bit 7 Bit 0 Bit 1 RXI interr upt BRI interrupt request by overrun error Figure 21 20 Sample SCIF Reception Operation in Clocked Synchronous Mode ...

Page 841: ...1 can also be identified by a TXI interrupt 2 Receive error handling Read the ORER flag in SCLSR to identify any error perform the appropriate error handling then clear the ORER flag to 0 Transmission reception cannot be resumed while the ORER flag is set to 1 3 SCIF status check and receive data read Read SCFSR and check that RDF 1 then read the receive data in SCFRDR and clear the RDF flag to 0 ...

Page 842: ... to perform data transfer If the RDF or DR flag in SCFSR is set to 1 when an RXI interrupt is enabled by the RIE bit an RXI interrupt request and a receive FIFO data full request for DMA transfer are generated If the RDF or DR flag is set to 1 when an RXI interrupt is disabled by the RIE bit only a receive FIFO data full request for DMA transfer is generated A receive FIFO data full request can ac...

Page 843: ...ease ERI Interrupt initiated by receive error flag ER Not possible High RXI Interrupt initiated by receive FIFO data full flag RDF or receive data ready flag DR Possible BRI Interrupt initiated by break flag BRK or overrun error flag ORER Not possible TXI Interrupt initiated by transmit FIFO data empty flag TDFE Possible Low Note An RXI interrupt by setting of the DR flag is available only in asyn...

Page 844: ...eading and the RDF Flag The RDF flag in SCFSR is set when the number of receive data bytes in SCFRDR has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in SCFCR After RDF is set receive data equivalent to the trigger number can be read from SCFRDR allowing efficient continuous reception However if the number of data bytes read in SCFRDR is equal to or greate...

Page 845: ...ing low level and then clear the TE bit to 0 halting transmission When the TE bit is cleared to 0 the transmitter is initialized regardless of the current transmission state and 0 is output from the SCIF_TXD pin 5 Receive Data Sampling Timing and Receive Margin in Asynchronous Mode In asynchronous mode the SCIF operates on a base clock with a frequency of 16 times the bit rate In reception the SCI...

Page 846: ...100 46 875 2 However this is a theoretical value A reasonable margin to allow in system designs is 20 to 30 6 When Using DMAC to Update SCFTDR in External Clock Synchronizing When using an external clock as the synchronization clock after SCFTDR is updated by the DMAC an external clock should be input after at least five peripheral clock Pck cycles A malfunction may occur when the transfer clock i...

Page 847: ... bit data 16 bit stereo audio input output MSB first for data transmission Supports a maximum of 48 kHz sampling rate Synchronization by either frame synchronization pulse or left right channel switch Supports CODEC control data interface Connectable to linear audio or A Law or µ Law CODEC chip Supports both master and slave modes Serial clock An external pin input or internal clock Pck can be sel...

Page 848: ...P S S P Pck 1 nMCLK SIOF_MCLK SIOF_SCK SIOF_SYNC SIOF_TXD SIOF_RXD Timing control SIOF interrupt request SIOFI Peripheral bus Bus interface Control registers Transmit FIFO 32 bits 16 stages Receive FIFO 32 bits 16 stages Transmit control data Receive control data Baud rate generator DMA transfer request Figure 22 1 Block Diagram of SIOF ...

Page 849: ... Name Function I O Description SIOF_MCLK Master clock Input Master clock input pin SIOF_SCK Serial clock I O Serial clock pin common to transmission reception SIOF_SYNC Frame synchronous signal I O Frame synchronous signal common to transmission reception SIOF_TXD Transmit data Output Transmit data pin SIOF_RXD Receive data Input Receive data pin Note These pins are multiplexed with HAC SSI and GP...

Page 850: ...DAR R W H FFE2 0004 H 1FE2 0004 16 Pck Receive data assign register SIRDAR R W H FFE2 0006 H 1FE2 0006 16 Pck Control data assign register SICDAR R W H FFE2 0008 H 1FE2 0008 16 Pck Control register SICTR R W H FFE2 000C H 1FE2 000C 16 Pck FIFO control register SIFCTR R W H FFE2 0010 H 1FE2 0010 16 Pck Status register SISTR R W H FFE2 0014 H 1FE2 0014 16 Pck Interrupt enable register SIIER R W H FF...

Page 851: ... data assign register SIRDAR H 0000 H 0000 Retained Retained Control data assign register SICDAR H 0000 H 0000 Retained Retained Control register SICTR H 0000 H 0000 Retained Retained FIFO control register SIFCTR H 1000 H 1000 Retained Retained Status register SISTR H 0000 H 0000 Retained Retained Interrupt enable register SIIER H 0000 H 0000 Retained Retained Transmit data register SITDR H xxxx x...

Page 852: ... table 22 4 00 Slave mode 1 01 Slave mode 2 10 Master mode 1 11 Master mode 2 13 SYNCAT 0 R W SIOF_SYNC Pin Valid Timing Indicates the position of the SIOF_SYNC signal to be output as a synchronization pulse 0 At the start bit data of frame 1 At the last bit data of slot 12 REDG 0 R W Receive Data Sampling Edge 0 The SIOF_RXD signal is sampled at the falling edge of SIOF_SCK 1 The SIOF_RXD signal ...

Page 853: ...W Receive Control Data Interrupt Mode 0 Sets the RCRDY bit in SISTR when the contents of SIRCR change 1 Sets the RCRDY bit in SISTR each time when the SIRCR receives the control data 5 SYNCAC 0 R W SIOF_SYNC Pin Polarity Valid when the SIOF_SYNC signal is output as a synchronous pulse 0 Active high 1 Active low 4 SYNCDL 0 R W Data Pin Bit Delay for SIOF_SYNC Pin Valid when the SIOF_SYNC signal is ...

Page 854: ...he serial clock generation conditions for the master clock SISCR can be specified when the bits TRMD 1 0 in SIMDR are specified as B 10 or B 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 BRDV 2 0 BRPS 4 0 MSSEL MSIMM R W R W R W R R R R R R W R W R W R W R W R R W R W Bit Initial value R W Bit Bit Name Initial Value R W Description 15 MSSEL 1 R W Master Clock Source Sele...

Page 855: ...ways read as 0 The write value should always be 0 2 to 0 BRDV 2 0 000 R W Baud rate generator s Division Ratio Setting Set the frequency division ratio for the output stage of the baud rate generator 000 Prescalar output 1 2 001 Prescalar output 1 4 010 Prescalar output 1 8 011 Prescalar output 1 16 100 Prescalar output 1 32 101 Setting prohibited 110 Setting prohibited 111 Prescalar output 1 1 Se...

Page 856: ...ble This bit is valid in master mode 0 Disables the SIOF_SCK output outputs 0 1 Enables the SIOF_SCK output If this bit is set to 1 the SIOF initializes the baud rate generator and initiates the operation At the same time the SIOF outputs the clock generated by the baud rate generator to the SIOF_SCK pin 14 FSE 0 R W Frame Synchronous Signal Output Enable This bit is valid in master mode 0 Disable...

Page 857: ...ata is stored in the transmit FIFO transmission of data from the SIOF_TXD pin begins This bit is initialized upon a transmit reset 8 RXE 0 R W Receive Enable 0 Disables data reception from SIOF_RXD 1 Enables data reception from SIOF_RXD This bit setting becomes valid at the start of the next frame at the rising edge of the SIOF_SYNC signal When the 1 setting for this bit becomes valid the SIOF beg...

Page 858: ...es valid immediately For details of transmit reset refer to table 22 13 SIOF automatically clears this bit upon the completion of reset Thus this bit is always read as 0 0 RXRST 0 R W Receive Reset 0 Does not reset receive operation 1 Resets receive operation This bit setting becomes valid immediately For details of receive reset refer to table 22 13 SIOF automatically clears this bit upon the com...

Page 859: ... R W Description 31 to 16 SITDL 15 0 Undefined W Left Channel Transmit Data Specify data to be output from the SIOF_TXD pin as left channel data The position of the left channel data in the transmit frame is specified by the TDLA bit in SITDAR These bits are valid only when the TDLE bit in SITDAR is set to 1 15 to 0 SITDR 15 0 Undefined W Right Channel Transmit Data Specify data to be output from ...

Page 860: ...t Initial value R W Bit Bit Name Initial Value R W Description 31 to 16 SIRDL 15 0 Undefined R Left Channel Receive Data Store data received from the SIOF_RXD pin as left channel data The position of the left channel data in the receive frame is specified by the RDLA bit in SIRDAR These bits are valid only when the RDLE bit in SIRDAR is set to 1 15 to 0 SIRDR 15 0 Undefined R Right Channel Receive...

Page 861: ... W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 SITC1 15 0 Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 16 SITC0 15 0 H 0000 R W Control Channel 0 Transmit Data Specify data to be output from the SIOF_TXD pin as control channel 0 transmit data The position of the control channel 0 data in the transmit or receive frame...

Page 862: ... 8 9 10 11 12 13 15 14 SIRC1 15 0 Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 16 SIRC0 15 0 Undefined R W Control Channel 0 Receive Data Store data received from the SIOF_RXD pin as control channel 0 receive data The position of the control channel 0 data in the transmit or receive frame is specified by the CD0A bit in SICDAR These bits are valid only when the CD0E bit i...

Page 863: ...lways be 0 14 TCRDY 0 R Transmit Control Data Ready 0 Indicates that a write to SITCR is disabled 1 Indicates that a write to SITCR is enabled If SITCR is written when this bit is cleared to 0 SITCR is over written and the previous contents of SITCR are not output from the SIOF_TXD pin This bit is valid when the TXE bit in SITCR is set to 1 This bit indicates a state of the SIOF If SITCR is writte...

Page 864: ...ditions for setting this bit are satisfied the SIOF again indicates 1 for this bit This bit is valid when the TXE bit in SICTR is 1 This bit indicates a state if the size of empty space in the transmit FIFO is less than the size specified by the TFWM bit in SIFCTR the SIOF clears this bit If the issue of interrupts by this bit is enabled an SIOF interrupt is issued 11 0 R Reserved This bit is alwa...

Page 865: ...d space in the receive FIFO exceeds the size specified by the RFWM bit in SIFCTR A receive data transfer request is issued when the valid data space in the receive FIFO exceeds the size specified by the RFWM bit in SIFCTR When using receive data transfer through the DMAC this bit is always cleared by one DMAC access After DMAC access when conditions for setting this bit are satisfied the SIOF agai...

Page 866: ...E bit in SICTR is 1 When 1 is written to this bit the contents are cleared If the issue of interrupts by this bit is enabled an SIOF interrupt is issued 4 FSERR 0 R W Frame Synchronization Error 0 Indicates that no frame synchronization error occurs 1 Indicates that a frame synchronization error occurs A frame synchronization error occurs when the next frame synchronization timing appears before t...

Page 867: ... When 1 is written to this bit the contents are cleared Writing 0 to this bit is invalid If the issue of interrupts by this bit is enabled an SIOF interrupt is issued 2 TFUDF 0 R W Transmit FIFO Underflow 0 No transmit FIFO underflow 1 Transmit FIFO underflow A transmit FIFO underflow means that loading for transmission has occurred when the transmit FIFO is empty When a transmit FIFO underflow oc...

Page 868: ...CTR is 1 When 1 is written to this bit the contents are cleared Writing 0 to this bit is invalid If the issue of interrupts by this bit is enabled an SIOF interrupt is issued 0 RFOVF 0 R W Receive FIFO Overflow 0 No receive FIFO overflow 1 Receive FIFO overflow A receive FIFO overflow means that writing has occurred when the receive FIFO is full When a receive FIFO overflow occurs the SIOF indicat...

Page 869: ...le Transmits an interrupt as an interrupt to the CPU DMA transfer request The TDREQE bit can be set as transmit interrupts 0 Used as a CPU interrupt 1 Used as a DMA transfer request to the DMAC 14 TCRDYE 0 R W Transmit Control Data Ready Enable 0 Disables interrupts due to transmit control data ready 1 Enables interrupts due to transmit control data ready 13 TFEMPE 0 R W Transmit FIFO Empty Enable...

Page 870: ... 5 SAERRE 0 R W Slot Assign Error Enable 0 Disables interrupts due to slot assign error 1 Enables interrupts due to slot assign error 4 FSERRE 0 R W Frame Synchronization Error Enable 0 Disables interrupts due to frame synchronization error 1 Enables interrupts due to frame synchronization error 3 TFOVFE 0 R W Transmit FIFO Overflow Enable 0 Disables interrupts due to transmit FIFO overflow 1 Enab...

Page 871: ...stages of the transmit FIFO are empty 001 Setting prohibited 010 Setting prohibited 011 Setting prohibited 100 Issue a transfer request when 12 or more stages of the transmit FIFO are empty 101 Issue a transfer request when 8 or more stages of the transmit FIFO are empty 110 Issue a transfer request when 4 or more stages of the transmit FIFO are empty 111 Issue a transfer request when 1 or more st...

Page 872: ...of the receive FIFO are valid 101 Issue a transfer request when 8 or more stages of the receive FIFO are valid 110 Issue a transfer request when 12 or more stages of the receive FIFO are valid 111 Issue a transfer request when 16 stages of the receive FIFO are valid A transfer request to the receive FIFO is issued by the RDREQE bit in SISTR The receive FIFO is always used as 16 stages of the FIFO ...

Page 873: ...on 14 to 12 All 0 R Reserved These bits are always read as 0 The write value should always be 0 11 to 8 TDLA 3 0 0000 R W Transmit Left Channel Data Assigns 3 to 0 Specify the position of left channel data in a transmit frame as 0000 0 to 1110 14 1111 Setting prohibited Transmit data for the left channel is specified in the SITDL bit in SITDR 7 TDRE 0 R W Transmit Right Channel Data Enable 0 Disab...

Page 874: ...itable register that specifies the position of the receive data in a frame 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDRA 3 0 RDRE RDLA 3 0 RDLE R W R W R W R W R R R R W R W R W R W R W R R R W R Bit Initial value R W Bit Bit Name Initial Value R W Description 15 RDLE 0 R W Receive Left Channel Data Enable 0 Disables left channel data reception 1 Enables left channel d...

Page 875: ...el is stored in the SIRDR bit in SIRDR 22 3 13 Control Data Assign Register SICDAR SICDAR is a 16 bit readable writable register that specifies the position of the control data in a frame SICDAR can be specified only when the FL bits in SIMDR are specified as B 1xxx x don t care 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CD1A 3 0 CD1E CD0A 3 0 CD0E R W R W R W R W R R R ...

Page 876: ...a is stored in the SIRD0 bit in SIRCR 7 CD1E 0 R W Control Channel 1 Data Enable 0 Disables transmission and reception of control channel 1 data 1 Enables transmission and reception of control channel 1 data 6 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 to 0 CD1A 3 0 0000 R W Control Channel 1 Data Assigns 3 to 0 Specify the position of control channe...

Page 877: ...aud rate generator BRG is used to generate the serial clock The division ratio is from 1 1 to 1 1024 Note that when using master clock directly as the serial clock without division by BRG division ratio 1 1 the MSIMM bit in SISCR should be set to 1 Figure 22 2 shows connections for supply of the serial clock SCKE SIOF_SCK SIOF_MCLK Pck Divider Pre scalar Baud rate generator 1 1 to 1 1024 Master cl...

Page 878: ... of 1286 REJ09B0158 0100 Table 22 5 SIOF Serial Clock Frequency Sampling Rate Frame Length 8 kHz 44 1 kHz 48 kHz 32 bits 256 kHz 1 4112 MHz 1 536 MHz 64 bits 512 kHz 2 8224 MHz 3 072 MHz 128 bits 1 024 MHz 5 6448 MHz 6 144 MHz 256 bits 2 048 MHz 11 2896 MHz 12 288 MHz ...

Page 879: ... the frame L R 1 2 frame width pulse indicating the left channel stereo data L in high level and the right channel stereo data R in low level Figure 22 3 shows the SIOF_SYNC synchronization timing SIOF_SCK SIOF_RXD SIOF_TXD SIOF_SYNC SIOF_SCK SIOF_RXD SIOF_TXD SIOF_SYNC a Synchronous pulse b L R 1 frame 1 frame Start bit data 1 bit delay Start bit of left channel data 1 2 frame length Start bit of...

Page 880: ...iming Figure 22 4 SIOF Transmit Receive Timing 22 4 3 Transfer Data Format The SIOF performs the following transfer Transmit receive data Transfer of 8 bit data 16 bit data 16 bit stereo data Control data Transfer of 16 bit data uses the specific register as interface Transfer Mode The SIOF supports the following four transfer modes as listed in table 22 6 The transfer mode can be specified by the...

Page 881: ...l data 0111 8 128 8 bit monaural data 10xx 16 16 16 bit monaural data 1100 16 32 16 bit monaural stereo data 1101 16 64 16 bit monaural stereo data 1110 16 128 16 bit monaural stereo data 1111 16 256 16 bit monaural stereo data Note x Don t care Slot Position The SIOF can specify the position of transmit data receive data and control data in a frame common to transmission and reception by slot num...

Page 882: ... c 8 bit monaural data d 16 bit stereo data left and right same audio output data Figure 22 5 Transmit Receive Data Bit Alignment Note In the figure only the shaded areas are transmitted or received as valid data Therefore access must be made in byte units for 8 bit data and in word units for 16 bit data Data in unshaded areas is not transmitted or received Monaural or stereo can be specified for ...

Page 883: ...same audio mode is not supported in receive data To execute 8 bit monaural transmission or reception use the left channel Control Data Control data is written to or read from by the following registers Transmit control data write SITCR 32 bit access Receive control data read SIRCR 32 bit access Figure 22 6 shows the control data and bit alignment in SITCR and SIRCR 31 24 23 16 15 8 7 0 31 24 23 16...

Page 884: ... slot position Control by secondary FS Control data is valid only when data length is specified as 16 bits Control by Slot Position Master Mode 1 Slave Mode 1 Control data is transferred for all frames transmitted or received by the SIOF by specifying the slot position of control data This method can be used in both SIOF master and slave modes Figure 22 7 shows an example of the control data inter...

Page 885: ...clears 0 To execute control data transmission send transmit data of LSB 1 the SIOF forcibly set to 1 by writing SITCR The CODEC outputs the secondary FS The SIOF transmits or receives stores in SIRCR control data data specified by SITCR synchronously with the secondary FS Figure 22 8 shows an example of the control data interface timing by the secondary FS SIOF_SCK SIOF_RXD SIOF_TXD SIOF_SYNC L ch...

Page 886: ...smit or receive can be specified individually The request conditions for the FIFO transmit and receive are specified by the bits TFWM 2 0 and the bits RFWM 2 0 in SIFCTR respectively Table 22 11 and table 22 12 summarize the conditions specified by SIFCTR Table 22 11 Conditions to Issue Transmit Request TFWM 2 0 Number of Requested Stages Transmit Request Used Areas 000 1 Empty area is 16 stages 1...

Page 887: ... FIFO stages The FIFO transmit or receive request is canceled when the above condition is not satisfied even if the FIFO is not empty or full Number of FIFOs The number of FIFO stages used in transmission and reception is indicated by the following register Transmit FIFO The number of empty FIFO stages is indicated by the bits TFUA 4 0 in SIFCTR Receive FIFO The number of valid data stages is indi...

Page 888: ...NC Transfer ended Clear the TXE bit in SICTR to 0 Set operating mode serial clock slot positions for transmit data slot position for control data control data and FIFO request threshold value Set operation start for baud rate generator Set the start for frame synchronous signal output and enable transmission Set transmit data Set to disable transmission Output serial clock Output frame synchronous...

Page 889: ...CTR to 0 Set operating mode serial clock slot positions for receive data slot position for control data and FIFO request threshold value Set operation start for baud rate generator Output serial clock Flow Chart SIOF Settings SIOF Operation Set the start for frame synchronous signal output and enable reception Issue receive transfer request according to the receive FIFO threshold value Reception E...

Page 890: ... Transmit SITDR from SIOF_TXD synchronously with SIOF_SYNC Transfer ended Clear the TXE bit in SICTR to 0 Set operating mode serial clock slot positions for transmit data slot position for control data control data and FIFO request threshold value Set transmit data Set to disable transmission Issue transmit transfer request to enable transmission when frame synchronous signal is input Transmit End...

Page 891: ...bit in SICTR to 0 Set operating mode serial clock slot positions for receive data slot position for control data and FIFO request threshold value Flow Chart SIOF Settings SIOF Operation Issue receive transfer request according to the receive FIFO threshold value Reception End reception Read receive data Set to disable reception Read SIRDR Store SIOFRXD receive data in SIRDR synchronously with SIOF...

Page 892: ...e reset RXRST bit in SICTR Table 22 13 shows the details of initialization upon transmit or receive reset Table 22 13 Transmit and Receive Reset Type Objects Initialized Transmit reset Stop transmitting form the SIOF_TXD high level is outputted Transmit FIFO write pointer TCRDY TFEMP and TDREQ bits in SISTR TXE bit in SICTR Receive reset Stop receiving form the SIOF_RXD Receive FIFO write pointer ...

Page 893: ...ransmit control register is ready to be written 6 Control RCRDY Receive control data ready The receive control data register stores valid data 7 TFUDF Transmit FIFO underflow Serial data transmit timing has arrived while the transmit FIFO is empty 8 TFOVF Transmit FIFO overflow Write to the transmit FIFO is performed while the transmit FIFO is full 9 RFOVF Receive FIFO overflow Serial data is rece...

Page 894: ...erforms the following operations Transmit FIFO underflow TFUDF The immediately preceding transmit data is again transmitted Transmit FIFO overflow TFOVF The contents of the transmit FIFO are protected and the write operation causing the overflow is ignored Receive FIFO overflow RFOVF Data causing the overflow is discarded and lost Receive FIFO underflow RFUDF An undefined value is output on the bu...

Page 895: ...D0A 3 0 0000 FL 3 0 0000 frame length 8 bits TDRE 0 RDRE 0 CD1E 0 TDRA 3 0 0000 RDRA 3 0 0000 CD1A 3 0 0000 Specifications 1 frame 1 bit delay Figure 22 13 Transmit and Receive Timing 8 Bit Monaural Data 1 8 bit Monaural Data 2 Synchronous pulse method falling edge sampling slot No 0 used for transmit and receive data and frame length 16 bits SIOF_SCK SIOF_RXD SIOF_TXD SIOF_SYNC L channel data TRM...

Page 896: ...0 0000 Slot No 0 Slot No 1 Slot No 2 Slot No 3 Specifications 1 frame 1 bit delay Figure 22 15 Transmit and Receive Timing 16 Bit Monaural Data 16 bit Stereo Data 1 L R method rising edge sampling slot No 0 used for left channel data slot No 1 used for right channel data and frame length 32 bits SIOF_SCK SIOF_RXD SIOF_TXD SIOF_SYNC L channel data TRMD 1 0 11 TDLE 1 RDLE 1 CD0E 0 REDG 1 TDLA 3 0 00...

Page 897: ... 1 Slot No 2 Slot No 3 Specifications 1 frame No bit delay Figure 22 17 Transmit and Receive Timing 16 Bit Stereo Data 2 16 bit Stereo Data 3 Synchronous pulse method falling edge sampling slot No 0 used for left channel data slot No 1 used for right channel data slot No 2 used for control data for channel 0 slot No 3 used for control data for channel 1 and frame length 128 bits SIOF_SCK SIOF_RXD ...

Page 898: ...ications 1 frame 1 bit delay R channel data Figure 22 19 Transmit and Receive Timing 16 Bit Stereo Data 4 Synchronization Pulse Output Mode at End of Each Slot SYNCAT Bit 1 Synchronous pulse method falling edge sampling slot No 0 used for left channel data slot No 1 used for right channel data slot No 2 used for control data for channel 0 slot No 3 used for control data for channel 1 and frame len...

Page 899: ...uplex communication A flexible peripheral clock division strategy allows a wide range of bit rates to be supported The programmable clock control logic allows setting for two different transmit protocols and accommodates transmit and receive functions on either edge of the serial bit clock Error detection logic is provided for warning of the receive buffer overflow The HSPI has a facility to gener...

Page 900: ...R SPSR SPTBR Control register Receive buffer register System control register Status register Transmit buffer register SPSR SPSCR SPTBR SPRBR MSB LSB HSPI_TX HSPI_RX Interrupt SPII Legend HSPI_CS HSPI_CLK Bus interface Register System control Shift register Clock division Peripheral clock Pck Polarity selection SCK generator Figure 23 1 Block Diagram of HSPI ...

Page 901: ...dress Area 7 Address Size Sync Clock Control register SPCR R W H FFE5 0000 H 1FE5 0000 32 Pck Status register SPSR R W H FFE5 0004 H 1FE5 0004 32 Pck System control register SPSCR R W H FFE5 0008 H 1FE5 0008 32 Pck Transmit buffer register SPTBR R W H FFE5 000C H 1FE5 000C 32 Pck Receive buffer register SPRBR R H FFE5 0010 H 1FE5 0010 32 Pck Note To clear the flag only 0s are written to bits 4 and...

Page 902: ...be read as an undefined value The write value should always be 0 7 FBS 0 R W First Bit Start Controls the timing relationship between each bit of transferred data and the serial bit clock 0 The first bit transmitted from the HSPI module is set up such that it can be sampled by the receiving device on the first edge of HSPI_CLK after the HSPI_CS pin goes low Similarly the first received bit is samp...

Page 903: ...00 1 intermediate frequency cycle Serial bit clock frequency Intermediate frequency 2 00001 2 Intermediate frequency cycles Serial bit clock frequency Intermediate frequency 4 00010 3 intermediate frequency cycles Serial bit clock frequency Intermediate frequency 6 11111 32 intermediate frequency cycles Serial bit clock frequency Intermediate frequency 64 The serial bit clock frequency can be comp...

Page 904: ... R R R R R R R R Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 1 0 0 1 0 0 TXFL TXFN RXFL RXOW RXOO RXEM RXHA RXFU TXEM TXHA TXFU R R R R W R W R R R R R R R R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 11 Undefined R Reserved These bits are always read as an undefined value The write value should always be 0 10 TXFU 0 R Transmit FIFO Full ...

Page 905: ...s set to 1 when the receive FIFO reaches the halfway point that is it has 4 bytes of data and 4 spaces for more data This flag is cleared to 0 when the receive data is read from receive FIFO and the FIFO level becomes under 4 bytes halfway point It remain set to 1 until cleared to 0 regardless of the subsequent FIFO levels If RXHA 1 and RHIE 1 then the interrupt is generated 5 RXEM 1 R Receive FIF...

Page 906: ...are loaded into the SPRBR This bit is cleared to 0 by reading SPRBR If RXFL 1 and RXDE 1 then the DMA transfer request enabled 1 TXFN 0 R Transmit Complete Status Flag This status flag indicates that the last transmission has completed It is set to 1 when SPTBR is able to write more data from the peripheral bus This bit is cleared to 0 by writing more data SPTBR If TXFN 1 and TFIE 1 then the inter...

Page 907: ...W R W R W R W R W R W R W R W R W R W R W R R Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 14 All 0 R Reserved Although the initial value is 0 these bits will be read as an undefined value The write value should always be 0 13 TEIE 0 R W Transmit FIFO Empty Interrupt Enable 0 Transmit FIFO empty interrupt disabled 1 Transmit FIFO empty interrupt enabled 12 THIE 0 R W Tran...

Page 908: ... 0 R W LSB MSB First Control 0 Data is transmitted and received most significant bit MSB first 1 Data is transmitted and received least significant bit LSB first 6 CSV 1 R W Chip Select Value Controls the value output from the chip select when the HSPI is a master and the chip select generation has been selected 0 Chip select output is low 1 Chip select output is high 5 CSA 0 R W Automatic Manual ...

Page 909: ... a 32 bit readable writable register that stores data to be transmitted 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 30 R R R R R R R R R R R R R R R R Bit Initial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 TD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R R R R R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 8 ...

Page 910: ...ial value R W 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 RD 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 8 All 0 R Reserved Although the initial value is 0 these bits will be read as an undefined value The write value should always be 0 7 to 0 RD All 0 R Receive Data Data from the s...

Page 911: ...om slave Another transmit required End Figure 23 2 Operational Flowchart Depending on the settings of SPCR the master transmits data to the slave on either the falling or rising edge of HSPI_CLK and samples data from the slave on the opposite edge The data transfer between the master and slave completes when the transmit complete status flag TXFN in SPSR is set to 1 This flag should be used to ide...

Page 912: ...When the DMAC indicates that all transfers have ended then the DMA request signals in the HSPI module should be disabled to remove any remaining DMA requests This is necessary as the HSPI module will always request data to transmit 23 4 3 Operation with FIFO Mode Enabled In order to reduce the interrupt overhead on the processor in the case for operation without DMA mode FIFO mode has been provide...

Page 913: ...ot empty interrupt and read data from the receive FIFO until it is empty Write more data to the transmit FIFO if required 4 Disable the module when the transfer is to stop 23 4 4 Timing Diagrams The following diagrams explain the timing relationship of all shift and sample processes in the HSPI Figure 23 3 shows the conditions when FBS 0 while figure 23 4 shows the conditions when FBS 1 It can be ...

Page 914: ... reset should be generated before asserting the HSPI_CS This prevent the HSPI from receiving an erroneous data 23 4 6 Clock Polarity and Transmit Control SPCR also allows the user to define the shift timing for transmit data and polarity The FBS bit in SPCR allows selection between two different transfer formats The MSB or LSB is valid on the falling edge of HSPI_CS The CLKP bit in SPCR allows for...

Page 915: ... of a command commands extended by the secure multimedia card Secure MMC and additional commands can be supported in the future within the range of combinations of currently defined command types response types 24 1 Features The MMCIF has the following features Interface that complies with The MultiMediaCard System Specification Version 3 1 Supports MMC mode Incorporates 64 data transfer FIFOs of ...

Page 916: ...rupt control MMC mode control Card clock generator Figure 24 1 Block Diagram of MMCIF 24 2 Input Output Pins Table 24 1 summarizes the pins of the MMCIF Table 24 1 Pin Configuration Pin Name I O Function MCCLK Output Card clock output MCCMD Input Output Command output response input MCDAT Input Output Data input output Note For insertion detachment of a card or for signals switching over between o...

Page 917: ...E6 000B 8 Pck Interrupt control register 0 INTCR0 R W H FFE6 000C H 1FE6 000C 8 Pck Interrupt control register 1 INTCR1 R W H FFE6 000D H 1FE6 000D 8 Pck Interrupt status register 0 INTSTR0 R W H FFE6 000E H 1FE6 000E 8 Pck Interrupt status register 1 INTSTR1 R W H FFE6 000F H 1FE6 000F 8 Pck Transfer clock control register CLKON R W H FFE6 0010 H 1FE6 0010 8 Pck Command timeout control register C...

Page 918: ...H 1FE6 002B 8 Pck Response register 12 RSPR12 R W H FFE6 002C H 1FE6 002C 8 Pck Response register 13 RSPR13 R W H FFE6 002D H 1FE6 002D 8 Pck Response register 14 RSPR14 R W H FFE6 002E H 1FE6 002E 8 Pck Response register 15 RSPR15 R W H FFE6 002F H 1FE6 002F 8 Pck Response register 16 RSPR16 R W H FFE6 0030 H 1FE6 0030 8 Pck CRC status register RSPRD R W H FFE6 0031 H 1FE6 0031 8 Pck Data timeout...

Page 919: ...ontrol register 0 INTCR0 H 00 H 00 Retained Retained Interrupt control register 1 INTCR1 H 00 H 00 Retained Retained Interrupt status register 0 INTSTR0 H 00 H 00 Retained Retained Interrupt status register 1 INTSTR1 H 00 H 00 Retained Retained Transfer clock control register CLKON H 00 H 00 Retained Retained Command timeout control register CTOCR H 01 H 01 Retained Retained Transfer byte number c...

Page 920: ... H 00 H 00 Retained Retained Response register 12 RSPR12 H 00 H 00 Retained Retained Response register 13 RSPR13 H 00 H 00 Retained Retained Response register 14 RSPR14 H 00 H 00 Retained Retained Response register 15 RSPR15 H 00 H 00 Retained Retained Response register 16 RSPR16 H 00 H 00 Retained Retained CRC status register RSPRD H 00 H 00 Retained Retained Data timeout register DTOUTR H FFFF H...

Page 921: ...rguments CMDR5 CRC and End bit Setting of CRC is unnecessary automatic calculation End bit is fixed to 1 and its setting is unnecessary automatic setting The read value is 0 CMDR0 to CMDR4 Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 command argument 0 0 0 0 R W R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 7 to 0 Command argument All 0 R W Command arguments See specifica...

Page 922: ...STR has been set to 1 or until command transmit end interrupt has occurred Command sequences are controlled by the sequencers in both the MMCIF side and the MMC card side Normally these operate synchronously However if an error occurs or a command is aborted these may become temporarily unsynchronized Be careful when setting the CMDOFF bit in OPCR issuing the CMD12 command or processing an error i...

Page 923: ...OFF command Write enabled period From command transmission completion to command sequence end Write of 0 Operation is not affected Write of 1 Command sequence is forcibly aborted Note Do not write to this bit out of the write enable period 6 0 R Reserved This bit is always read as 0 The write value should always be 0 5 RD_CONTI 0 R W Read Continue Read data reception is resumed when 1 is written w...

Page 924: ...it out of the write enable period 3 to 0 All 0 R Reserved These bits are always read as 0 The write value should always be 0 In write data transmission the contents of the command response and data response should be analyzed and then transmission should be triggered In addition the data transmission should be temporarily halted by FIFO full empty and it should be resumed when the preparation has ...

Page 925: ... the MMCIF command sequence is aborted 0 Idle state waiting for a command or data busy state 1 Command sequence execution in progress 6 FIFO_FULL 0 R FIFO Full This bit is set to 1 when the FIFO becomes full while data is being received from the card and cleared to 0 when RD_CONTI is set to 1 or the command sequence is completed Indicates whether the FIFO is empty or not 0 The FIFO is empty 1 The ...

Page 926: ...without data transfer which includes the busy state in the response or a command with write data has been ended 0 Idle state waiting for a command or command sequence execution in progress 1 Card is in the data busy state after command sequence termination 2 DTBUSY_TU Undefined R Data Busy Pin Status Indicates the MCDAT pin level By reading this bit the MCDAT level can be monitored 0 A low level i...

Page 927: ... FFIE 0 R W FIFO Full Interrupt Flag Setting Enable 0 Disables FIFO full interrupt disables FFI flag setting 1 Enables FIFO full interrupt enables FFI flag setting 5 DRPIE 0 R W Data Response Interrupt Flag Setting Enable 0 Disables data response interrupt disables DPRI flag setting 1 Enables data response interrupt enables DPRI flag setting 4 DTIE 0 R W Data Transfer End Interrupt Flag Setting En...

Page 928: ... setting 0 BTIE 0 R W Multiple block Transfer End Flag Flag Setting Enable 0 Disables multiple block transfer end flag setting 1 Enables multiple block transfer end flag setting INTCR1 Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W INTR Q2E INTR Q1E INTR Q0E CRCE RIE DTE RIE CTE RIE R W R W R R R W R W R W Bit Bit Name Initial Value R W Description 7 INTRQ2E 0 R W ERR Interrupt Enable 0...

Page 929: ... flag setting 0 CTERIE 0 R W Command Timeout Error Interrupt Flag Setting Enable 0 Disables command timeout error interrupt disables CTERI flag setting 1 Enables command timeout error interrupt enables CTERI flag setting INTCR2 Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R W FRDYIE R R R R R R R W INTR Q3E Bit Bit Name Initial Value R W Description 7 INTRQ3E 0 R W FRDY Interrupt Enable 0...

Page 930: ...itial Value R W Description Interrupt output 7 FEI 0 R W FIFO Empty Interrupt Flag 0 No interrupt Clearing condition Write 0 after reading FEI 1 Writing 1 is invalid 1 Interrupt requested Setting condition When FIFO becomes empty while FEIE 1 and data is being transmitted when the FIFO_EMPTY bit in CSTR is set FSTAT 6 FFI 0 R W FIFO Full Interrupt Flag 0 No interrupt Clearing condition Write 0 aft...

Page 931: ... after reading DTI 1 Writing 1 is invalid 1 Interrupt requested Setting condition When the number of bytes of data transfer specified in TBCR ends while DTIE 1 TRAN 3 CRPI 0 R W Command Response Receive End Interrupt Flag 0 No interrupt Clearing condition Write 0 after reading CRPI 1 Writing 1 is invalid 1 Interrupt requested Setting condition When command response reception ends while CRPIE 1 TRA...

Page 932: ...after reading DBSYI 1 Writing 1 is invalid 1 Interrupt requested Setting condition When data busy state is canceled while DBSYIE 1 When the DTBUSY bit in CSTR is cleared TRAN 0 BTI 0 R W Multiple block Transfer End Flag 0 No interrupt Clearing condition Write 0 after reading BTI 1 Writing 1 is invalid 1 Interrupt requested Setting condition When the number of bytes of data transfer specified in TB...

Page 933: ...ndition When a CRC error for command response or receive data or a CRC status error for transmit data response is detected while CRCERIE 1 For the command response CRC is checked when the RTY4 in RSPTYR is enabled ERR 1 DTERI 0 R W Data Timeout Error Interrupt Flag 0 No interrupt Clearing condition Write 0 after reading DTERI 1 Writing 1 is invalid 1 Interrupt requested Setting condition When a da...

Page 934: ...d R FIFO Ready Flag Regardless of set values of DMAEN and FRDYIE this bit is read as 0 when FIFO data amount matches the condition set in DMACR 2 0 and otherwise read as 1 0 FRDYI 0 R W FIFO Ready Interrupt Flag 0 No interrupt Clearing condition Write 0 after reading FRDYI 1 Writing 1 is invalid 1 Interrupt requested Setting condition When remained FIFO data does not match the assert condition set...

Page 935: ...n 6 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 2 1 0 CSEL3 CSEL2 CSEL1 CSEL0 0 0 0 0 R W R W R W R W Transfer Clock Frequency Select 0000 Reserved 0001 Uses the 1 2 divided peripheral clock as a transfer clock 0010 Uses the 1 4 divided peripheral clock as a transfer clock 0011 Uses the 1 8 divided peripheral clock as a transfer clock 0100 Uses the 1 ...

Page 936: ...les reaches the number specified in CTOCR When the CTERIE bit in INTCR1 is set to 1 the CTERI flag in INTSTR1 is set As CTOUTC continues counting transfer clock the CTERI flag setting condition is repeatedly generated To perform command timeout error handling the command sequence should be aborted by setting the CMDOFF bit to 1 and then the CTERI flag should be cleared to prevent extra interrupt g...

Page 937: ... data block This setting is ignored by the stream transfer command Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R C2 C3 C1 C0 R R R R W R W R W R W Bit Bit Name Initial Value R W Description 7 to 4 All 0 R Reserved These bits are always read as 0 The write value should always be 0 3 2 1 0 CS3 CS2 CS1 CS0 0 0 0 0 R W R W R W R W Transfer Data Block Size Four or more bytes should be set bef...

Page 938: ...m sending a command by setting the START bit in CMDSTRT to 1 and ends when all necessary data transmission reception and response reception have been completed The multimedia card supports the data busy state such that only the specific command is accepted to write erase data to from the flash memory in the card during command sequence execution and after command sequence execution has ended The d...

Page 939: ...Y6 to TY2 to all 0s Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R TY4 TY3 TY2 TY1 TY0 R W R W R W R W R W R W R W TY6 TY5 Bit Bit Name Initial Value R W Description 7 to 5 All 0 R Reserved These bits are always read as 0 The write value should always be 0 6 TY6 0 R W Type 6 Specifies a predefined multiple block transaction TY 1 0 should be set to 01 or 10 When using the command set to th...

Page 940: ...equence of the multiple block transfer specified by this bit ends when it is aborted by the CMD12 command 1 0 TY1 TY0 0 0 R W R W Types 1 and 0 These bits specify the existence and direction of transfer data 00 A command without data transfer 01 A command with read data reception 10 A command with write data transmission 11 Setting prohibited 24 3 12 Response Type Register RSPTYR RSPTYR is an 8 bi...

Page 941: ...s not check CRC through CRC7 1 Checks CRC through CRC7 3 0 R Reserved These bits are always read as 0 The write value should always be 0 2 1 0 RTY2 RTY1 RTY0 0 0 0 R W R W R W Response Types 2 to 0 These bits specify the number of command response bytes 000 A command needs no command response 001 Setting prohibited 010 Setting prohibited 011 Setting prohibited 100 A command needs 6 byte command re...

Page 942: ... 101 CMD3 SET_RELATIVE_ADDR R1 00 4 100 CMD4 SET_DSR 00 000 CMD7 SELECT DESELECT_CARD R1b 00 1 4 100 CMD9 SEND_CSD R2 00 101 CMD10 SEND_CID R2 00 101 CMD11 READ_DAT_UNTIL_STOP R1 1 01 4 100 CMD12 STOP_TRANSMISSION R1b 1 00 1 4 100 CMD13 SEND_STATUS R1 00 4 100 CMD15 GO_INACTIVE_STATE 00 000 CMD16 SET_BLOCKLEN R1 00 4 100 CMD17 READ_SINGLE_BLOCK R1 3 01 4 100 CMD18 READ_MULTIPLE_BLOCK R1 2 2 01 4 1...

Page 943: ...AST_IO R4 00 4 100 CMD40 GO_IRQ_STATE R5 00 4 100 CMD42 LOCK_UNLOCK R1b 10 1 4 100 CMD55 APP_CMD R1 00 4 100 CMD56 GEN_CMD R1b 5 1 4 100 Notes A blank Means value 0 1 These commands are not supported after MMCA Ver3 1 specification cards 2 Set the TY6 bit and clear the TY2 bit when the transfer block number is set in advance clear the TY6 bit and set the TY2 bit when the transfer block number is n...

Page 944: ...umber in the TBNCR The value of TBNCR is decremented by one as each block transfer is executed and the command sequence ends when the TBNCR value equals 0 TBNCR Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 15 to 0 TBNCR All 0 R W Transfer Block N...

Page 945: ...the number of command response bytes and valid RSPR register Table 24 6 Correspondence between Command Response Byte Number and RSPR MMC Mode Response RSPR registers 6 bytes R1 R1b R3 R4 R5 17 bytes R2 RSPR0 1st byte RSPR1 2nd byte RSPR2 3rd byte RSPR3 4th byte RSPR4 5th byte RSPR5 6th byte RSPR6 7th byte RSPR7 8th byte RSPR8 9th byte RSPR9 10th byte RSPR10 11th byte RSPR11 1st byte 12th byte RSPR...

Page 946: ...00 R W These bits are cleared to H 00 by writing an arbitrary value RSPR0 to RSPR16 comprise a continuous 17 byte shift register RSPRD Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R RSPRD R R R W R W R W R W R W Bit Bit Name Initial Value R W Description 7 to 5 All 0 R Reserved These bits are always read as 0 The write value should always be 0 4 to 0 RSPRD 00000 R W CRC status Clearing co...

Page 947: ...rescaler output and enters the data timeout error states when the number of prescaler outputs reaches the number specified in DTOUTR When the DTERIE bit in INTCR1 is set to 1 the DTERI flag in INTSTR1 is set As DTOUTC continues counting prescaler output the DTERI flag setting condition is repeatedly generated To perform data timeout error handling the command sequence should be aborted by setting ...

Page 948: ...in that order Word access and byte access can be done in random order However DR address 1 cannot be accessed in bytes The following shows examples of DR access When data is written to DR in the following steps 1 to 4 the transmit data is stored in the FIFO as shown in figure 24 2 1 Write word data H 0123 to DR 2 Write byte data H 45 to DR 3 Write word data H 6789 to DR 4 Write byte data H AB to D...

Page 949: ...24 2 DR Access Example 24 3 17 FIFO Pointer Clear Register FIFOCLR The FIFO write read pointer is cleared by writing an arbitrary value to FIFOCLR Bit Initial value R W 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 W FIFOCLR W W W W W W W Bit Bit Name Initial Value R W Description 7 to 0 FIFOCLR H 00 W The FIFO pointer is cleared by writing an arbitrary value to this register ...

Page 950: ...f DMA request signal 6 AUTO 0 R W Auto Mode for pre defined multiple block transfer using DMA transfer 0 Disable auto mode 1 Enable auto mode 5 to 3 All 0 R Reserved These bits are always read as 0 The write value should always be 0 2 1 0 SET2 SET1 SET0 0 0 0 R W R W R W DMA Request Signal Assert Condition Sets DMA request signal assert condition 000 Not output 001 FIFO remained data is 1 4 or les...

Page 951: ...nsfer In this case the next command is the CMD12 command which aborts the current command sequence In MMC mode broadcast commands that simultaneously issue commands to multiple cards are supported After information of the inserted cards is recognized by a broadcast command a relative address is given to each card One card is selected by the relative address other cards are deselected and then vari...

Page 952: ... state 2 Operation of Relative Address Commands CMD7 CMD9 CMD10 CMD13 CMD15 CMD39 and CMD55 are relative address commands that address the card by RCA The relative address commands are used to read card administration information and original information and to change the specific card states CMD7 sets one addressed card to the transfer state and the other cards to the standby state Only the card ...

Page 953: ...MD MCDAT CMDSTRT START INTSTR0 CMDI CSTR CWRE BUSY REQ Input output pins Command output 48 bits Command transmission started Command transmission ended Cleared by software Command transmission period Command sequence period Figure 24 3 Example of Command Sequence for Commands Not Requiring Command Response ...

Page 954: ...ry operation commands include a number of commands that do not include data transfer Such commands execute the desired data transfer using command arguments and command responses For a command that is related to time consuming processing such as flash memory write erase the card indicates the data busy state via the MCDAT Figures 24 5 and 24 6 show examples of the command sequence for commands wit...

Page 955: ...detected through the data busy end interrupt DBSYI Write the CMDOFF bit to 1 if a CRC error CRCERI or a command timeout error CTERI occurs The MCCMD and MCDAT pins go to the high impedance state when the MMCIF and the MMC card do not drive the bus and the input level of these pins are high because they are pulled up internally MCCLK MCCMD MCDAT CMDSTRT START INTSTR0 CMDI CSTR BUSY CWRE REQ CRPI DB...

Page 956: ... CRPI DBSYI DTBUSY_TU DTBUSY Input output pins Command output 48 bits Command transmission started Command response reception Command transmission period Command sequence execution period Response reception completed Data busy period Busy state completed Busy state Figure 24 6 Example of Command Sequence for Commands without Data Transfer with Data Busy State ...

Page 957: ...type to CMDTYR Set command response type to RSPTYR Set the START bit in CMDSTRT to 1 Yes No CRCERI interrupt detected Yes No CRPI interrupt detected Yes No R1b response Yes No DTBUSY detected Yes No Yes No DBSYI interrupt detected End of command sequence CTERI interrupt detected Write CMDOFF to 1 Figure 24 7 Example of Operational Flow for Commands without Data Transfer ...

Page 958: ...ay not be received correctly Therefore to receive the command response correctly the command sequence must be continued set the RD_CONT bit to 1 until the command response reception ends Figures 24 8 to 24 11 show examples of the command sequence for commands with read data Figures 24 12 to 24 14 show the operational flows for commands with read data Make settings to issue the command and clear FI...

Page 959: ...rror CTERI occurs in the command response reception Clear the FIFO by writing the CMDOFF bit to 1 when CRC error CRCERI and data timeout error DTERI occurs in the read data reception MCCLK MCCMD MCDAT CMDSTRT START INTSTR0 CMDI CMDOFF CSTR CWRE BUSY REQ CRPI DTI FFI FIFO_FULL CMD17 READ_SINGLE_BLOCK OPCR RD_CONTI Input output pins Command Command response Read data Command transmission started Sin...

Page 960: ...INGLE_BLOCK OPCR RD_CONTI Input output pins Transfer clock transmission halted Transfer clock transmission resumed Command response Command Block data reception suspended Read data Read data Block data reception resumed Reading data from FIFO Single block read command execution sequence Command transmission started Figure 24 9 Example of Command Sequence for Commands with Read Data Block Size FIFO...

Page 961: ...2 STOP_TRANSMISSION OPCR RD_CONTI Input output pins Transfer clock transmission halted Transfer clock transmission resumed Read data Block data reception ended Multiblock read command execution sequence Stop command execution sequence Command Command Command transmission started Command response Read data Read data Command response Figure 24 10 Example of Command Sequence for Commands with Read Da...

Page 962: ... Data reception resumed Data reception ended Read data from FIFO Stream read command execution sequence MCCLK MCCMD MCDAT CMDSTRT START INTSTR0 CMDI CMDOFF CSTR CWRE BUSY REQ CRPI DTI FFI BTI FIFO_FULL OPCR RD_CONTI Command Read data Read data Read data Command response Command Command response Command transmission started Transfer clock transmission halted Data reception suspended Figure 24 11 Ex...

Page 963: ...tatus normal ended Yes No End of command sequence CTERI interrupt detected Yes No FFI interrupt detected Set the CMDOFF to 1 Read data from FIFO Set the RD_CONTI to 1 Read data from FIFO No Yes DTERI interrupt detected No Yes CRCERI interrupt detected No Yes Legend Len Block length Byte Cap FIFO size Byte n FFI Number of FFI from read sequence starts DTERI interrupt detected Yes No DTI interrupt d...

Page 964: ...sponse register Execute CMD18 CMDR to CMDSTRT Set the number of transfer block size to TBCR No Yes CRCERI interrupt detected Yes No CMD16 normal end Yes No CRPI interrupt detected Yes No Response status normal ended Yes No CTERI interrupt detected 1 2 Figure 24 13 Example of Operational Flow for Commands with Read Data 1 Open ended Multiple Block Transfer ...

Page 965: ... CRCERI interrupt detected No Yes Legend Len Block length Byte Cap FIFO size Byte n FFI Number of FFI from read sequence starts n DTI Number of DTI from read sequence start DTERI interrupt detected Yes No Next block read Yes No DTI interrupt detected Yes No Cap Len 1 n DTI Cap n FFI Set the CMDOFF to 1 Execute CMD12 Set the CMDOFF to 1 Execute CMD12 Clear FIFO 1 2 Figure 24 13 Example of Operation...

Page 966: ...MDSTRT Set the number of transfer block size to TBCR No Yes CRCERI interrupt detected Yes No CMD16 normal end Execute CMD23 Set the number of transfer block TBNCR Yes No CMD23 normal end Yes No CRPI interrupt detected Yes No Response status normal ended Yes No CTERI interrupt detected 1 2 Figure 24 13 Example of Operational Flow for Commands with Read Data 3 Pre defined Multiple Block Transfer ...

Page 967: ... Yes Legend Len Block length Byte Cap FIFO size Byte n FFI Number of FFI from read sequence starts n DTI Number of DTI from read sequence start DTERI interrupt detected Yes No BTI interrupt detected Yes No DTI interrupt detected Yes No Cap Len 1 n DTI Cap n FFI Yes No TBNCR value n DTI Set the CMDOFF to 1 Execute CMD12 Read data from FIFO Set the CMDOFF to 1 Clear FIFO 1 2 Figure 24 13 Example of ...

Page 968: ...rupt detected Yes No Response status normal ended Yes No End of command sequence CTERI interrupt detected Yes No FFI interrupt detected Set the CMDOFF to 1 Read data from FIFO Set the RD_CONTI to 1 No Yes DTERI inte rrupt detected Yes No Data read completed Set the CMDOFF to 1 Execute CMD12 Execute CMD12 Read data from FIFO Set the CMDOFF to 1 Clear FIFO Figure 24 14 Example of Operational Flow fo...

Page 969: ...command sequence to continue Figures 24 15 to 24 18 show examples of the command sequence for commands with write data Figures 24 19 to 24 21 show the operational flows for commands with write data Make settings to issue a command and clear FIFO Set the START bit in CMDSTRT to 1 to start command transmission MCCMD must be kept driven until the end bit output is completed Command transmission compl...

Page 970: ...data busy state the end of the data busy state is detected by the data busy end interrupt DBSYI Write the CMDOFF bit to 1 if a CRC error CRCERI or a command timeout error CTERI occurs in the command response reception Write the CMDOFF bit to 1 if a CRC error CRCERI or a data timeout error DTERI occurs in the write data transmission Note In a write to the card by stream transfer the MMCIF continues...

Page 971: ...MDOFF CSTR CWRE BUSY DTBUSY DTBUSY_TU REQ CRPI DTI DBSYI FEI FIFO_EMPTY CMD24 WRITE_SINGLE_BLOCK OPCR DATAEN DRPI Input output pins Command Command response Command transmission started Single block write command execution sequence Write data Status Busy Figure 24 15 Example of Command Sequence for Commands with Write Data Block Size FIFO Size ...

Page 972: ...4 WRITE_SINGLE_BLOCK OPCR DATAEN Input output pins Command Command response Command transmission started Busy Transfer clock transmission halted Transfer clock transmission resumed Block data transmission suspended Writing data to FIFO Write data Write data Block data transmission resumed Single block write command execution sequence Figure 24 16 Example of Command Sequence for Commands with Write...

Page 973: ...25 WRITE_MULTIPE_BLOCK CMD12 STOP_TRANSMISSION OPCR DATAEN Input output pins Write data Write data Write data Status Status Block data transmission started Block data reception ended Next block data transmission started Stop command execution sequence Command Command response Command Command response Command transmission started Figure 24 17 Example of Command Sequence for Commands with Write Data...

Page 974: ...nse Command Stop command execution sequence Busy Transfer clock trans mission halted Transfer clock trans mission halted Transfer clock transmission resumed Transfer clock transmission resumed Writing data to FIFO Data transmission suspended Data transmission suspended Data transmission resumed Data transmission ended Stream write command execution sequence Command response Command transmission st...

Page 975: ...e status normal ended Yes No End of command sequence CTERI interrupt detected Set the CMDOFF to 1 Writing data to FIFO Set the DATAEN to 1 Yes DTBUSY detected Yes DBSYI interrupt detected No Yes CRCERI interrupt detected No Yes Legend Len Block length Byte Cap FIFO size Byte n FEI Number of FEI from read sequence starts DTERI interrupt detected Yes No DRPI interrupt detected Yes Cap n FEI Len No N...

Page 976: ...ponse register Execute CMD25 CMDR to CMDSTRT Set the number of transfer block size to TBCR No Yes CRCERI interrupt detected Yes No CMD16 normal end Yes No CRPI interrupt detected Yes No Response status normal ended Yes No CTERI interrupt detected 1 2 Figure 24 20 Example of Operational Flow for Commands with Write Data 1 Open ended Multiple Block Transfer ...

Page 977: ... size or FIFO size or for FIFO size block size FIFO size Len Block length Byte Cap FIFO size Byte n FEI Number of FEI from read sequence starts n DRPI Number of DRPI from write sequence starts Legend DTERI interrupt detected Yes No DRPI interrupt detected Yes Cap n FEI Len 1 n DTI Len No No Yes DTI interrupt detected No Yes FEI interrupt detected No Set the CMDOFF to 1 Set the CMDOFF to 1 Execute ...

Page 978: ...e register Execute CMD25 CMDR to CMDSTRT Set the number of transfer block size to TBCR No Yes CRCERI interrupt detected Yes No CMD16 normal end Yes No CRPI interrupt detected Yes No Response status normal ended Yes No CTERI interrupt detected Execute CMD 23 Yes No CMD 23 normal end 1 2 Figure 24 20 Example of Operational Flow for Commands with Write Data 3 Pre defined Multiple Block Transfer ...

Page 979: ...IFO size Len Block length Byte Cap FIFO size Byte n FEI Number of FEI from read sequence starts n DRPI Number of DRPI from write sequence starts Legend DTERI interrupt detected Yes No DRPI interrupt detected Yes Cap n FEI Len 1 n DRPI Len No No Yes TBNCR n DRPI No Yes BTI interrupt detected No Yes DTI interrupt detected No Yes FEI interrupt detected No Set the CMDOFF to 1 Set the CMDOFF to 1 Set t...

Page 980: ...CERI interrupt detected Yes No CRPI interrupt detected Yes No Response status normal ended Yes No CTERI interrupt detected End of command sequence Writing data to FIFO Set the DATAEN to 1 Yes No All data write to FIFO completed Yes FEI interrupt detected No Set the CMDOFF to 1 Set the CMDOFF to 1 Execute CMD12 Figure 24 21 Example of Operational Flow for Commands with Write Data Stream Transfer ...

Page 981: ... be individually enabled by the enable bits in INTCR0 to INTCR2 Disabled interrupt sources do not set the flag Table 24 7 MMCIF Interrupt Sources Name Interrupt source Interrupt flag FIFO empty FEI FSTAT FIFO full FFI Data response DRPI Data transfer end DTI Command response receive end CRPI Command transmit end CMDI TRAN Data busy end DBSYI CRC error CRCERI Data timeout error DTERI ERR Command ti...

Page 982: ...lear DMACR to H 00 if a CRC error CRCERI or a command timeout error CTERI occurs in the command response reception Set the CMDOFF bit to 1 clear DMACR to H 00 and clear FIFO if a CRC error CRCERI or a data timeout error DTERI occurs in the read data reception When using DMA next block read is resumed automatically when the AUTO bit in DMACR is set to 1 and normal read is detected after the block t...

Page 983: ...MACR to 0 Set the CMDOFF bit to 1 and clear DMACR to H 00 if a CRC error CRCERI or a command timeout error CTERI occurs in the command response reception Set the CMDOFF bit to 1 clear DMACR to H 00 and clear FIFO if a CRC error CRCERI or a data timeout error DTERI occurs in the read data reception Note In multiple block transfer when the command sequence is ended the CMDOFF bit is written to 1 bef...

Page 984: ... 1 Clear the DMACR to H 00 CMD16 normal end No Yes CRPI interrupt detected No Yes Response status normal ended No Yes DTI interrupt detected No Yes DMA transfer end No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No CRCERI interrupt detected Yes No DTERI interrupt detected Yes No Set the number of transfer block size to TBCR Execute CMD17 CMDR to CMDSTRT Set the CMDOFF to 1 Cl...

Page 985: ...ted condition Set DMACR Read response register CMD16 normal end No Yes CRPI interrupt detected No Yes Response status normal ended No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No Set the number of transfer block size to TBCR Execute CMD 18 CMDR to CMDSTRT 1 2 Figure 24 23 Example of Read Sequence Flow 1 Open ended Multiple Block Transfer ...

Page 986: ...OFF to 1 Clear the DMACR to H 00 Execute CMD12 Set the CMDOFF to 1 DTI interrupt detected No Yes DMA transfer end No Yes CRCERI interrupt detected Yes No DTERI interrupt detected Yes No Next block read No Yes 1 2 Set RD_CONTI to 1 Set the CMDOFF to 1 Clear the DMACR to H 00 Clear FIFO Execute CMD12 Figure 24 23 Example of Read Sequence Flow 2 Open ended Multiple Block Transfer ...

Page 987: ... register CMD16 normal end No Yes CRPI interrupt detected No Yes Response status normal ended No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No Set the number of transfer block size to TBCR Set the number of block to TBNCR Execute CMD 18 CMDR to CMDSTRT Execute CMD 23 CMD 23 normal end No Yes 1 2 Figure 24 23 Example of Read Sequence Flow 3 Pre defined Multiple Block Transfer...

Page 988: ... Set the CMDOFF to 1 DTI interrupt detected No Yes DMA transfer end No Yes CRCERI interrupt detected Yes No DTERI interrupt detected Yes No BTI interrupt detected No Yes TBNCR n DTI No Yes Legend n DTI Number of DTI from read sequence start 1 2 Set RD_CONTI to 1 Set the CMDOFF to 1 Clear the DMACR to H 00 Clear FIFO Execute CMD12 Figure 24 23 Example of Read Sequence Flow 4 Pre defined Multiple Bl...

Page 989: ...gister Set the CMDOFF to 1 Execute CMD12 Set the CMDOFF to 1 Clear the DMACR to H 00 CRPI interrupt detected No Yes Response status normal ended No Yes DMA transfer end No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No DTERI interrupt detected Yes No Execute CMD11 CMDR to CMDSTRT Set the CMDOFF to 1 Execute CMD12 Clear FIFO Figure 24 24 Example of Operational Flow for Stream ...

Page 990: ...16 normal end No Yes CRPI interrupt detected No Yes Response status normal ended No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No Set the number of transfer block size to TBCR Set the number of transfer block to TBNCR Execute CMD 18 CMDR to CMDSTRT Execute CMD 23 CMD 23 normal end No Yes 1 2 Figure 24 25 Example of Operational Flow for Auto mode Pre defined Multiple Block Re...

Page 991: ...o 1 Clear the DMACR to H 00 Clear the DMACR to H 00 Clear FIFO Execute CMD12 Set the CMDOFF to 1 Clear the DMACR to H 00 Set the CMDOFF to 1 BTI interrupt detected No Yes DMA transfer end No Yes CRCERI interrupt detected Yes No DTERI interrupt detected Yes No 1 2 Figure 24 25 Example of Operational Flow for Auto mode Pre defined Multiple Block Read Transfer 2 ...

Page 992: ...sfer is completed and be sure to clear the DMAEN bit in DMACR to 0 Set the CMDOFF bit to 1 if a CRC error CRCERI or a data timeout error DTERI occurs in the command response reception Set the CMDOFF bit to 1 clear FIFO and clear DMACR to H 00 if a CRC error CRCERI or a data timeout error DTERI occurs in the write data transmission When using DMA an inter block interrupt can be processed by hardwar...

Page 993: ...ata busy state Detect whether in the data busy state through the DTBUSY bit in CSTR after data transfer end after DRPI is detected If still in the data busy state wait for the DBSY flag to confirm that the data busy state has ended Set the CMDOFF bit to 1 and end the command sequence Set the CMDOFF bit to 1 and clear DMACR to H 00 if a CRC error CRCERI or a command timeout error CTERI occurs in th...

Page 994: ...C related condition Set DMACR Read response register CMD16 normal end No Yes CRPI interrupt detected No Yes Response status normal ended No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No Set the number of transfer block size to TBCR Execute CMD 24 CMDR to CMDSTRT 1 2 Figure 24 26 Example of Write Sequence Flow 1 Single Block Transfer ...

Page 995: ...t to 1 DRPI interrupt detected No Yes DBSYI interrupt detected No Yes CRCERI interrupt detected Yes No DTERI interrupt detected Yes No DTBUSY detected No Yes FRDYI interrupt detected or DMA transfer end No Yes Clear the DMACR to H 00 DMA transfer end No Yes DTI interrupt detected No Yes 1 2 Figure 24 26 Example of Write Sequence Flow 2 Single Block Transfer ...

Page 996: ...ed condition Set DMACR Read response register CMD16 normal end No Yes CRPI interrupt detected No Yes Response status normal ended No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No Set the number of transfer block size to TBCR Execute CMD 25 CMDR to CMDSTRT 1 2 Figure 24 27 Example of Write Sequence Flow 1 Open ended Multiple Block Transfer ...

Page 997: ...No DTERI interrupt detected Yes No Next block write No Yes DTBUSY detected No Yes FRDYI interrupt detected or DMA transfer end No Yes Clear the DMACR to H 00 DMA transfer end No Yes DTI interrupt detected No Yes 1 2 Set the CMDOFF to 1 Clear FIFO Clear the DMACR to H 00 Execute CMD12 or Tran Set the CMDOFF to 1 Execute CMD12 or Stop Set the CMDOFF to 1 Figure 24 27 Example of Write Sequence Flow 2...

Page 998: ...register CMD16 normal end No Yes CRPI interrupt detected No Yes Response status normal ended No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No Set the number of transfer block size to TBCR Execute CMD 25 CMDR to CMDSTRT 1 2 Set the number of block to TBNCR Execute CMD 23 CMD 23 normal end No Yes Figure 24 27 Example of Write Sequence Flow 3 Pre defined Multiple Block Transfer...

Page 999: ...es No BTI interrupt detected No Yes TBNCR n DRPI No Yes DTBUSY detected No Yes FRDYI interrupt detected or DMA transfer end No Yes Clear the DMACR to H 00 DMA transfer end Yes DTI interrupt detected No Yes 1 2 Set the CMDOFF to 1 Clear FIFO Clear the DMACR to H 00 Execute CMD12 or Stop Tran Set the CMDOFF to 1 Set the CMDOFF to 1 Legend n DRPI Number of DRPI from read sequence start Figure 24 27 E...

Page 1000: ...Response status normal ended No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No Execute CMD 20 CMDR to CMDSTRT End of command sequence Set the DATAEN to 1 FRDYI interrupt detected or DMA transfer end No Yes Clear the DMACR to H 00 DMA transfer end No Yes FEI interrupt detected No Yes Set the CMDOFF to 1 Execute CMD12 Set the CMDOFF to 1 Figure 24 28 Example of Operational Flow...

Page 1001: ... CMD16 normal end No Yes CRPI interrupt detected No Yes Response status normal ended No Yes CTERI interrupt detected No Yes CRCERI interrupt detected Yes No Set the number of transfer block size to TBCR Execute CMD 25 CMDR to CMDSTRT 1 2 Set the number of block to TBNCR Execute CMD 23 CMD 23 normal end No Yes Figure 24 29 Example of Operational Flow for Auto mode Pre defined Multiple Block Write T...

Page 1002: ...cted No Yes CRCERI interrupt detected Yes No DTERI interrupt detected Yes No DTBUSY detected No Yes Clear the DMACR to H 00 DMA transfer end No Yes 1 2 Set the CMDOFF to 1 Clear FIFO Clear the DMACR to H 00 Execute CMD12 or Stop Tran Set the CMDOFF to 1 Set the CMDOFF to 1 Figure 24 29 Example of Operational Flow for Auto mode Pre defined Multiple Block Write Transfer 2 ...

Page 1003: ...h Little Endian Specification When the little endian is specified the access size for registers or that for memory where the corresponding data is stored should be fixed For example if data read from the MMCIF with the word size is written to memory and then it is read from memory with the byte size data misalignment occurs ...

Page 1004: ...Section 24 Multimedia Card Interface MMCIF Rev 1 00 Dec 13 2005 Page 954 of 1286 REJ09B0158 0100 ...

Page 1005: ...or the DMA transfer by the DMAC can be used 25 1 Features The HAC has the following features Supports Digital interface to a subset of a single AC 97 revision 2 1 Audio Codec PIO transfer of status slots 1 and 2 in Rx frames PIO transfer of command slots 1 and 2 in Tx frames PIO transfer of data slots 3 and 4 in Rx frames PIO transfer of data slots 3 and 4 in Tx frames Selectable 16 bit or 20 bit ...

Page 1006: ... for slot 1 Shift register for slot 2 Shift register for slot 3 Shift register for slot 4 DMA control DMA control CSAR TX buffer CSDR TX buffer PCML TX buffer PCMR TX buffer CSAR RX buffer CSDR RX buffer PCML RX buffer PCMR RX buffer Data 19 0 Data 19 0 Data 19 0 Data 19 0 DMA request DMA request Slot3 slot4 request signal Figure 25 1 Block Diagram 25 2 Input Output Pins Table 25 1 describes the H...

Page 1007: ...32 Pck RX status register HACRSR R W H FFE4 005C H 1FE4 005C 32 Pck HAC control register HACACR R W H FFE4 0060 H 1FE4 0060 32 Pck Table 25 3 Register States of HAC in Each Processing Mode Register Name Abbrev Power on Reset by PRESET Pin WDT H UDI Manual Reset by WDT Multiple Exceptions Sleep by SLEEP Instruction Module Standby Control and status register HACCR H 0000 0200 H 0000 0200 Retained Re...

Page 1008: ...R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 R R R R W W R R CR CDRT WMRT ST 0 Bit Bit Name Initial Value R W Description 31 to 16 All 0 R Reserved Always 0 for read and write 15 CR 0 R Codec Ready 0 The HAC connected codec is not ready 1 The HAC connected codec is ready 14 to 12 All 0 R Reserved Always read as 0 Write prohibited 11 CDRT 0 W HAC Cold Reset Use a cold res...

Page 1009: ... 5 ST 0 W Start Transfer Write 1 Starts data transmission reception 0 Stops data transmission reception at the end of the current frame Do not take this action to terminate transmission reception in normal operation Read Always read as 0 4 to 0 All 0 R Reserved Always 0 for read and write To place the off chip codec device into the power down mode write 1 to bit 12 of the register index 26 in the ...

Page 1010: ... R R R R R R R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R R R R CA3 SA3 CA2 SA2 CA1 SA1 CA0 SA0 SLR EQ3 SLR EQ4 SLR EQ5 SLR EQ6 SLR EQ7 SLR EQ8 SLR EQ9 SLR EQ10 SLR EQ11 SLR EQ12 CA6 SA6 RW CA5 SA5 CA4 SA4 0 Bit Bit Name Initial Value R W Description 31 to 20 All 0 R Reserved Always 0 for read and write 19 RW 0 R W Codec Read Write...

Page 1011: ...be written Read Indicate the status address received via slot 1 corresponding to the codec register whose data has been returned in HACCSDR 11 10 9 8 7 6 5 4 3 2 SLREQ3 SLREQ4 SLREQ5 SLREQ6 SLREQ7 SLREQ8 SLREQ9 SLREQ10 SLREQ11 SLREQ12 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R Slot Requests 3 to 12 Valid only in the Rx frame Indicate whether the codec is requesting slot data in the next Tx frame Auto...

Page 1012: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W CD11 SD11 CD10 SD10 CD9 SD9 CD8 SD8 CD7 SD7 CD6 SD6 CD5 SD5 CD4 SD4 CD3 SD3 CD2 SD2 CD1 SD1 CD0 SD0 CD15 SD15 CD14 SD14 CD13 SD13 CD12 SD12 0 Bit Bit Name Initial Value R W Description 31 to 20 All 0 R Reserved Always 0 for read and write 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 CD15 SD15 CD14 SD14 CD13 ...

Page 1013: ...bits or less 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value R R R R R R R R R R R R R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W D19 D18 D17 D16 D3 D2 D1 D0 D7 D6 D5 D4 D11 D10 D9 D8 D15 D14 D13 D12 0 Bit Bit Name Initia...

Page 1014: ...D3 RD1 RD2 RD0 RD7 RD6 RD5 RD4 RD11 RD10 RD9 RD8 RD15 RD14 RD13 RD12 LD3 LD1 LD2 LD0 LD7 LD6 LD5 LD4 LD11 LD10 LD9 LD8 LD15 LD14 LD13 LD12 0 Bit Bit Name Initial Value R W Description 31 to 16 LD15 to LD0 All 0 R W Left Data 15 to 0 Write the PCM playback left channel data to these bits The HAC then transmits the data to the codec on an on demand basis Read these bits to get the PCM record left ch...

Page 1015: ...it or less 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value R R R R R R R R R R R R R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W D19 D18 D17 D16 D3 D2 D1 D0 D7 D6 D5 D4 D11 D10 D9 D8 D15 D14 D13 D12 0 Bit Bit Name Initial ...

Page 1016: ...F RQIE 0 Bit Bit Name Initial Value R W Description 31 30 All 0 R Reserved Always 0 for read and write 29 PLTFRQIE 0 R W PCML TX Request Interrupt Enable 0 Disables PCML TX request interrupts 1 Enables PCML TX request interrupts 28 PRTFRQIE 0 R W PCMR TX Request Interrupt Enable 0 Disables PCMR TX request interrupts 1 Enables PCMR TX request interrupts 27 to 10 All 0 R Reserved Always 0 for read a...

Page 1017: ...Q 0 Bit Bit Name Initial Value R W Description 31 CMDAMT 1 R W 2 Command Address Empty 0 CSAR Tx buffer contains untransmitted data 1 CSAR Tx buffer is empty and ready to store data 1 30 CMDDMT 1 R W 2 Command Data Empty 0 CSDR Tx buffer contains untransmitted data 1 CSDR Tx buffer is empty and ready to store data 1 29 PLTFRQ 1 R W 2 PCML TX Request 0 PCML Tx buffer contains untransmitted data 1 P...

Page 1018: ...t written to PCMR 7 to 0 All 0 R Reserved Always 0 for read and write Notes 1 CMDAMT and CMDDMT have no associated interrupts Poll these bits until they are read as 1 before writing a new command to HACCSAR HACCSDR When bit 19 RW of HACCSAR is 0 and TX12_ATOMIC is 1 take the following steps 1 Initialize CMDDMT and CMDAMT before first accessing a codec register after HAC initialization by any reset...

Page 1019: ...tatus Address Ready Interrupt Enable 0 Disables status address ready interrupts 1 Enables status address ready interrupts 21 STDRYIE 0 R W Status Data Ready Interrupt Enable 0 Disables status data ready interrupts 1 Enables status data ready interrupts 20 PLRFRQIE 0 R W PCML RX Request Interrupt Enable 0 Disables PCML RX request interrupts 1 Enables PCML RX request interrupts 19 PRRFRQIE 0 R W PCM...

Page 1020: ...Y STDRY PLR FRQ PRR FRQ PLR FOV PRR FOV 0 Bit Bit Name Initial Value R W Description 31 to 23 All 0 R Reserved Always 0 for read and write 22 STARY 0 R W Status Address Ready 0 HACCSAR status address is not ready 1 HACCSAR status address is ready 21 STDRY 0 R W Status Data Ready 0 HACCSDR status data is not ready 1 HACCSDR status data is ready 20 PLRFRQ 0 R W PCML RX Request 0 PCML RX data is not ...

Page 1021: ...g 0 to the bit initializes it but writing 1 has no effect 25 3 10 HAC Control Register HACACR HACACR is a 32 bit read write register used for controlling the HAC interface 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 Initial value R R W R W R R R W R R W R W R W R W R R R R R R R R R R R R R R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 ...

Page 1022: ...ely Setting prohibited 1 Transmits TX data in HACCSAR and that in HACCSDR in the same frame if bit 19 in HACCSAR is 0 write HACCSAR must be written last 25 0 R Reserved Always 0 for read and write 24 RXDMAL_EN 0 R W RX DMA Left Enable 0 Disables 20 bit RX DMA for HACPCML 1 Enables 20 bit RX DMA is for HACPCML 23 TXDMAL_EN 0 R W TX DMA Left Enable 0 Disables 20 bit TX DMA for HACPCML 1 Enables 20 b...

Page 1023: ...5 4 AC97 Transmit Frame Structure Slot Name Description 0 SDATA_OUT TAG Codec IDs and Tags indicating valid data 1 Control CMD Addr write port Read write command and register address 2 Control DATA write port Register write data 3 PCM L DAC playback Left channel PCM output data 4 PCM R DAC playback Right channel PCM output data 5 Modem Line 1 DAC Modem 1 output data unsupported 6 PCM Center Center...

Page 1024: ...ted 12 Modem IO status Modem control IO input unsupported Notes There is no register for unsupported functions 25 5 Operation 25 5 1 Receiver The HAC receiver receives serial audio data input on the HAC_SDIN pin synchronous to HAC_BITCLK From slot 0 the receiver extracts tag bits that indicate which other slots contain valid data It will update the receive data only when receiving valid slot data ...

Page 1025: ...d DMATX16 bits in HACACR When the data size is 20 bits transfer of data slots 3 and 4 requires two local bus access cycles Since each of the receiver and transmitter has its DMA request the stereo mode generates a DMA request for slots 3 and 4 separately The mono mode generates a DMA request for just one slot When the data size is 16 bits data from slots 3 and 4 are packed into a single 32 bit qua...

Page 1026: ...DMA transfer Receiver Transmitter HACCR H 0000 0020 Codec ready HACCR H 0000 8000 Set DMAC Set read address H 26 Power down Ctrl Stat HACCSAR H 000A 6000 External codec internal status ADC DAC Analog REF ready HACCSDR H 0000 00F0 Set read volume and sampling rate TX RX enable set HACACR H 03E0 0000 20 bit DMATX slot 1 and slot 2 are atomic control External codec device initialization HAC module in...

Page 1027: ...Cnt to 0 TSR CMDAMT 1 TSR CMDDMT 1 Wait for 1 µs LoopCnt Necessary setting ACR TX12_ATOMIC 1 No Yes 5 RetryCnt Error Return E1 Number required for the target system 21 E1 1000 Input Addr Address of the codec register to be written to Data Data to be written to the codec register RetryCnt Software counter for error detection LoopCnt Software counter for wait insertion Notes RetryCnt Figure 25 4 Sam...

Page 1028: ...ead_codec_aux Input RegN address of the codec register to be read When external codec registers are read in sequence data in the last register that was read may be read again in some codec devices In this case use the read procedure shown in this flowchart Send_read_request RegN Error Error Error Error Error Data 2 return Send_read_request RegN Get_codec_data RegN Get_codec_data RegN Data 1 acquis...

Page 1029: ...o Yes Yes No Yes Get_codec_data Clear LoopCnt2 to 0 Input RegN address of the codec register to be read WaitLoop_RSR Addr R RegN Assign HACCSDR read value to DataT DataT return E2 Number required for the target system 13 E2 LoopCnt2 Software counter for wait insertion Addr Variable to hold CSAR read value DataT Variable to hold CSDR read value Notes Wait for 5 ms LoopCnt2 Assign HACCSAR read value...

Page 1030: ...otes E3 and E4 Numbers required for the target system 21 E3 21 E4 1000 LoopCnt3 Software counter for wait insertion LoopCnt4 Software counter for wait insertion Error RSR STARY 1 RSR STDRY 1 Write 0 to RSR STARY Write 0 to RSR STDRY Yes E4 LoopCnt 4 Wait for 1 µs LoopCnt4 Figure 25 7 Sample Flowchart for Off Chip Codec Register Read 3 It is possible to stop the supply of clock to the HAC using the...

Page 1031: ...ule standby mode is shown below 1 Check that all data transactions have ended Also check that the transmit buffer of the HAC is empty and the receive buffer of the HAC has been read out to be empty 2 Disable all DMA requests and interrupt requests 3 Place the codec into power down mode 4 Write 1 to the MSTP0 bit in MSTPCR 25 5 6 Notes The HAC_SYNC signal is generated by the HAC to indicate the pos...

Page 1032: ...Section 25 Audio Codec Interface HAC Rev 1 00 Dec 13 2005 Page 982 of 1286 REJ09B0158 0100 ...

Page 1033: ... the following features Number of channels One channel Operating modes Compressed mode and non compressed mode The compressed mode is used for continuous bit stream transfer The non compressed mode supports all serial audio streams divided into channels The SSI module is configured as any of a transmitter or receiver The serial bus format can be used in the compressed and non compressed mode Async...

Page 1034: ...rcuit Bit counter Serial clock control Divider LSB MSB Shift register Figure 26 1 Block Diagram of SSI Module 26 2 Input Output Pins Table 26 1 lists the pin configurations relating to the SSI module Table 26 1 Pin Configuration Pin Name I O Function SSI_SCK I O Serial bit clock SSI_WS I O Word select SSI_SDATA I O Serial data input output SSI_CLK Input Divider input clock oversampling clock 256 3...

Page 1035: ...t data register SSITDR R W H FFE7 0008 H 1FE7 0008 32 Pck Receive data register SSIRDR R H FFE7 000C H 1FE7 000C 32 Pck Note To clear the flag only 0s are written to bits 27 and 26 Table 26 3 Register States of SSI in Each Processing Mode Register Name Abbrev Power on Reset by PRESET Pin WDT H UDI Manual Reset by PRESET Pin WDT Multiple Exception Sleep by SLEEP Instruction Module Standby Control r...

Page 1036: ... W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 29 R Reserved These bits are always read as an undefined value The write value should always be 0 28 DMEN 0 R W DMA Enable Enables or disables the DMA request 0 DMA request disabled 1 DMA request enabled 27 UIEN 0 R W Un...

Page 1037: ...s indicate the encoded number of bits in a data word These bits are ignored if CPEN 1 000 8 Bits 001 16 Bits 010 18 Bits 011 20 Bits 100 22 Bits 101 24 Bits 110 32 Bits 111 Setting prohibited 18 17 16 SWL2 SWL1 SWL0 0 0 0 R W R W R W System Word Length These bits indicate the encoded number of bits in a system word These bits are ignored if CPEN 1 000 8 Bits 001 16 Bits 010 24 Bits 011 32 Bits 100...

Page 1038: ...CK rising edge SSI_WS input sampling in slave mode SWSD 0 SSI_SCK rising edge SSI_SCK falling edge SSI_WS output change timing in master mode SWSD 1 SSI_SCK falling edge SSI_SCK rising edge 12 SWSP 0 R W Serial WS Polarity The function of this bit depends on whether the SSI module is in non compressed mode or compressed mode CPEN 0 Non compressed mode 0 SSI_WS is low for the first channel high for...

Page 1039: ...aning This bit is applied to SSIRDR in receive mode and to SSITDR in transmit mode 0 Parallel data SSITDR or SSIRDR is left aligned 1 Parallel data SSITDR or SSIRDR is right aligned DWL 000 data word length 8 bits PDTA ignored All data bits in SSIRDR or SSITDR are used on the audio serial bus Four data words are transmitted received in each 32 bit access The first data word is derived from bits 7 ...

Page 1040: ...hich are used in SSIRDR or SSITDR are the following Bits number of bits having data word length specified by DWL 1 to 0 If DWL 011 then data word length is 20 bits and bits 19 to 0 are used of either SSIRDR or SSITDR All other bits are ignored or reserved DWL 110 data word length 32 bits PDTA ignored All data bits in SSIRDR or SSITDR are used on the audio serial bus 8 DEL 0 R W Serial Data Delay 0...

Page 1041: ...al bit clock frequency oversampling clock frequency 8 100 Serial bit clock frequency oversampling clock frequency 16 101 Serial bit clock frequency oversampling clock frequency 6 110 Serial bit clock frequency oversampling clock frequency 12 111 Setting prohibited 3 MUEN 0 R W Mute Enable When in transmit mode TRMD 1 by making MUEN 1 the output of SSI_SDATA will be in low level 0 The SSI module is...

Page 1042: ... 0 R R R R R W R R R R W R R R R R R R 0 0 1 1 R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R W Description 31 to 29 R Reserved These bits are always read as an undefined value The write value should always be 0 28 DMRQ 0 R DMA Request Status Flag This status flag allows the CPU to see the status of the DMA request of SSI module TRMD 0 Receive Mode If DMRQ 1 then SSIRDR has unread da...

Page 1043: ...1 it indicates that SSIRDR was read out before DMRQ and DIRQ bits would indicate the existence of new unread data In this instance the same received data may be stored twice by the host which can lead to destruction of multi channel data When TRMD 1 Transmit Mode If UIRQ 1 it indicates that the transmitted data was not written in SSITDR By this the same data may be transmitted one time too often w...

Page 1044: ... destruction of multi channel data When TRMD 1 Transmit Mode If OIRQ 1 it indicates that SSITDR had data written in before the data in SSITDR was transferred to the shift register This may cause the loss of data which can lead to destruction of multi channel data Note When overflow error occurs the data in the data buffer will be overwritten by the next data sent from the SSI interface 25 IIRQ 1 R...

Page 1045: ...ead data exists in SSIRDR 1 Unread data exists in SSIRDR When TRMD 1 Transmit Mode 0 The transmit buffer is full 1 The transmit buffer is empty and requires that data be written in SSITDR 23 to 4 R Reserved These bits are always read as an undefined value The write value should always be 0 3 2 CHNO1 CHNO0 0 0 R R Channel Number The number indicates the current channel When TRMD 0 Receive Mode This...

Page 1046: ...This bit is cleared if EN 1 and the Serial Bus is currently active This bit can be set to 1 automatically under the following conditions SSI Serial bus master transmitter SWSD 1 and TRMD 1 This bit is set to 1 if no more data has been written to SSITDR and the current system word has been completed It can also be set to 1 by clearing the EN bit after sufficient data has been written to SSITDR to c...

Page 1047: ...nitial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 26 3 4 Receive Data Register SSIRDR SSIRDR is a 32 bit register that stores the received data Data in SSIRDR is transferred from the shift register as each data word is received If the ...

Page 1048: ...6 4 Bus Formats of SSI Module Bus Format TPMD CPEN SCKD SWSD EN MUEN DIEN IIEN OIEN UIEN DEL PDTA SDTA SPDP SWSP SCKP SWL 2 0 DWL 2 0 CHNL 1 0 Non Compressed Slave Receiver 0 0 0 0 Non Compressed Slave Transmitter 1 0 0 0 Non Compressed Master Receiver 0 0 1 1 Non Compressed Master Transmitter 1 0 1 1 Control bits Configuration bits Compressed Slave Receiver 0 1 0 1 0 Compressed Slave Transmitter ...

Page 1049: ...form to the format as specified in the SSI module then operation is not guaranteed 3 Master Receiver This mode allows the SSI module to receive serial data from another device The clock and word select signals are internally derived from the HAC_BIT_CLK input clock The format of these signals is as defined in the SSI module If the incoming data does not conform to the defined format then operation...

Page 1050: ... SSI_SCK SSI_WS SSI_SDATA SCKP 0 SWSP 0 DEL 0 CHNL 00 System word length data word length Figure 26 2 Philips Format with no Padding MSB LSB MSB LSB Next System word 1 System word 2 Data word 1 Data word 2 Padding Padding SSI_SCK SSI_WS SSI_SDATA SCKP 0 SWSP 0 DEL 0 CHNL 00 SPDP 0 SDTA 0 System word length data word length Figure 26 3 Philips Format with Padding Figure 26 4 shows the format used b...

Page 1051: ...0 SWSP 0 DEL 1 CHNL 00 SPDP 0 SDTA 1 System word length data word length Figure 26 5 Matsushita Format with Padding Bits First Followed by Serial Data 6 Multi Channel Formats There are some extend format of the Philips specification that allows more than 2 channels to be transferred within two system words The SSI module supports the transfer of 4 6 and 8 channels by the use of the CHNL SWL and DW...

Page 1052: ... 32 24 16 14 12 10 8 0 100 48 40 32 30 28 26 24 16 101 64 56 48 46 44 42 40 32 110 128 120 112 110 108 106 104 96 00 1 111 256 248 240 238 236 234 232 224 000 8 001 16 0 010 24 8 011 32 16 0 100 48 32 16 12 8 4 0 101 64 48 32 28 24 20 16 0 110 128 112 96 92 88 84 80 64 01 2 111 256 240 224 220 216 212 208 192 000 8 001 16 010 24 0 011 32 8 100 48 24 0 101 64 40 16 10 4 110 128 104 80 74 68 62 56 3...

Page 1053: ...e transmitted received first and followed by serial data in the third example This selection is purely arbitrary MSB LSB Data word 1 MSB LSB MSB LSB MSB LSB Data word 2 Data word 3 Data word 4 System word 1 System word 2 MSB LSB Data word 1 MSB LSB MSB LSB MSB LSB Data word 2 Data word 3 Data word 4 System word 1 System word 2 LSB MSB SSI_SCK SSI_WS SSI_SDATA SCKP 0 SWSP 0 DEL 1 CHNL 01 SPDP don t...

Page 1054: ...ystem word 1 Padding SSI_WS SSI_SDATA SSI_SCK SCKP 0 SWSP 0 DEL 1 CHNL 11 SPDP 0 SDTA 1 System word length data word length 4 Figure 26 8 Multi channel Format 8 Channels with Padding Bits First Followed by Serial Data with Padding 7 Configuration Fields Signal Format Fields There are several more configuration bits in non compressed mode which will now be demonstrated These bits are NOT mutually e...

Page 1055: ...e in SSI module demonstration only DWL 4 bits not attainable in SSI module demonstration only CHNL 00 SCKP 0 SWSP 0 SPDP 0 SDTA 0 PDTA 0 DEL 0 MUEN 0 4 bit data samples continuously written to SSITDR are transmitted onto the serial audio bus Figure 26 9 Basic Sample Format Transmit Mode with Example System Data Word Length In figure 26 9 system word length of 6 bits and a data word length of 4 bit...

Page 1056: ...t 3 Inverted Padding Polarity SSI_SCK SSI_WS SSI_SDATA TD28 TD31 1st Channel 2nd Channel 1 1 1 1 1 1 TD31 TD30 TD29 TD28 TD31 TD30 TD29 TD28 As basic sample format configuration except SPDP 1 Figure 26 12 Inverted Padding Polarity 4 Padding Bits First Followed by Serial Data with Delay SSI_SCK SSI_WS SSI_SDATA 0 0 0 TD28 0 0 1st Channel 2nd Channel TD30 TD29 TD31 TD30 TD29 TD28 TD31 TD30 TD29 TD28...

Page 1057: ... Followed by Serial Data without Delay 6 Serial Data First Followed by Padding Bits without Delay As basic sample format configuration except DEL 1 0 0 0 0 0 0 TD31 TD30 TD31 TD30 TD29 TD28 TD31 TD30 TD29 TD28 SSI_SCK SSI_WS SSI_SDATA 1st Channel 2nd Channel Figure 26 15 Serial Data First Followed by Padding Bits without Delay 7 Parallel Right Aligned with Delay As basic sample format configuratio...

Page 1058: ...rst mode is enabled then data bits being transmitted can be identified by virtue of the fact that the serial clock output is only activated when there is a word to be output and only the required number of clock pulses necessary to clock out each 32 bit word are generated The serial bit clock stops at a low level when SSICR SCKP 0 and at a high level when SSICR SCKP 1 Note burst mode is only valid...

Page 1059: ...Figure 26 19 Compressed Data Format Slave Transmitter and Burst Mode Enabled 1 Slave Receiver This mode allows the module to receive a serial bit stream from another device and store it in memory The shift register clock can be supplied from an external device or from an internal clock The word select pin is used as an input flow control Assuming that SWSP 0 if SSI_WS is high then the module will ...

Page 1060: ...aster Transmitter This mode allows the module to transmit a serial bit stream from internal memory to another device The shift register clock can be supplied from an external device or from an internal clock The word select pin is used as an output flow control The module always asserts the word select signal to indicate it will transmit more data continuously Word select signal is not asserted un...

Page 1061: ...us inactive EN 0 IDST 0 EN 0 IDST 1 Reset Figure 26 20 Transition Diagram between Operation Modes 1 Configuration Mode This mode is entered after the module is released from reset All required settings in the control register should be defined in this mode before the SSI module is enabled by setting the EN bit Setting the EN bit causes the SSI module to enter the module enabled mode 2 Module Enabl...

Page 1062: ... interrupts that the SSI module generates to supply data as required This mode has a higher interrupt load as the SSI module is only double buffered and will require data to be written at least every system word period When disabling the SSI module the SSI clock must be supplied continuously until the module enters in the idle state indicated by the IIRQ bit Figure 26 21 shows the transmit operati...

Page 1063: ...from DMAC or SSI SSI error interrupt Has DMAC Tx data been completed More data to be send Disable SSI module disable DMA disable error interrupt enable Idle interrupt Wait for idle interrupt from SSI module Reset SSI module if required End Note When SSI error interrupt occurs underflow overflow back to start and execute flow again Yes No No Yes Yes No Specify TRMD EN SCKD SWSD MUEN DEL PDTA SDTA S...

Page 1064: ...ore data to be send Disable SSI module disable DMA disable error interrupt enable Idle interrupt Wait for Idle interrupt from SSI module Reset SSI module if required End No Yes Yes No Specify TRMD EN SCKD SWSD MUEN DEL PDTA SDTA SPDP SWSP SCKP SWL DWL CHNL EN 1 DIEN 1 UIEN 1 OIEN 1 Use SSI status register bits to realign data after underflow overflow EN 0 DIEN 0 UIEN 0 OIEN 0 IIEN 1 Load data of c...

Page 1065: ...an be controlled in one of two ways either DMA or an interrupt driven Figures 26 23 and 26 24 show the flow of operation When disabling the SSI module the SSI clock must be supplied continuously until the module enters in the idle state which is indicated by the IIRQ bit Note SCKD 0 Clock input through the SSI_SCK pin SCKD 1 Clock input through the SSI_CLK pin ...

Page 1066: ... from DMAC or SSI SSI Error interrupt Has DMAC Rx data been completed More data to be received Disable SSI module disable DMA disable error interrupt enable Idle interrupt Wait for idle interrupt from SSI module Reset SSI module if required End Note When SSI error interrupt occurs underflow overflow back to start and execute flow again Specify TRMD EN SCKD SWSD MUEN DEL PDTA SDTA SPDP SWSP SCKP SW...

Page 1067: ...Error interrupt More data to be received Disable SSI module disable data interrupt disable error IRQ enable idle IRQ Wait for idle interrupt from SSI module Reset SSI module if required End Yes No Yes No Specify TRMD EN SCKD SWSD MUEN DEL PDTA SDTA SPDP SWSP SCKP SWL DWL CHNL EN 1 DIEN 1 UIEN 1 OIEN 1 Use SSI status register bits to realign data after underflow overflow EN 0 DIEN 0 UIEN 0 OIEN 0 I...

Page 1068: ...ntil it is ready to store the sample data that the SSI module is indicating that it will receive next to ensure consistency of the number of received data and so resynchronize with the audio data stream 26 4 7 Serial Clock Control This function is used to control and select which clock is used for the serial bus interface If the serial clock direction is set to input SCKD 0 the SSI module is in cl...

Page 1069: ...w occurs under the condition of control register SSICR data word length DWL2 to DWL0 is 32 bit and system word length SWL2 to SWL0 is 32 bit SSI has received the data at right channel that should be received at left channel If an overflow occurs through an overflow error interrupt or overflow error status flag the OIRQ bit in SSISR disable the DMA transfer of the SSI to halt its operation by writi...

Page 1070: ...Section 26 Serial Sound Interface SSI Module Rev 1 00 Dec 13 2005 Page 1020 of 1286 REJ09B0158 0100 ...

Page 1071: ...ect one of the following two access modes Command access mode Performs an access by specifying a command to be issued from the FLCTL to flash memory address and data size to be input or output Read write or erasure of data without ECC processing can be achieved Sector access mode Performs a read or write in physical sector units by specifying a physical sector By specifying the number of sectors t...

Page 1072: ...of flash memory to the DMA controller data and control code can be sent to different areas Access Size Registers can be accessed in 32 bits or 8 bits Registers must be accessed in the specified access size FIFOs are accessed in 32 bits 4 bytes Set the byte number for read to a multiple of four and the byte number for write to a multiple of four Access Time The operating frequency of the FLCTL pins...

Page 1073: ...H FIFO 256 bytes 32 4 8 8 8 32 32 CPG FCKSEL 1 1 2 1 4 FCLK DMA transfer requests 2 lines Peripheral bus Peripheral bus interface Interrupts FLSTE FLTEND FLTRQ0 FLTRQ1 Registers Interrupt control Transmission reception control Control signal Note FCLK is an operating clock for interface signals with flash memory QTSEL Peripheral clock Pck FLCTL Figure 27 1 FLCTL Block Diagram ...

Page 1074: ...e Output RE Read Enable RE Reads data at the falling edge of RE FWE 5 Write enable Output WE Write Enable Flash memory latches a command address and data at the rising edge of WE FRB 4 Ready busy Input R B Ready Busy Indicates ready state at high level indicates busy state at low level WP Write Protect Reset Not supported When this pin goes low erroneous erasure or programming at power on or off c...

Page 1075: ...r FLBSYTMR R W H FFE9 001C H 1FE9 001C 32 Ready busy timeout counter FLBSYCNT R H FFE9 0020 H 1FE9 0020 32 Data FIFO register FLDTFIFO R W H FFE9 0024 H 1FE9 0024 32 Control code FIFO register FLECFIFO R W H FFE9 0028 H 1FE9 0028 32 Transfer control register FLTRCR R W H FFE9 002C H 1FE9 002C 8 Table 27 3 Register States of FLCTL in Each Processing Mode Register Abbreviation Power On Reset Manual ...

Page 1076: ... SEL ECCPOS 1 0 ACM 1 0 NAND WF SE CE0 TYPE SEL Bit Bit Name Initial Value R W Description 31 to 18 All 0 R Reserved These bits are always read as 0 The write value should always be 0 17 QTSEL 0 R W Fourth Divided Flash Clock Select 0 Uses the value in FCKSEL 1 Divides a peripheral clock Pck provided from the CPG by four and uses it as FCLK when FCKSEL 0 Note When FCKSEL 1 setting to 1 to this bit...

Page 1077: ...ited 11 Setting prohibited 9 NANDWF 0 R W NAND Wait Insertion Operation 0 Performs address or data input output in one FCLK cycle 1 Performs address or data input output in two FCLK cycles 8 SE 0 R W Spare Area control code area Enable bit 0 Spare area access enable can be access the data area and the control code area continuously 1 Spare area access disable In sector access mode clear this bit t...

Page 1078: ...CTCNT 15 0 Bit Bit Name Initial Value R W Description 31 to 27 All 0 R Reserved These bits are always read as 0 The write value should always be 0 26 ADRMD 0 R W Sector Access Address Specification This bit is invalid in command access mode This bit is valid only in sector access mode 0 The value of the address register is handled as a physical sector number Use this value usually in sector access...

Page 1079: ...2 byte address 10 Issue 3 byte address 11 Issue 4 byte address 17 DOCMD2 0 R W Second Command Stage Execution Specification Specifies whether or not the second command stage is executed in command access mode 0 Does not execute the second command stage 1 Executes the second command stage 16 DOCMD1 0 R W First Command Stage Execution Specification Specifies whether or not the first command stage is...

Page 1080: ... 0 The write value should always be 0 15 to 8 CMD 15 8 H 00 R W Specify a command code to be issued in the second command stage 7 to 0 CMD 7 0 H 00 R W Specify a command code to be issued in the first command stage 27 3 4 Address Register FLADR FLADR is a 32 bit readable writable register that specifies an address to be output in command access mode In sector access mode a physical sector number s...

Page 1081: ...fy 1st data to be output to flash memory as an address in command access mode Sector Access Mode 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 R R R R R R R R R R R R R R R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W ADR 17 16 ADR 15 0 Bit Bit Name Initi...

Page 1082: ...ese bit values are used when the CPU reads from or writes to FLECFIFO In FLECFIFO read these bits specify the number of longwords of the data that can be read from FLECFIFO In FLECFIFO write these bits specify the number of longwords of empty area that can be written in FLECFIFO 23 to 16 DTFLW 7 0 H 00 R FLDTFIFO Access Count Specify the number of longwords 4 byte in FLDTFIFO to be read or written...

Page 1083: ...R W R W Bit Initial value R W Bit Initial value R W DT 31 24 DT 23 16 DT 15 8 DT 7 0 Bit Bit Name Initial Value R W Description 31 to 24 DT 31 24 H 00 R W Fourth Data Specify the 4th data to be input or output via the FD7 to FD0 pins In write Specify write data In read Store read data 23 to 16 DT 23 16 H 00 R W Third Data Specify the 3rd data to be input or output via the FD7 to FD0 pins In write ...

Page 1084: ...arted 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R W R W R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W FIFOTRG 1 0 AC1 CLR AC0 CLR DREQ1 EN DREQ0 EN STE RB BTO ERB TRR EQF1 TRR EQF0 STER INTE RBER INTE TE INTE T...

Page 1085: ...e a DMA transfer request to the DMAC when FLDTFIFO stores 16 bytes of data In flash memory programming 00 Issue an interrupt to the CPU when FLDTFIFO has empty area of 4 bytes or more do not set DMA transfer 01 Issue an interrupt or a DMA transfer request to the CPU when FLDTFIFO has empty area of 16 bytes or more 10 Issue an interrupt to the CPU when FLDTFIFO has empty area of 128 bytes or more d...

Page 1086: ...le Enables or disables the DMA transfer request issued from FLDTFIFO 0 Disables the DMA transfer request issued from the FLDTFIFO 1 Enables the DMA transfer request issued from the FLDTFIFO 15 to 10 All 0 R Reserved These bits are always read as 0 The write value should always be 0 9 0 R Reserved Although the initial value is 0 this bit will be read as an undefined value The write value should alw...

Page 1087: ...ag 1 cannot be written to this bit Only 0 can be written to clear the flag 0 Indicates that no transfer request is issued from FLECFIFO 1 Indicates that a transfer request is issued from FLECFIFO 5 TRREQF0 0 R W FLDTFIFO Transfer Request Flag Indicates that a transfer request is issued from FLDTFIFO This bit is a flag 1 cannot be written to this bit Only 0 can be written to clear the flag 0 Indica...

Page 1088: ... CPU 1 Enables the transfer end interrupt request to the CPU 1 TRINTE1 0 R W FLECFIFO Transfer Request Enable to CPU Enables or disables an interrupt request to the CPU by a transfer request issued from FLECFIFO 0 Disables an interrupt request to the CPU by a transfer request from FLECFIFO 1 Enables an interrupt request to the CPU by a transfer request from FLECFIFO When the DMA transfer is enable...

Page 1089: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R W R W R W R W 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W RBTMOUT 19 16 RBTMOUT 15 0 Bit Bit Name Initial Value R W Description 31 to 20 All 0 R Reserved These bits are always read as 0 The write value should always be 0 19 to 0 RBTMOUT 19 0 H 0...

Page 1090: ...n interrupt is enabled by the RBERINTE bit in FLINTDMACR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R Bit Initial value R W Bit Initial value R W STAT 7 0 RBTIMCNT 19 16 RBTIMCNT 15 0 Bit Bit Name Initial Value R W Description 31 t...

Page 1091: ...R W Bit Initial value R W DTFO 31 24 DTFO 23 16 DTFO 15 8 DTFO 7 0 Bit Bit Name Initial Value R W Description 31 to 24 DTFO 31 24 Undefined R W First Data Specify 1st data to be input or output via the FD7 to FD0 pins In write Specify write data In read Store read data 23 to 16 DTFO 23 16 Undefined R W Second Data Specify 2nd data to be input or output via the FD7 to FD0 pins In write Specify writ...

Page 1092: ...l value R W Bit Initial value R W ECFO 31 24 ECFO 23 16 ECFO 15 8 ECFO 7 0 Bit Bit Name Initial Value R W Description 31 to 24 ECFO 31 24 Undefined R W First Data Specify 1st data to be input or output via the FD7 to FD0 pins In write Specify write data In read Store read data 23 to 16 ECFO 23 16 Undefined R W Second Data Specify 2nd data to be input or output via the FD7 to FD0 pins In write Spec...

Page 1093: ... TREND TRSTRT Bit Bit Name Initial Value R W Description 7 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 TREND 0 R W Processing End Flag Bit Indicates that the processing performed in the specified access mode has been completed The write value should always be 0 0 TRSTRT 0 R W Transfer Start By setting this bit from 0 to 1 when the TREND bit is 0 proce...

Page 1094: ...r write direction and number of times to the registers In this mode I O data can be transferred by the DMA via FLDTFIFO NAND Type Flash Memory Access Figure 27 2 shows an example of read operation for NAND type flash memory In this example the first command is specified as H 00 address data length is specified as 3 bytes and the number of read bytes is specified as 8 bytes in the data counter CLE ...

Page 1095: ...d 27 4 show examples of programming operation for NAND type flash memory CLE ALE WE RE I O7 to I O0 R B H 80 A2 A1 A3 1 2 3 4 5 8 Figure 27 3 Programming Operation Timing for NAND Type Flash Memory 1 CLE ALE WE RE I O7 to I O0 R B H 10 H 70 Status Figure 27 4 Programming Operation Timing for NAND Type Flash Memory 2 ...

Page 1096: ...de is stored in FLECFIFO the DREQ1EN and DREQ0EN bits in FLINTDMACR can be set to transfer by the DMA Figure 27 5 shows the relationship of DMA transfer between sectors in flash memory data and control code and memory on the address space FLCTL FLDT FIFO FLEC FIFO Flash memory Data 512 bytes Control code 16 bytes DMA channel 0 transfer DMA channel 1 transfer Address area external memory area Data ...

Page 1097: ...AND type flash memory and the address of flash memory bit17 bit0 3rd 3rd 4th 4th 2nd 2nd 1st 0 0 0 0 0 0 0 0 bit17 bit0 0 0 0 0 0 0 1st 2nd 3rd 4th Physical sector address For NAND type flash memory Physical sector address bit FLADR17 to FLADR0 Order of address output to NAND type flash memory I O Figure 27 6 Relationship between Sector Number and Address Expansion of NAND Type Flash Memory ...

Page 1098: ...guous because of an unusable sector in NAND type flash memory 00 12 0 0 11 11 12 13 13 40 40 300 12 300 1 13 28 Physical sector Values specified in registers by the CPU Physical sector specification register Sector transfer count specification register Sector 0 to sector 11 are transferred Sector 12 is transferred Sector 13 to sector 40 are transferred Logical sector Transfer start Transfer start ...

Page 1099: ...in FLINTDMACR is enabled Status Read of NAND Type Flash Memory The status register of NAND type flash memory can be read by inputting command H 70 to NAND type flash memory If programming is executed in command access mode or sector access mode while the DOSR bit in FLCMDCR is set to 1 the FLCTL automatically inputs command H 70 to NAND type flash memory and reads the status register of NAND type ...

Page 1100: ...mand stage DOADR 1 perform address stage ADRMD 1 address register value is output as memory address ADRCNT 1 0 01 issue 2 byte address DOSR 1 perform status read Command code register FLCMCDR CMD 7 0 H 60 block erase command CMD 15 8 H D0 block erase execute command Address register FLADR Set erase address to ADR 7 0 ADR 15 8 Transfer control register FLTRCR TRSTRT 1 Start flash memory accessing P...

Page 1101: ...ntrol Register FLINTDMACR DREQ1EN 1 enable DMA transfer request from FLECFIFO DREQ0EN 1 enable DMA transfer request from FLDTFIFO Perform flash memory writing Issue first command Issue address Data stage sector access Issue second command Read status FLTRCR TREND 1 End of flash memory access FLTRCR TREND 0 clear processing end flag Read status Check FLBSYCNT STAT 7 0 END Set DMAC related registers...

Page 1102: ...rm status read Set command code register FLCMCDR CMD 7 0 H 00 flash read Address register FLADR Set address to ADR 7 0 ADR 15 8 ADR 23 16 Data counter register FLDTCNTR Specify number of bytes of read data to DTCNT 11 0 Interrupt DMA control register FLINTDMACR Set enable bit of DMA transfer or interrupt request in use Set transfer control register FLTRCR TRSTRT 1 Start flash memory accessing Perf...

Page 1103: ...NTE Status error FLSTE interrupt BTOERB RBERINTE Ready busy timeout error FLTEND interrupt TREND TEINTE Transfer end FLTRQ0 interrupt TRREQF0 TRINTE0 FIFO0 transfer request FLTRQ1 interrupt TRREQF1 TRINTE1 FIFO1 transfer request Note Flags for the FIFO0 overrun error underrun error and FIFO1 overrun error underrun error also exist However no interrupt is requested to the CPU 27 7 DMA Transfer Spec...

Page 1104: ...Section 27 NAND Flash Memory Controller FLCTL Rev 1 00 Dec 13 2005 Page 1054 of 1286 REJ09B0158 0100 ...

Page 1105: ...ther General Purpose I Os GPIO or on chip modules by port control register PACR to PHCR and PJCR to PMCR and on chip module select register OMSELR The GPIO has the following features Each port pin is multiplexed pin for which the port control register can set the pin function and pull up MOS control individually Each port has a data register that stores data for the pins GPIO interrupts are suppor...

Page 1106: ...t PCIC AD23 B PB7 input output PCIC AD22 B PB6 input output PCIC AD21 B PB5 input output PCIC AD20 B PB4 input output PCIC AD19 B PB3 input output PCIC AD18 B PB2 input output PCIC AD17 B PB1 input output PCIC AD16 B PB0 input output PCIC AD15 C PC7 input output PCIC AD14 C PC6 input output PCIC AD13 C PC5 input output PCIC AD12 C PC4 input output PCIC AD11 C PC3 input output PCIC AD10 C PC2 input...

Page 1107: ... input output LBSC D29 F PF5 input output LBSC D28 F PF4 input output LBSC D27 F PF3 input output LBSC D26 F PF2 input output LBSC D25 F PF1 input output LBSC D24 F PF0 input output LBSC D23 G PG7 input output LBSC D22 G PG6 input output LBSC D21 G PG5 input output LBSC D20 G PG4 input output LBSC D19 G PG3 input output LBSC D18 G PG2 input output LBSC D17 G PG1 input output LBSC D16 G PG0 input o...

Page 1108: ...lable DREQ0 K PK7 input output DMAC DREQ1 K PK6 input output DMAC DREQ2 INTB AUDATA0 K PK5 input output DMAC LBSC H UDI Available DREQ3 INTC AUDATA1 K PK4 input output DMAC LBSC H UDI Available DACK2 MRESETOUT AUDATA2 K PK3 input output DMAC LBSC H UDI DACK3 IRQOUT AUDATA3 K PK2 input output DMAC LBSC H UDI DRAK2 CE2A K PK1 output DMAC LBSC H UDI DRAK3 CE2B AUDSYNC K PK0 output DMAC LBSC H UDI DAC...

Page 1109: ...Rev 1 00 Dec 13 2005 Page 1059 of 1286 REJ09B0158 0100 Pin Name Port GPIO Multiplexed Module GPIO Interrupt STATUS0 CMT_CTR0 Power Down Modes CMT STATUS1 CMT_CTR1 Power Down Modes CMT Note A module that uses this pin is selected by OMSELR ...

Page 1110: ...FEA 0010 H 1FEA 0010 16 Pck Port K control register PKCR R W H FFEA 0012 H 1FEA 0012 16 Pck Port L control register PLCR R W H FFEA 0014 H 1FEA 0014 16 Pck Port M control register PMCR R W H FFEA 0016 H 1FEA 0016 16 Pck Port A data register PADR R W H FFEA 0020 H 1FEA 0020 8 Pck Port B data register PBDR R W H FFEA 0022 H 1FEA 0022 8 Pck Port C data register PCDR R W H FFEA 0024 H 1FEA 0024 8 Pck ...

Page 1111: ...ll up control register PKPUPR R W H FFEA 0052 H 1FEA 0052 8 Pck Port M pull up control register PMPUPR R W H FFEA 0056 H 1FEA 0056 8 Pck Input pin pull up control register 1 PPUPR1 R W H FFEA 0060 H 1FEA 0060 16 Pck Input pin pull up control register 2 PPUPR2 R W H FFEA 0062 H 1FEA 0062 16 Pck On chip module select register OMSELR R W H FFEA 0080 H 1FEA 0080 16 Pck Note There are 8 bit and 16 bit ...

Page 1112: ...ined Retained Port A data register PADR H 00 Retained Retained Port B data register PBDR H 00 Retained Retained Port C data register PCDR H 00 Retained Retained Port D data register PDDR H 00 Retained Retained Port E data register PEDR H x0 Retained Retained Port F data register PFDR H 00 Retained Retained Port G data register PGDR H 00 Retained Retained Port H data register PHDR H xx Retained Ret...

Page 1113: ...nitial value R W Bit Bit Name Initial value R W Description 15 14 PA7MD1 PA7MD0 0 0 R W R W PA7 Mode 00 PCIC module 01 Port output 10 Port input pull up MOS Off 11 Setting prohibited 13 12 PA6MD1 PA6MD0 0 0 R W R W PA6 Mode 00 PCIC module 01 Port output 10 Port input pull up MOS Off 11 Setting prohibited 11 10 PA5MD1 PA5MD0 0 0 R W R W PA5 Mode 00 PCIC module 01 Port output 10 Port input pull up M...

Page 1114: ...le 01 Port output 10 Port input pull up MOS Off 11 Setting prohibited 28 2 2 Port B Control Register PBCR PBCR is a 16 bit readable writable register that selects the pin function 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PB0 MD0 PB0 MD1 PB1 MD0 PB1 MD1 PB2 MD0 PB2 MD1 PB3 MD0 PB3 MD1 PB4 MD0 PB4 MD1 PB5 MD0 PB5 MD1 PB6 MD0 PB6 MD1 PB7 MD1 PB7 MD0 R W R W R W R W R W R ...

Page 1115: ...PB4MD0 0 0 R W R W PB4 Mode 00 PCIC module 01 Port output 10 Port input pull up MOS Off 11 Setting prohibited 7 6 PB3MD1 PB3MD0 0 0 R W R W PB3 Mode 00 PCIC module 01 Port output 10 Port input pull up MOS Off 11 Setting prohibited 5 4 PB2MD1 PB2MD0 0 0 R W R W PB2 Mode 00 PCIC module 01 Port output 10 Port input pull up MOS Off 11 Setting prohibited 3 2 PB1MD1 PB1MD0 0 0 R W R W PB1 Mode 00 PCIC m...

Page 1116: ...nitial value R W Bit Bit Name Initial value R W Description 15 14 PC7MD1 PC7MD0 0 0 R W R W PC7 Mode 00 PCIC module 01 Port output 10 Port input pull up MOS Off 11 Setting prohibited 13 12 PC6MD1 PC6MD0 0 0 R W R W PC6 Mode 00 PCIC module 01 Port output 10 Port input pull up MOS Off 11 Setting prohibited 11 10 PC5MD1 PC5MD0 0 0 R W R W PC5 Mode 00 PCIC module 01 Port output 10 Port input pull up M...

Page 1117: ...le 01 Port output 10 Port input pull up MOS Off 11 Setting prohibited 28 2 4 Port D Control Register PDCR PDCR is a 16 bit readable writable register that selects the pin function 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PD0 MD0 PD0 MD1 PD1 MD0 PD1 MD1 PD2 MD0 PD2 MD1 PD3 MD0 PD3 MD1 PD4 MD0 PD4 MD1 PD5 MD0 PD5 MD1 PD6 MD0 PD6 MD1 PD7 MD1 PD7 MD0 R W R W R W R W R W R ...

Page 1118: ...PD4MD0 0 0 R W R W PD4 Mode 00 PCIC module 01 Port output 10 Port input pull up MOS Off 11 Setting prohibited 7 6 PD3MD1 PD3MD0 0 0 R W R W PD3 Mode 00 PCIC module 01 Port output 10 Port input pull up MOS Off 11 Setting prohibited 5 4 PD2MD1 PD2MD0 0 0 R W R W PD2 Mode 00 PCIC module 01 Port output 10 Port input pull up MOS Off 11 Setting prohibited 3 2 PD1MD1 PD1MD0 0 0 R W R W PD1 Mode 00 PCIC m...

Page 1119: ...R W Bit Initial value R W Bit Bit Name Initial value R W Description 15 14 All 0 R W Reserved These bits are always read as 0 and the write value should always be 0 13 12 PE6MD1 PE6MD0 1 1 R W R W PE6 Mode 00 INTC FLCTL module IRQ IRL7 FD7 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 11 10 PE5MD1 PE5MD0 0 0 R W R W PE5 Mode 00 PCIC module 01 Port output 10 Setting proh...

Page 1120: ...OS On Note Can be selectable the modules that use this pin by on chip module select register 28 2 6 Port F Control Register PFCR PFCR is a 16 bit readable writable register that selects the pin function and input pull up MOS control 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PF0 MD0 PF0 MD1 PF1 MD0 PF1 MD1 PF2 MD0 PF2 MD1 PF3 MD0 PF3 MD1 PF4 MD0 PF4 MD1 PF5 MD0 PF5 MD1 P...

Page 1121: ...W R W PF4 Mode 00 LBSC module 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 7 6 PF3MD1 PF3MD0 0 0 R W R W PF3 Mode 00 LBSC module 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 5 4 PF2MD1 PF2MD0 0 0 R W R W PF2 Mode 00 LBSC module 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 3 2 PF1MD1 PF1MD0 0 0 R W R W PF1 Mode 0...

Page 1122: ...R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 15 14 PG7MD1 PG7MD0 0 0 R W R W PG7 Mode 00 LBSC module 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 13 12 PG6MD1 PG6MD0 0 0 R W R W PG6 Mode 00 LBSC module 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 11 10 PG5MD1 PG5MD0...

Page 1123: ...up MOS Off 11 Port input pull up MOS On 5 4 PG2MD1 PG2MD0 0 0 R W R W PG2 Mode 00 LBSC module 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 3 2 PG1MD1 PG1MD0 0 0 R W R W PG1 Mode 00 LBSC module 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 1 0 PG0MD1 PG0MD0 0 0 R W R W PG0 Mode 00 LBSC module 01 Port output 10 Port input pull up MOS Off 11 Po...

Page 1124: ...ue R W Bit Bit Name Initial value R W Description 15 14 PH7MD1 PH7MD0 1 1 R W R W PH7 Mode 00 SCIF1 MMCIF module 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 13 1 R W Reserved This bit is always read as 1 and the write value should always be 1 12 PH6MD 1 R W PH6 Mode 0 SCIF1 MMCIF module 1 Port output 11 10 PH5MD1 PH5MD0 1 1 R W R W PH5 Mode 00 SCIF1 MMCIF module 01 Po...

Page 1125: ... 11 Port input pull up MOS On 1 0 PH0MD1 PH0MD0 1 1 R W R W PH0 Mode 00 SCIF0 HSPI FLCTL module 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On Note Can be selectable the modules that use this pin by on chip module select register 28 2 9 Port J Control Register PJCR PJCR is a 16 bit readable writable register that selects the pin function and input pull up MOS control 0 1...

Page 1126: ...ll up MOS Off 11 Port input pull up MOS On 7 6 PJ3MD1 PJ3MD0 1 1 R W R W PJ3 Mode 00 SIOF HAC SSI module 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 5 4 PJ2MD1 PJ2MD0 1 1 R W R W PJ2 Mode 00 SIOF HAC module 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 3 2 PJ1MD1 PJ1MD0 1 1 R W R W PJ1 Mode 00 SIOF HAC SSI module 01 Port output 10 Port inpu...

Page 1127: ...W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 15 14 PK7MD1 PK7MD0 1 1 R W R W PK7 Mode 00 DMAC module 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 13 12 PK6MD1 PK6MD0 1 1 R W R W PK6 Mode 00 DMAC module 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 11 10 PK5MD1 PK5MD0 1 1 R W R W PK5 M...

Page 1128: ...R W R W PK2 Mode 00 DMAC INTC H UDI module 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 3 1 R W Reserved This bit is always read as 1 and the write value should always be 1 2 PK1MD0 1 R W PK1 Mode 0 DMAC LBSC H UDI module 1 Port output 1 1 R W Reserved This bit is always read as 1 and the write value should always be 1 0 PK0MD 1 R W PK0 Mode 0 DMAC LBSC H UDI module 1 ...

Page 1129: ...Bit Name Initial value R W Description 15 to 7 All 1 R W Reserved These bits are always read as 1 and the write value should always be 1 6 PL3MD 1 R W PL3 Mode 0 DMAC module 1 Port output 5 1 R W Reserved This bit is always read as 1 and the write value should always be 1 4 PL2MD 1 R W PL2 Mode 0 DMAC module 1 Port output 3 1 R W Reserved This bit is always read as 1 and the write value should alw...

Page 1130: ...D0 PL0 MD1 PL1 MD0 PL1 MD1 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 15 to 4 All 1 R W Reserved These bits are always read as 1 and the write value should always be 1 3 2 PM1MD1 PM1MD0 1 1 R W R W PM1 Mode 00 LBSC module 01 Port output 10 Port input pull up MOS Off 11 Port input pull up MOS On 1 0 PM0MD1 PM0MD0 ...

Page 1131: ... register will be read out When the pin functions as a general input port if the port is read the status of the corresponding pin will be read out 28 2 14 Port B Data Register PBDR PBDR is an 8 bit readable writable register that stores port B data 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 PB0DT PB1DT PB2DT PB3DT PB4DT PB5DT PB6DT PB7DT R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Init...

Page 1132: ... register will be read out When the pin functions as a general input port if the port is read the status of the corresponding pin will be read out 28 2 16 Port D Data Register PDDR PDDR is an 8 bit readable writable register that stores port D data 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 PD0DT PD1DT PD2DT PD3DT PD4DT PD5DT PD6DT PD7DT R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Init...

Page 1133: ...al value R W Description 7 0 R W Reserved This bit is always read as 0 and the write value should always be 0 6 PE6DT Pin input R W 5 PE5DT 0 R W 4 PE4DT 0 R W 3 PE3DT 0 R W 2 PE2DT 0 R W 1 PE1DT 0 R W 0 PE0DT 0 R W These bits store output data of a pin which is used as a general output port When the pin functions as a general output port if the port is read the value of this corresponding registe...

Page 1134: ... register will be read out When the pin functions as a general input port if the port is read the status of the corresponding pin will be read out 28 2 19 Port G Data Register PGDR PGDR is an 8 bit readable writable register that stores port G data 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 PG0DT PG1DT PG2DT PG3DT PG4DT PG5DT PG6DT PG7DT R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Init...

Page 1135: ...eneral input port if the port is read the status of the corresponding pin will be read out However Bit 6 and 3 are exclusively used as output ports 28 2 21 Port J Data Register PJDR PJDR is an 8 bit readable writable register that stores port J data 0 1 2 3 4 5 6 7 0 0 PJ0DT PJ1DT PJ2DT PJ3DT PJ4DT PJ5DT R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Descripti...

Page 1136: ...ort is read the corresponding value of this register will be read out When the pin functions as a general input port if the port is read the status of the corresponding pin will be read out However Bit 0 is exclusively used as an output port 28 2 23 Port L Data Register PLDR PLDR is an 8 bit readable writable register that stores port L data 0 1 2 3 4 5 6 7 0 0 0 0 0 0 0 0 PL0DT PL1DT PL2DT PL3DT ...

Page 1137: ...s a general output port When the pin functions as a general output port if the port is read the corresponding value of this register will be read out When the pin functions as a general input port if the port is read the status of the corresponding pin will be read out 28 2 25 Port E Pull Up Control Register PEPUPR PEPUPR is an 8 bit readable writable register that individually controls the pull u...

Page 1138: ...y controls the pull up for this port Each bit of this register corresponds to port H PH7 to PH0 and when these pins are set to the on chip modules the pull up control is performed individually However if these pins are set to the GPIO in the PHCR the setting in this register is invalid 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 PH0 PUPR PH1 PUPR PH2 PUPR PH3 PUPR PH4 PUPR PH5 PUPR PH6 PUPR PH7 PUPR R W R W R...

Page 1139: ...vidually However if these pins are set to the GPIO in the PJCR the setting in this register is invalid 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 PJ0 PUPR PJ1 PUPR PJ2 PUPR PJ3 PUPR PJ4 PUPR PJ5 PUPR R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 7 6 All 1 R W Reserved These bits are always read as 1 and the write value should always be 1 5 PJ5PUPR 1 R W 4 PJ...

Page 1140: ...trol is performed individually However if these pins are set to the GPIO in the PKCR the setting in this register is invalid 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 PK0 PUPR PK1 PUPR PK2 PUPR PK3 PUPR PK4 PUPR PK5 PUPR PK6 PUPR PK7 PUPR R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 7 PK7PUPR 1 R W 6 PK6PUPR 1 R W 5 PK5PUPR 1 R W 4 PK4PUPR 1 R W 3 PK3PUPR ...

Page 1141: ...ip modules the pull up control is performed individually However if these pins are set to the GPIO in the PMCR the setting in this register is invalid 0 1 2 3 4 5 6 7 1 1 1 1 1 1 1 1 PM0 PUPR PM1 PUPR R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 7 to 2 All 1 R W Reserved These bits are always read as 1 and the write value should always be 1 1 PM1...

Page 1142: ... 1 1 1 1 1 1 1 1 1 1 1 1 1 CTR0 PUP CTR1 PUP RDY PUP R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Bit Name Initial value R W Description 15 to 3 All 1 R W Reserved These bits are always read as 1 and the write value should always be 1 2 RDYPUP 1 R W Controls pull up of RDY 0 RDY pull up off 1 RDY pull up on 1 CTR1PUP 1 R W Controls pull up of CMT_CTR1 0...

Page 1143: ... value R W Bit Bit Name Initial value R W Description 15 to 12 All 1 R W Reserved These bits are always read as 1 and the write value should always be 1 11 FD3PUP 1 R W Controls pull up of FD3 0 FD3 pull up off 1 FD3 pull up on 10 FD2PUP 1 R W Controls pull up of FD2 0 FD2 pull up off 1 FD2 pull up on 9 FD1PUP 1 R W Controls pull up of FD1 0 FD1 pull up off 1 FD1 pull up on 8 FD0PUP 1 R W Controls...

Page 1144: ...For details of pin multiplexing see table 28 1 Multiplexed Pins Controlled by Port Control Registers This register is valid only when on chip modules are selected by PECR PE6 PHCR PJCR or PKCR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 15 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OMSEL 0 OMSEL 1 OMSEL 2 OMSEL 3 OMSEL 4 OMSEL 5 OMSEL 6 OMSEL 8 OMSEL 9 OMSEL 10 OMSEL 11 OMSEL 12 OMSEL 13 OMSEL 14 R W R W R W R W R W ...

Page 1145: ...H UDI INTC 1 FLCTL 11 10 OMSEL11 OMSEL10 0 0 R W R W Out of the modules SCIF0 HSPI PCIC and FLCTL select the one using the pins SCIF0_SCK HSPI_CLK FRE SCIF0_TXD HSPI_TX FWE MODE8 SCIF0_RXD HSPI_RX FRB SCIF0_CTS INTD FCLE and SCIF0_RTS HSPI_CE FSE 00 SCIF0 01 HSPI PCIC 10 FLCTL 11 SCIF0 PCIC Note Cannot use modem control pin SCIF0_CTS this pin is used by PCIC and SCIF0_RTS pin should be pulled up b...

Page 1146: ... Out of the modules DMAC PCIC and H UDI select the one using the pins DREQ3 INTC AUDATA1 and DREQ2 INTB AUDATA0 00 DMAC 01 PCIC 10 H UDI 11 Setting prohibited 3 2 OMSEL3 OMSEL2 0 0 R W R W Out of the modules DMAC INTC RESET and H UDI select the one using the pins DACK3 IRQOUT AUDATA3 and DACK2 MRESETOUT AUDATA2 00 DMAC 01 INTC RESET 10 H UDI 11 Setting prohibited 1 0 OMSEL1 OMSEL0 1 1 R W R W Out ...

Page 1147: ...onding two bits in port control register PACR to PMCR Then for each output port the settings of port pull up control register PEPUPR PHPUPR PJPUPR PKPUPR and PMPUPR and on chip module select register OMSELR are invalid Figure 28 1 shows an example of port data output timing Setting the output data to port data register and then the port outputs the data after one peripheral clock Pck output data s...

Page 1148: ... The input data to each port can be read out from the corresponding bit in port data register Then for each input port the settings of port pull up control register PEPUPR PHPUPR PJPUPR PKPUPR and PMPUPR and on chip module select register OMSELR are invalid Figure 28 2 shows an example of port data input timing The input data from each port can be read out from corresponding port data register aft...

Page 1149: ...orresponding port is input or input output port it is necessary for each port to set the pull up MOS by setting port pull up control register PEPUPR PHPUPR PJPUPR PKPUPR and PMPUPR Write B 0 when pull up MOS is off or B 1 when pull up MOS is on to the corresponding bit For an output port the pull up MOS is off regardless of the settings of the port pull up control register After that write B 00 to...

Page 1150: ...Section 28 General Purpose I O GPIO Rev 1 00 Dec 13 2005 Page 1100 of 1286 REJ09B0158 0100 ...

Page 1151: ...reak Sequential break involves two cases such that the channel 0 break condition is satisfied in a certain bus cycle and then the channel 1 break condition is satisfied in a different bus cycle and vice versa Address When 40 bits containing ASID and 32 bit address are compared with the specified value all the ASID bits can be compared or masked 32 bit address can be masked bit by bit allowing the ...

Page 1152: ...BR0 CRR0 CAR0 CAMR0 CBR1 CRR1 CAR1 CAMR1 CDR1 CDMR1 CETR1 CCMFR CBCR SAB SDB Legend ASID comparator ASID comparator ASID Match condition setting register 0 Match operation setting register 0 Match address setting register 0 Match address mask setting register 0 Match condition setting register 1 Match operation setting register 1 Match address setting register 1 Match address mask setting register...

Page 1153: ... 1 CBR1 R W H FF200020 H 1F200020 32 Match operation setting register 1 CRR1 R W H FF200024 H 1F200024 32 Match address setting register 1 CAR1 R W H FF200028 H 1F200028 32 Match address mask setting register 1 CAMR1 R W H FF20002C H 1F20002C 32 Match data setting register 1 CDR1 R W H FF200030 H 1F200030 32 Match data mask setting register 1 CDMR1 R W H FF200034 H 1F200034 32 Execution count brea...

Page 1154: ...1 Undefined Retained Retained Match data setting register 1 CDR1 Undefined Retained Retained Match data mask setting register 1 CDMR1 Undefined Retained Retained Execution count break register 1 CETR1 Undefined Retained Retained Channel match flag register CCMFR H 00000000 Retained Retained Break control register CBCR H 00000000 Retained Retained The access size must be the same as the control reg...

Page 1155: ... 0 0 0 0 0 0 0 0 0 MFE AIE MFI AIV SZ CD ID RW CE R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R W R W R W R R R R R W R W R W R W R R W R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 MFE 0 R W Match Flag Enable Specifies whether or not to include the match ...

Page 1156: ...bits are 000000 in the condition of CCRMF MF0 0 23 to 16 AIV All 0 R W ASID Specify Specifies the ASID value to be included in the match conditions 15 0 R Reserved This bit is always read as 0 The write value should always be 0 14 to 12 SZ All 0 R W Operand Size Select Specifies the operand size to be included in the match conditions This bit is valid only when the operand access cycle is specifie...

Page 1157: ...e 3 0 R Reserved This bit is always read as 0 The write value should always be 0 2 1 RW All 0 R W Bus Command Select Specifies the read write cycle as the match condition This bit is valid only when the operand access cycle is specified as a match condition 00 Read cycle or write cycle 01 Read cycle 10 Write cycle 11 Read cycle or write cycle 0 CE 0 R W Channel Enable Validates invalidates the cha...

Page 1158: ...match flag is not included in the match conditions thus not checked 1 The match flag is included in the match conditions 30 AIE 0 R W ASID Enable Specifies whether or not to include the ASID specified by the AIV bit of this register in the match conditions 0 The ASID is not included in the match conditions thus not checked 1 The ASID is included in the match conditions 29 to 24 MFI 100000 R W Matc...

Page 1159: ... operand size specifies the match condition 1 001 Byte access 010 Word access 011 Longword access 100 Quadword access 2 Others Reserved setting prohibited 11 ETBE 0 R W Execution Count Value Enable Specifies whether or not to include the execution count value in the match conditions If this bit is 1 and the match condition satisfaction count matches the value specified by the CETR1 register the op...

Page 1160: ...on 00 Read cycle or write cycle 01 Read cycle 10 Write cycle 11 Read cycle or write cycle 0 CE 0 R W Channel Enable Validates invalidates the channel If this bit is 0 all the other bits in this register are invalid 0 Invalidates the channel 1 Validates the channel Notes 1 If the data value is included in the match conditions be sure to specify the operand size 2 If the quadword access is specified...

Page 1161: ... R R R R R R R R R R R R R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 14 All 0 R Reserved These bits are always read as 0 The write value should always be 0 13 1 R Reserved This bit is always read as 1 The write value should always be 1 12 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 PCB 0 R W PC ...

Page 1162: ...e value should always be 0 13 1 R Reserved This bit is always read as 1 The write value should always be 1 12 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 PCB 0 R W PC Break Select Specifies either before or after instruction execution as the break timing for the instruction fetch cycle This bit is invalid for breaks other than ones for the instruction...

Page 1163: ...l value R W Bit Bit Name Initial Value R W Description 31 to 0 CA Undefined R W Compare Address Specifies the address to be included in the break conditions When the operand bus has been specified using the CBR0 register specify the SAB address in CA 31 0 CAR1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CA CA R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8...

Page 1164: ... R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 0 CAM Undefined R W Compare Address Mask Specifies the bits to be masked among the address bits which are specified using the CAR0 register Set the bits to be masked to 1 0 Address bits CA n are included in the break condition 1 Address bits ...

Page 1165: ...ch Data Setting Register 1 CDR1 CDR1 is a readable writable 32 bit register which specifies the data value to be included in the break conditions for channel 1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CD CD R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R ...

Page 1166: ...n the match conditions the upper and lower 32 bits of 64 bit data are each compared with the contents of both the match data setting register and match data mask setting register 29 2 6 Match Data Mask Setting Register 1 CDMR1 CDMR1 is a readable writable 32 bit register which specifies the bits to be masked among the data value bits specified using the match data setting register Set the bits to ...

Page 1167: ...s decremented by one every time the channel is hit When the channel is hit after the register value reaches H 001 a break occurs 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CET R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 R R R R R W R W R W R W R W R W R W R W R W R W R W R W Bit Initial value R W Bit Initial value R W Bit Bit N...

Page 1168: ...8 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MF1 MF0 R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R W R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 2 All 0 R Reserved These bits are always read as 0 The write value should always be 0 1 MF1...

Page 1169: ...0 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 UBDE R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R W Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Description 31 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 UBDE 0 R W User Break Debugging ...

Page 1170: ...sed in contrast to address All types of operand access are classified into read or write access Special care must be taken in using the following instructions PREF OCBP and OCBWB Instructions for a read access MOVCA L and OCBI Instructions for a write access TAS B Instruction for a single read access or a single write access The operand access accompanying the PREF OCBP OCBWB and OCBI instructions...

Page 1171: ...atch condition is satisfied as a result of fetching the instruction using the match operation setting register CRR0 or CRR1 After having set all the bits in the match condition setting register except the CE bit and the other necessary registers set the CE bit and read the match condition setting register again This ensures that the set values in the control registers are valid for the subsequent ...

Page 1172: ... break is requested when the instruction is fetched and determined to be executed Therefore this function cannot be used for the instructions which are fetched through overrun i e the instructions fetched during branching or making transition to the interrupt routine but not executed For priorities of pre instruction execution break and the other exceptions refer to section 5 Exception Handling If...

Page 1173: ...e following access cycles assuming that all the other conditions are satisfied Longword access to address H 00001000 Word access to address H 00001002 Byte access to address H 00001003 2 When the data value is included in the channel 1 match conditions If the data value is included in the match conditions be sure to select the quadword longword word or byte as the operand size using the operand si...

Page 1174: ...Sequential Break 1 Sequential break conditions can be specified by setting the MFE and MFI bits in the match condition setting registers CBR0 and CBR1 Sequential break involves two cases such that channel 0 break condition is satisfied then channel 1 break condition is satisfied and vice versa To use the sequential break function clear the MFE bit of the match condition setting register and the BI...

Page 1175: ...equence Instruction B is 0 or one instruction after instruction A Sequential operation is not guaranteed Instruction B is two or more instructions after instruction A Sequential operation is guaranteed When the match condition is satisfied at the operand access cycle for the first channel in the sequence whereas the match condition is satisfied at the instruction fetch cycle for the second channel...

Page 1176: ...ied for the delayed branch instruction or its delayed slot these instructions are executed and the address of the branch destination is saved in the SPC When the operand access address only is specified as the match condition The address of the instruction immediately after the instruction which has satisfied the break conditions is saved in the SPC The instruction which has satisfied the match co...

Page 1177: ...dress indicated by the VBR offset Figure 29 2 shows the flowchart of the user break debugging support function SPC PC SSR SR SR BL B 1 SR MD B 1 SR RB B 1 Exception interrupt is generated Exception Exception interrupt trap Trap Interrupt PC H A000 0000 PC VBR vector offset Execute RTE instruction PC SPC SR SSR SGR R15 PC DBR Debugging program R15 SGR STC instruction Reset exception CBCR UBDE 1 use...

Page 1178: ...ction fetch before executing instruction ASID data values and execution count are not included in the conditions With the above settings the user break occurs after executing the instruction at address H 00000404 or before executing the instruction at address H 00008010 to H 00008016 Example 1 2 Register settings CBR0 H 40800013 CRR0 H 00002000 CAR0 H 00037226 CAMR0 H 00000000 CBR1 H C0700013 CRR1...

Page 1179: ...unt H 00000000 Bus cycle Instruction fetch before executing the instruction ASID data values and execution count are not included in the conditions With the above settings the user break occurs for channel 0 before executing the instruction at address H 00027128 No user break occurs for channel 1 since the instruction fetch is executed only at even addresses Example 1 4 Register settings CBR0 H 40...

Page 1180: ... Execution count H 00000005 Bus cycle Instruction fetch before executing the instruction Execution count 5 ASID and data values are not included in the conditions With the above settings the user break occurs for channel 0 before executing the instruction at address H 00000500 The user break occurs for channel 1 after executing the instruction at address H 00001000 four times before executing the ...

Page 1181: ...0000000 CETR1 H 00000000 CBCR H 00000000 Specified conditions Independent for channels 0 and 1 Channel 0 Address H 00123456 Address mask H 00000000 ASID H 80 Bus cycle Operand bus operand access and read operand size is not included in the conditions Channel 1 Address H 000ABCDE Address mask H 000000FF ASID H 70 Data H 0000A512 Data mask H 00000000 Execution count H 00000000 Bus cycle Operand bus ...

Page 1182: ...isters is not necessary At only last updating the UBC register execute one of these methods The PCB bit of the CRR0 and CRR1 registers is valid only when the instruction fetch is specified as the match condition If the sequential break conditions are set the sequential break conditions are satisfied when the conditions for the first and second channels in the sequence are satisfied in this order T...

Page 1183: ...d independently for channels 0 and 1 resulting in identical SPC values for both of the breaks the user break occurs only once However the condition match flags are set for both channels For example Instruction at address 110 post instruction execution break for instruction fetch for channel 0 SPC 112 CCMFR MF0 1 Instruction at address 112 pre instruction execution break for instruction fetch for c...

Page 1184: ...Section 29 User Break Controller UBC Rev 1 00 Dec 13 2005 Page 1134 of 1286 REJ09B0158 0100 ...

Page 1185: ...re multiplexed with on chip modules And the H UDI has one chip mode setting pin MPMD The H UDI has two TAP controller blocks one is for the boundary scan test and another is H UDI function except the boundary scan test The H UDI initial state is for the boundary scan after power on or TRST asserted It is necessary to set H UDI switchover command to use the H UDI function And the CPU cannot access ...

Page 1186: ...2 FD2 AUDATA1 FD1 AUDATA0 FD0 DRAK3 CE2B AUDSYNC DRAK2 CE2A AUDCK DACK3 IRQOUT AUDATA3 DACK2 MRESETOUT AUDATA2 DREQ3 INTC AUDATA1 DREQ2 INTB AUDATA0 Note These pins are multiplexed with on chip module s To use the H UDI AUD function select the H UDI module by OMSELR in GPIO Legend OMSELR On chip module select register SDBPR Bypass register SDBSR Boundary scan register SDINT Interrupt source regist...

Page 1187: ... should be asserted for a given period regardless of whether or not the JTAG function is used which differs from the JTAG standard Fixed to ground or connected to the PRESET pin 3 TDI Data input Input Data Input Data is sent to the H UDI by changing this signal in synchronization with the TCK signal Open 1 TDO Data output Output Data Output Data is read from the H UDI in synchronization with the T...

Page 1188: ...pt functions Assertion of TRST for example at power on reset activates the boundary scan TAP controller and enables the boundary scan function prescribed in the JTAG standards Executing a switchover command to the H UDI allows usage of the H UDI reset and H UDI interrupts This LSI however has the following limitations Clock related pins EXTAL XTAL EXTAL2 and XTAL2 are out of the scope of the bound...

Page 1189: ...t1 IR Update IR Run Test Idle Test Logic Reset Select DR Select IR Capture IR Shift IR Test Logic Reset Run Test Idle Test Logic Reset Run Test Idle Shift IR TCK TMS TRST TDI H UDI Run Test Idle TRST is asserted H UDI select command is input to boundary scan TAP controller H UDI is used TRST is asserted Boundary scan TAP controller External pins H UDI selection Status Status H UDI select command B...

Page 1190: ...g the TLB 2 The low level of the TRST pin or the Test Logic Reset state of the TAP controller initializes to these values Table 30 4 Register Configuration 2 H UDI Side Register Name Abbrev R W Size Initial Value 1 Instruction register SDIR R W 32 H FFFF FFFD fixed value 2 Interrupt source register SDINT W 3 32 H 0000 0000 Boundary scan register SDBSR Bypass register SDBPR R W 1 Undefined Note 1 T...

Page 1191: ...guaranteed when a reserved command is set to this register TI Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 1 R R R R R R R R R R R R R R R R Bit Bit Name Initial Value R W Description 15 to 8 TI 0000 1110 R Test Instruction Bits 7 to 0 0110 xxxx H UDI reset negate 0111 xxxx H UDI reset assert 101x xxxx H UDI interrupt 0000 1110 Initial state Other than ...

Page 1192: ...y TRST or in the Test Logic Reset state INTREQ Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R R R R R R R R R W Bit Bit Name Initial Value R W Description 15 to 1 All 0 R Reserved These bits are always read as 0 The write value should always be 0 0 INTREQ 0 R W Interrupt Request Indicates whether or not an interrupt by an H UDI interrupt...

Page 1193: ...AUDATA3 Control 501 DREQ0 Input 522 DACK3 IRQOUT AUDATA3 Input 500 DRAK3 CE2B AUDSYNC Output 521 DACK2 MRESETOUT AUDATA2 Output 499 DRAK3 CE2B AUDSYNC Control 520 DACK2 MRESETOUT AUDATA2 Control 498 DRAK3 CE2B AUDSYNC Input 519 DACK2 MRESETOUT AUDATA2 Input 497 DRAK2 CE2A AUDCK Output 518 DACK1 MODE1 Output 496 DRAK2 CE2A AUDCK Control 517 DACK1 MODE1 Control 495 DRAK2 CE2A AUDCK Input 516 DACK1 M...

Page 1194: ...71 A24 Input 438 A11 Input 470 A19 Output 437 A10 Output 469 A19 Control 436 A10 Control 468 A19 Input 435 A10 Input 467 A20 Output 434 A9 Output 466 A20 Control 433 A9 Control 465 A20 Input 432 A9 Input 464 A21 Output 431 A8 Output 463 A21 Control 430 A8 Control 462 A21 Input 429 A8 Input 461 A16 Output 428 A7 Output 460 A16 Control 427 A7 Control 459 A16 Input 426 A7 Input 458 A17 Output 425 A6 ...

Page 1195: ...put 404 D31 Output 371 D21 Output 403 D31 Control 370 D21 Control 402 D31 Input 369 D21 Input 401 D30 Output 368 D20 Output 400 D30 Control 367 D20 Control 399 D30 Input 366 D20 Input 398 D29 Output 365 D19 Output 397 D29 Control 364 D19 Control 396 D29 Input 363 D19 Input 395 D28 Output 362 D18 Output 394 D28 Control 361 D18 Control 393 D28 Input 360 D18 Input 392 D27 Output 359 D17 Output 391 D2...

Page 1196: ...8 D11 Output 305 D3 Output 337 D11 Control 304 D3 Control 336 D11 Input 303 D3 Input 335 D10 Output 302 WE0 REG Output 334 D10 Control 301 WE0 REG Control 333 D10 Input 300 WE0 REG Input 332 D9 Output 299 D0 Output 331 D9 Control 298 D0 Control 330 D9 Input 297 D0 Input 329 WE1 Output 296 BREQ Output 328 WE1 Control 295 BREQ Control 327 WE1 Input 294 BREQ Input 326 D7 Output 293 BACK Output 325 D7...

Page 1197: ...put 239 GNT2 Output 271 CS5 Control 238 GNT2 Control 270 CS5 Input 237 GNT2 Input 269 CS6 Output 236 GNT1 Output 268 CS6 Control 235 GNT1 Control 267 CS6 Input 234 GNT1 Input 266 CLKOUT Control 233 AD31 Output 265 CLKOUT Output 232 AD31 Control 264 CS0 Output 231 AD31 Input 263 CS0 Control 230 REQ3 Output 262 CS0 Input 229 REQ3 Control 261 CS1 Output 228 REQ3 Input 260 CS1 Control 227 AD30 Output ...

Page 1198: ... 173 IRDY Output 205 AD25 Control 172 IRDY Control 204 AD25 Input 171 IRDY Input 203 IDSEL Output 170 CBE2 Output 202 IDSEL Control 169 CBE2 Control 201 IDSEL Input 168 CBE2 Input 200 AD24 Output 167 TRDY Output 199 AD24 Control 166 TRDY Control 198 AD24 Input 165 TRDY Input 197 AD21 Output 164 PCIFRAME Output 196 AD21 Control 163 PCIFRAME Control 195 AD21 Input 162 PCIFRAME Input 194 AD23 Output ...

Page 1199: ...D2 Input 140 SERR Output 107 AD8 Output 139 SERR Control 106 AD8 Control 138 SERR Input 105 AD8 Input 137 AD11 Output 104 AD7 Output 136 AD11 Control 103 AD7 Control 135 AD11 Input 102 AD7 Input 134 AD9 Output 101 AD0 Output 133 AD9 Control 100 AD0 Control 132 AD9 Input 99 AD0 Input 131 CBE1 Output 98 AD5 Output 130 CBE1 Control 97 AD5 Control 129 CBE1 Input 96 AD5 Input 128 AD14 Output 95 AD3 Out...

Page 1200: ...CIF0_RTS HSPI_CS FSE Output 73 IRQ IRL4 FD4 MODE3 Control 46 SCIF0_RTS HSPI_CS FSE Control 72 IRQ IRL4 FD4 MODE3 Input 45 SCIF0_RTS HSPI_CS FSE Input 71 IRQ IRL5 FD5 MODE4 Output 44 SCIF1_SCK MCCMD Output 70 IRQ IRL5 FD5 MODE4 Control 43 SCIF1_SCK MCCMD Control 69 IRQ IRL5 FD5 MODE4 Input 42 SCIF1_SCK MCCMD Input 68 IRQ IRL6 FD6 MODE6 Output 41 SCIF1_TXD MCCLK MODE5 Output 67 IRQ IRL6 FD6 MODE6 Co...

Page 1201: ...utput 9 AUDATA3 FD3 Input 25 SIOF_MCLK HAC_RES Control 8 AUDCK FALE Output 24 SIOF_MCLK HAC_RES Input 7 AUDCK FALE Control 23 SIOF_SCK HAC_BITCLK SSI_CLK Output 6 AUDCK FALE Input 22 SIOF_SCK HAC_BITCLK SSI_CLK Control 5 AUDSYNC FCE Output 21 SIOF_SCK HAC_BITCLK SSI_CLK Input 4 AUDSYNC FCE Control 20 AUDATA0 FD0 Output 3 AUDSYNC FCE Input 19 AUDATA0 FD0 Control 2 ASEBRK BRKACK Output 18 AUDATA0 FD...

Page 1202: ...TCK signal and shifted at the falling edge of the TCK signal The TDO value is changed at the falling edge of the TCK signal The TDO signal is in a Hi Z state other than in the Shift DR or Shift IR state A transition to the Test Logic Reset by clearing TRST to 0 is performed asynchronously with the TCK signal Test Logic Reset Capture DR Shift DR Exit1 DR Pause DR Exit2 DR Update DR Select DR Scan R...

Page 1203: ...set 30 5 3 H UDI Interrupt The H UDI interrupt function generates an interrupt by setting the appropriate command in SDIR from the H UDI An H UDI interrupt is a general exception interrupt operation resulting in branching to the VBR address The H UDI returns from the interrupt handling routine with a RTE instruction When an H UDI interrupt occurs the exception code H 600 is stored in the interrupt...

Page 1204: ... is set it will be changed only by an assertion of the TRST signal making the TAP controller Test Logic Reset state or writing other commands from the H UDI The H UDI is used for emulator connection Therefore H UDI functions cannot be used when using an emulator An H UDI interrupt or an H UDI reset can be accepted to cancel sleep mode ...

Page 1205: ... maximum ratings are exceeded 2 The LSI may be permanently damaged if any of the VSS pins are not connected to GND 3 The upper limit of the input voltage must not exceed the power supply voltage 4 R8A77800ADBG V only code V indicates Lead Free product 5 For the powering on and powering off sequence see Appendix H Turning On and Off Power Supply 6 It is prohibited to input signals to the following ...

Page 1206: ... 2 1 15 1 25 1 35 V Normal operation sleep mode VCCQ DDR 2 3 2 5 2 7 Reference voltage DDR VREF 1 15 1 25 1 35 Normal operation sleep mode DDR backup mode Normal operation 740 1300 Ick 400MHz Sleep mode IDD 530 Normal operation 150 220 Ick 400MHz Sleep mode IDDQ 90 Bck 100MHz ΣIDD PLL 25 mA Normal operation ΣIDD DLL 400 µA DDR Normal operation 530 mA DDRck 160MHz DDR backup mode ICCQ DDR 160 mA Su...

Page 1207: ... pins DDR VREF 0 15 VCCQ DDR 0 3 V DDR VREF 1 15 to 1 35V VCCQ DDR 2 3 to 2 7V PCICLK VDDQ 0 6 VDDQ 0 3 Other PCI pins VDDQ 0 5 VDDQ 0 3 Other input pins VIH 2 VDDQ 0 3 VDDQ 3 0 to 3 6V PRESET NMI TRST ASEBRK BRKACK SCIF0_RTS IRQ IRL7 FD7 IRQ IRL6 FD6 MODE6 IRQ IRL5 FD5 MODE4 IRQ IRL4 FD4 MODE3 IRQ IRL3 IRQ IRL2 IRQ IRL1 IRQ IRL0 0 3 VDDQ 0 1 VDDQ 3 0 to 3 6 V DDR pins 0 3 DDR VREF 0 15 DDR VREF 1...

Page 1208: ... 1 µA VIN 0 5 VDDQ 0 5V PCI pins 2 4 VDDQ 3 0 to 3 6V IOH 4mA DDR pins 1 84 VCCQ DDR 2 3V IOH 7 6mA Other output pins VOH 2 4 VDDQ 3 0 to 3 6V IOH 2mA PCI pins 0 55 VDDQ 3 0 to 3 6V IOL 4mA DDR pins 0 54 VCCQ DDR 2 3V IOL 7 6mA Output voltage Other output pins VOL 0 55 V VDDQ 3 0 to 3 6V IOL 2mA Pull up resistance All pins Rpull 20 60 180 kΩ DDR pins 5 Pin capacitance Other pins CL 10 pF Note The ...

Page 1209: ...ble output high current per pin PCI pins 4 Permissible output high current per pin other than DDR and PCI pins IOH 2 Permissible output high current total Σ IOH 40 mA Note To protect chip reliability do not exceed the output current values in table 31 3 31 3 AC Characteristics In principle this LSI s input should be synchronous Unless specified otherwise ensure that the setup time and hold times f...

Page 1210: ...UT clock output high level pulse width tCLKOUTH1 1 ns 31 2 CLKOUT clock output rise time tCLKOUTr 3 ns 31 2 CLKOUT clock output fall time tCLKOUTf 3 ns 31 2 CLKOUT clock output low level pulse width tCLKOUTL2 3 ns 31 3 CLKOUT clock output high level pulse width tCLKOUTH2 3 ns 31 3 Power on oscillation settling time tOSC1 18 ms 31 4 Power on oscillation settling time mode setting tOSCMODE 18 ms 31 ...

Page 1211: ...H VIH VIL VIL EXTAL input VIH 1 2VDDQ Note When the clock is input from the EXTAL pin Figure 31 1 EXTAL Clock Input Timing tCLKOUTcyc tCLKOUTH1 CLKOUT tCLKOUTL1 tCKOr tCKOf 1 2VDDQ VOH VOH VOL VOL VOH 1 2VDDQ Figure 31 2 CLKOUT Clock Output Timing 1 tCLKOUTH2 CLKOUT 1 5V 1 5V 1 5V tCLKOUTL2 Figure 31 3 CLKOUT Clock Output Timing 2 ...

Page 1212: ... Internal clock VDD MODEn PRESET TRST tOSC1 VDD min tMDRH tOSCMODE tTRSTRH Stable oscillation tRESW CLKOUT Note Oscillation settling time when on chip resonator is used Figure 31 4 Power On Oscillation Settling Time tMODERS tMODERH tPRf tPRr PRESET MODEn Figure 31 5 MODE pins Setup Hold Timing ...

Page 1213: ...al Timing VDDQ 3 0 to 3 6V VDD 1 25V Ta 20 to 75 C 40 to 85 C CL 30pF Item Symbol Min Max Unit Figure BREQ setup time tBREQS 2 5 ns 31 7 BREQ hold time tBREQH 1 5 ns 31 7 BACK delay time tBACKD 6 ns 31 7 Bus three state delay time tBOFF1 12 ns 31 7 Bus buffer on time tBON1 12 ns 31 7 CLKOUT A 25 0 CSn BS R W CE2A CE2B WE RD BREQ BACK tBREQH tBREQS tBREQH tBACKD tBACKD tBOFF1 tBON1 tBREQS Figure 31...

Page 1214: ...RWD 1 5 6 ns RD delay time tRSD 1 5 6 ns Read data setup time tRDS 2 5 ns Read data hold time tRDH 1 5 ns WE delay time falling edge tWEDF 6 ns Relative to CLKOUT falling edge WE delay time tWED1 1 5 6 ns Write data delay time tWDD 1 5 6 ns RDY setup time tRDYS 2 5 ns RDY hold time tRDYH 1 5 ns FRAME delay time tFMD 1 5 6 ns MPX IOIS16 setup time tIO16S 2 5 ns PCMCIA IOIS16 hold time tIO16H 1 5 ns...

Page 1215: ...age 1165 of 1286 REJ09B0158 0100 T1 tAD tAD T2 CLKOUT A25 A0 CSn R W RD D31 D0 read D31 D0 write BS DACK tWDD tWDD tWDD tRDH tRDS tCSD tCSD tRWD tRWD tRSD tRSD tRSD tWED1 tWEDF tWEDF tBSD tBSD tDACD tDACD RDY WE Figure 31 8 SRAM Bus Cycle Basic Bus Cycle No Wait ...

Page 1216: ...286 REJ09B0158 0100 tWDD tWDD tWDD CLKOUT A25 A0 CSn R W RD D31 D0 read D31 D0 write BS DACK RDY WE T1 tAD Tw T2 tAD tRDH tRDS tCSD tRWD tRWD tCSD tRSD tRSD tRSD tWED1 tWEDF tWEDF tRDYH tRDYS tBSD tBSD tDACD tDACD Figure 31 9 SRAM Bus Cycle Basic Bus Cycle One Internal Wait ...

Page 1217: ...00 tWDD tWDD tWDD CLKOUT A25 A0 CSn R W RD D31 D0 read D31 D0 write BS DACK RDY WE T1 tAD Tw Twe T2 tAD tRDH tRDS tCSD tRWD tRWD tCSD tRSD tRSD tRSD tWED1 tWEDF tWEDF tRDYH tRDYS tRDYH tRDYS tBSD tBSD tDACD tDACD Figure 31 10 SRAM Bus Cycle Basic Bus Cycle One Internal Wait One External Wait ...

Page 1218: ...DD tWDD tWDD TS1 tAD T1 T2 TH1 tAD tRDH tRDS tCSD tRWD tRWD tCSD tRSD tRSD tRSD tWED1 tWEDF tWEDF tBSD tBSD tDACD tDACD CLKOUT A25 A0 CSn R W RD D31 D0 read D31 D0 write BS DACK RDY WE Figure 31 11 SRAM Bus Cycle Basic Bus Cycle No Wait No Address Setup Hold Time Insertion RDS 1 RDH 0 WTS 1 WTH 1 ...

Page 1219: ... 2005 Page 1169 of 1286 REJ09B0158 0100 CLKOUT A25 A5 T1 T2 CSn R W RD D31 D0 read BS RDY A4 A0 TB2 TB1 TB2 TB1 TB2 TB1 tCSD tAD tRWD tBSD tRDS tBSD tRSD tRSD tRDH tAD tAD tCSD tRWD tRDH tRSD tRDS DACK tDACD tDACD Figure 31 12 Burst ROM Bus Cycle No Wait ...

Page 1220: ... Twb Twb Twb Twe Tw t AD t CSD t RSD t RDH t RDS t BSD t AD t RDH t RSD t RDS t AD t CSD t RDYH t RDYS t RDYH t RDYS t RDYH t RDYS t DACD t DACD t RWD t RWD CLKOUT A25 A5 CSn R W RD D31 D0 read BS RDY A4 A0 DACK Figure 31 13 Burst ROM Bus Cycle 1st Data One Internal Wait One External Wait 2nd 3rd 4th Data One Internal Wait ...

Page 1221: ... t CSD t RWD t BSD t RDS t BSD t RSD t AD TS1 TB1 TB2 t AD t RDH TB1 TB2 T2 TB1 t AD t CSD t RWD t RDH t RSD t RDS TH1 TS1 TH1 TS1 TH1 TS1 TH1 CLKOUT A25 A5 CSn R W RD D31 D0 read BS RDY A4 A0 DACK t DACD t DACD Figure 31 14 Burst ROM Bus Cycle No Wait No Address Setup Hold Time Insertion RDS 1 RDH 0 ...

Page 1222: ... Twb Twbe Twb T2 TB2 Twbe TB1 CLKOUT A25 A5 A4 A0 D31 D0 read t AD t AD t AD t RDH t RDS t RDH t RDS BS RDY DACK RD t BSD t BSD t BSD t BSD t RSD t RSD CSn t RWD t CSD t RWD t CSD t DACD t DACD t RSD R W t RDYH t RDYS t RDYH t RDYS t RDYH t RDYS t RDYH t RDYS Figure 31 15 Burst ROM Bus Cycle One Internal Wait One External Wait ...

Page 1223: ...15 D0 write BS DACK RDY WE1 tAD tAD tWDD tBSD tBSD tBSD tBSD tWDD tWDD tRWD tCSD tCSD tRWD tRSD tRSD tRSD tWEDF tWED1 tWEDF tDACD tRDH tRDS tRDYH tRDYS tRDYH tRDYS tDACD tAD tAD tWDD tWDD tWDD tRWD tCSD tCSD tRWD tRSD tRSD tRSD tWEDF tWED1 tWEDF tDACD tRDH tRDS tDACD 1 TEDx 0 TEHx 0 No Wait 2 TEDx 1 TEHx 1 One Internal Wait One External Wait A25 A0 Figure 31 16 PCMCIA Memory Bus Cycle ...

Page 1224: ... tAD tBSD tBSD tBSD tBSD tWDD tWDD tRWD tCSD tCSD tRWD tICRSD tICRSD tICWSDF tICWSDF tDACD tRDH tRDS tRDYH tRDYS tRDYH tRDYS tIO16H tIO16S tIO16H tIO16S tDACD tAD tAD tWDD tWDD tWDD tRWD tCSD tCSD tRWD tICRSD tICRSD tICRSD tICWSDF tICWSDF tICWSDF tDACD tRDH tRDS tDACD D15 D0 read D15 D0 write 1 TEDx 0 TEHx 0 No Wait 2 TEDx 1 TEHx 1 One Internal Wait One External Wait A25 A0 Figure 31 17 PCMCIA I O...

Page 1225: ...UT A25 A1 A0 CExx REG WE0 R W IORD WE2 D15 D0 read D15 D0 write BS RDY IOIS16 IOWR WE3 tBSD tBSD tAD tAD tWDD tWDD tWDD tWDD tWDD tRWD tRWD tAD tCSD tCSD tCSD tICRSD tICRSD tICRSD tICWSDF tICWSDF tICWSDF tICWSDF tICWSDF tRDH tRDS tRDYS tRDYH tIO16S tIO16H tRDYS tRDYH Figure 31 18 PCMCIA I O Bus Cycle TEDx 1 THEx 1 IW PCIW 1 One Internal Wait Dynamic Bus Sizing ...

Page 1226: ... tFMD tCSD tCSD tRDH tRDS tWDD A D0 tWDD tWDD A tWDD tRWD tRWD tWED1 tWED1 tDACD tDACD tRDYH tRDYS tRDYH tRDYS 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 1xx Burst 32 bytes D25 D0 Address 1 1st Data One Internal Wait 2 1st Data One Internal Wait One External Wait 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long...

Page 1227: ...Tmd1we Tmd1 t FMD t FMD t BSD t BSD t CSD t CSD t DACD t DACD t WED1 t WED1 D0 t RWD t RWD A t WDD t WDD t WDD 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 1xx Burst 32 bytes D25 D0 Address 1 1st Data No Wait 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 1xx Burst 32 bytes D25 D0 Address 2 1st Data One...

Page 1228: ... t BSD t BSD t CSD t CSD t RDYS t RDYH t DACD t DACD D8 t RWD t RWD A t WDD D7 D3 D1 D2 t WDD t RDH t RDS t RDYS t RDYH t RDYH 1 1st Data One Internal Wait 2nd to 8th Data No Internal Wait 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 1xx Burst 32 bytes D25 D0 Address 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Lo...

Page 1229: ...e Tmd2 Tmd3 Tmd7 Tmd8we Tmd8 t FMD t FMD t BSD t BSD t CSD t CSD t RDYS t RDYH t DACD t DACD t RWD t RWD A t WDD t WDD t WDD t RDYS t RDYH 1st data bus cycle information D31 D29 Access size 000 Byte 001 Word 2 bytes 010 Long 4 bytes 1xx Burst 32 bytes D25 D0 Address 1 No Internal Wait 2 1st Data One Internal Wait 2nd to 8th Data No Internal Wait External Wait Control 1st data bus cycle information...

Page 1230: ... BS DACK RDY A25 A0 t CSD t CSD t DACD t RDYH t RDYS t DACD t RWD t RWD T1 T2 t CSD t CSD t DACD t DACD t WED1 t RWD t RWD t RDYH t RDYS t RDYH t RDYS t AD t AD t AD t AD T1 Tw Twe T2 t RSD t RSD t RSD t RSD t RSD t RSD t RSD t RSD t WED1 t WED1 t WEDF t WED1 t WEDF t WED1 t WEDF t WED1 t CSD t CSD t DACD t BSD t BSD t BSD t BSD t BSD t BSD t DACD t RWD t RWD t RSD t AD t AD t RDH t RDS t RDH t RD...

Page 1231: ...B0158 0100 CLKOUT CSn R W RD WE D31 D0 read BS DACK RDY A25 A0 TS1 T1 T2 TH1 tRSD tRSD tWED1 tWEDF tWED1 tCSD tCSD tDACD tBSD tBSD tDACD tRWD tRWD tRSD tAD tAD tRDH tRDS Figure 31 24 Byte Control SRAM Bus Cycle Basic Read Cycle No Wait No Address Setup Hold Time Insertion RDS 1 RDH 0 ...

Page 1232: ...vel pulse width tMCLKL 0 45 0 55 tMCLK 31 25 1 0 DDR320 Address and control signal setup time to MCLK rising edge tADCTLS 1 2 ns 31 26 31 27 DDR266 1 0 DDR320 Address and control signal hold time to MCLK rising edge tADCTLH 1 2 ns 31 26 31 27 DDR266 0 75 0 75 DDR320 MCLK to MDQS skew time read tRMDQS MCLK 0 8 0 8 ns 31 26 DDR266 0 5 DDR320 MDQS MDA skew for DQS and associated MDA signals tRMDQSQ 0...

Page 1233: ... tWMDQSH 0 35 tMCLK 31 27 MDQS low level pulse width write tWMDQSL 0 35 tMCLK 31 27 0 7 DDR320 MDA and MDQM setup time to MDQS rising falling edge write tWDS 0 75 ns 31 27 DDR266 0 7 DDR320 MDA and MDQM hold time to MDQS rising falling edge write tWDH 0 75 ns 31 27 DDR266 Note tMCLK one MCLK cycle time MCLK tMCLK tMCLKL tMCLKH MCLK Figure 31 25 MCLK Output Timing ...

Page 1234: ...1 00 Dec 13 2005 Page 1184 of 1286 REJ09B0158 0100 MCLK MCLK MDQS D0 D1 D2 D3 D0 D1 D2 D3 MDQS MDA MDA CKE MCS WE MA BA MRAS MCAS tADCTLS tRMDQSQ tRMDQS MCLK Min tADCTLH tRMDQS tRMDQS MCLK Max Figure 31 26 Read Timing of DDR SDRAM 2 Burst Read ...

Page 1235: ...0 MCLK MCLK MDQS D0 D1 D2 MDA MDQM CKE MCS WE MA BA MRAS MCAS tADCTLS Write command tWDS tWDH tWMDQSS Min tADCTLH tWMDQSH tWDSS tWDSH tWDS tWDH tWDS tWDH tWMDQSL MDQS D0 D1 D2 MDA MDQM tWDS tWDH tWMDQSS Max tWMDQSH tWDSS tWDSH tWMDQSL D3 D3 Figure 31 27 Write Timing of DDR SDRAM 2 Burst Write ...

Page 1236: ...sleep mode IRQ IRL7 to IRQ IRL0 setup time tIRQS 3 5 ns 31 29 IRQ input IRQ IRL7 to IRQ IRL0 hold time tIRQH 1 5 ns 31 29 IRQ input IRQ IRL7 to IRQ IRL0 setup time tIRLS 3 5 ns 31 29 IRL input IRQ IRL7 to IRQ IRL0 hold time tIRLH 1 5 ns 31 29 IRL input GPIO interrupt setup time Port E6 E0 H1 H0 J0 K5 K4 tGPIOS 3 5 ns 31 29 GPIO interrupt input GPIO interrupt hold time Port E6 E0 H1 H0 J0 K5 K4 tGP...

Page 1237: ...trical Characteristics Rev 1 00 Dec 13 2005 Page 1187 of 1286 REJ09B0158 0100 IRQ IRL GPIO IRQOUT CLKOUT tIRQS tIRLS tGPIOS tIRQH tIRLH tGPIOH tIRQOD Figure 31 29 IRQ IRL GPIO Interrupt Input and IRQOUT Output Timing ...

Page 1238: ...ns 31 32 Output data delay time tPCIVAL 2 10 2 6 ns 31 31 Tri state drive delay time tPCION 2 10 2 6 ns 31 31 Tri state high impedance delay time tPCIOFF 2 12 2 6 ns 31 31 Input setup time tPCISU 3 3 ns 31 32 AD31 AD0 CBE3 CBE0 PAR PCIFRAME IRDY TRDY STOP LOCK DEVSEL PERR Input hold time tPCIH 1 5 1 5 ns 31 32 Output data delay time tPCIVAL 2 10 2 6 ns 31 31 Tri state drive delay time tPCION 2 10 ...

Page 1239: ...DDQ 0 5VDDQ tPCICYC PCICLK tPCIHIGH VH VH VH VL VL tPCILOW tPCIf tPCIr Figure 31 30 PCI Clock Input Timing Output delay Tri state output PCICLK tPCIVAL 0 4VDDQ 0 4VDDQ tPCION tPCIOFF Figure 31 31 Output Signal Timing Input PCICLK 0 4VDDQ 0 4VDDQ 0 4VDDQ tPCIH tPCISU Figure 31 32 Input Signal Timing ...

Page 1240: ...dule Signal Timing VDDQ 3 0 to 3 6V VDD 1 25V Ta 20 to 75 C 40 to 85 C CL 30pF Item Symbol Min Max Unit Figure Notes DREQ setup time tDRQS 2 5 ns 31 33 DREQ hold time tDRQH 1 5 ns 31 33 DRAK delay time tDRAKD 1 5 5 3 ns 31 33 DACK delay time tDACD 1 5 6 ns 31 8 etc tDRAKD tDRQH tDRQH tDRQS tDRQS CLKOUT DREQ DRAC Figure 31 33 DREQ and DRAK Timing ...

Page 1241: ...o 3 6V VDD 1 25V Ta 20 to 75 C 40 to 85 C CL 30pF Item Symbol Min Max Unit Figure Notes Timer clock pulse width High tTCLKWH 4 tPcyc 31 34 Timer clock pulse width Low tTCLKWL 4 tPcyc 31 34 Timer clock rise time tTCLKr 0 8 tPcyc 31 34 Timer clock fall time tTCLKf 0 8 tPcyc 31 34 Note tPcyc one Pck cycle tim tTCLKWH TCLK tTCLKWL tTCLKf tTCLKr Figure 31 34 TCLK Input Timing ...

Page 1242: ...30pF Item Symbol Min Max Unit Figure CMT_CTR output delay time tTMD 8 ns 31 35 CMT_CTR input setup time tTMS 5 ns 31 35 CMT_CTR input hold time tTMH 5 ns 31 35 Timer clock low level width tTMLOW 1 5 tcyc 31 36 Timer clock high level width tTMHIGH 1 5 tcyc 31 36 Note tcyc one CLKOUT cycle time tTMD tTMS tTMH CLKOUT CMT_CTR CMT_CTR Figure 31 35 CMT Timing 1 tTMHIGH tTMS tTMLOW CLKOUT CMT_CTR Figure ...

Page 1243: ...le asynchronous 4 tPcyc 31 37 Input clock cycle synchronous tScyc 6 tPcyc 31 37 Input clock pulse width tSCKW 0 4 0 6 tScyc 31 37 Input clock rise time tSCKr 0 8 tPcyc 31 37 Input clock fall time tSCKf 0 8 tPcyc 31 37 Transfer data delay time tTXD 1 5 6 ns 31 38 Receive data setup time synchronous tRXS 16 ns 31 38 Receive data hold time synchronous tRXH 16 ns 31 38 Note tPcyc one Pck cycle time tS...

Page 1244: ... 31 Electrical Characteristics Rev 1 00 Dec 13 2005 Page 1194 of 1286 REJ09B0158 0100 SCIFn_TXD SCIFn_SCK SCIFn_RXD tScyc tRXS tRXH tTXD tTXD Figure 31 38 SCIF Channel n I O Synchronous Mode Clock Timing n 0 1 ...

Page 1245: ...to 31 44 SIOF_SCK output high level width tSWHO 0 4 tSICYC ns 31 40 to 31 43 SIOF_SCK output low level width tSWLO 0 4 tSICYC ns 31 40 to 31 43 SIOF_SYNC output delay time tFSD 10 ns 31 40 to 31 43 SIOF_SCK input high level width tSWHI 0 4 tSICYC ns 31 44 SIOF_SCK input low level width tSWLI 0 4 tSICYC ns 31 44 SIOF_SYNC input setup time tFSS 10 ns 31 44 SIOF_SYNC input hold time tFSH 10 ns 31 44 ...

Page 1246: ...TDD tSRDS tSRDH tFSD SIOF_SCK output SIOF_SYNC output SIOF_TXD SIOF_RXD Figure 31 40 SIOF Transmission Reception Timing Master Mode 1 Fall Sampling tSICYC tSWHO tSWLO tFSD tSTDD tSTDD tSRDS tSRDH tFSD SIOF_SCK output SIOF_SYNC output SIOF_TXD SIOF_RXD Figure 31 41 SIOF Transmission Reception Timing Master Mode 1 Rise Sampling ...

Page 1247: ...SRDS tSRDH tFSD tFSD SIOF_SCK output SIOF_SYNC output SIOF_TXD SIOF_RXD Figure 31 42 SIOF Transmission Reception Timing Master Mode 2 Fall Sampling tSICYC tSWHO tSWLO tSTDD tSTDD tSTDD tSTDD tSRDS tSRDH tFSD tFSD SIOF_SCK output SIOF_SYNC output SIOF_TXD SIOF_RXD Figure 31 43 SIOF Transmission Reception Timing Master Mode 2 Rise Sampling ...

Page 1248: ...tics Rev 1 00 Dec 13 2005 Page 1198 of 1286 REJ09B0158 0100 tSICYC tSWLI tSWHI tFSH tSTDD tSTDD tSRDS tSRDH tFSS SIOF_SCK input SIOF_SYNC input SIOF_TXD SIOF_RXD Figure 31 44 SIOF Transmission Reception Timing Slave Mode 1 Slave Mode 2 ...

Page 1249: ...y tSPIcyc Pck 8 Hz 31 45 HSPI clock high level width tSPIHW 60 ns 31 45 HSPI clock low level width tSPILW 60 ns 31 45 HSPI_TX setup time master mode tSUSPITX 20 ns 31 45 HSPI_TX delay time master mode tDSPITX 20 ns 31 45 HSPI_TX setup time slave mode tSUSPITX 10 ns 31 45 HSPI_TX delay time slave mode tDSPITX 80 ns 31 45 HSPI_RX setup time tSUSPIRX 20 ns 31 45 HSPI_RX hold time tHLSPIRX 20 ns 31 45...

Page 1250: ...B0158 0100 CLKP 1 HSPI_CLK CLKP 0 HSPI_CLK HSPI_CS FBS 0 HSPI_TX HSPI_RX FBS 1 HSPI_TX HSPI_RX tSPIcyc tSPILW tSPIHW tCSLEAD tSUSPITX tDSPITX MSB MSB 1 MSB MSB 1 MSB 2 MSB MSB 1 MSB MSB 1 tSUSPIRX tHLSPIRX tSUSPITX tDSPITX tSUSPIRX tHLSPIRX Figure 31 45 HSPI Data Output Input Timing ...

Page 1251: ...CCLK clock high level width tMMWH 0 4 tMMcyc ns 31 46 MCCLK clock low level width tMMWL 0 4 tMMcyc ns 31 46 MCCMD output data delay time tMMTCD 10 ns 31 46 MCCMD input data setup time tMMRCS 10 ns 31 47 MCCMD input data hold time tMMRCH 10 ns 31 47 MCDAT output data delay time tMMTDD 10 ns 31 46 MCDAT input data setup time tMMRDS 10 ns 31 47 MCDAT input data hold time tMMRDH 10 ns 31 47 tMMWH tMMT...

Page 1252: ...Section 31 Electrical Characteristics Rev 1 00 Dec 13 2005 Page 1202 of 1286 REJ09B0158 0100 tMMRCS tMMRCH tMMRDH tMMRDS MCCLK MCCMD input MCDAT input Figure 31 47 MMCIF Receive Timing ...

Page 1253: ...h tSYN_HIGH 1000 ns 31 49 HAC_SYNC delay time 1 tSYNCD1 0 15 ns 31 51 HAC_SYNC delay time 2 tSYNCD2 0 15 ns 31 51 HAC_SD_OUT delay time tSDOUTD 0 15 ns 31 51 HAC_SD_IN setup time tSDINS 10 ns 31 51 HAC_SD_IN hold time tSDINH 10 ns 31 51 HAC_BIT_CLK input high level width tICL_HIGH tPcyc 2 ns 31 50 HAC_BIT_CLK input low level width tICL_LOW tPcyc 2 ns 31 50 Note tPcyc one Pck cycle time HAC_RES tRS...

Page 1254: ...31 Electrical Characteristics Rev 1 00 Dec 13 2005 Page 1204 of 1286 REJ09B0158 0100 HAC_BITCLK HAC_SDIN HAC_SDOUT HAC_SYNC tSDINS tSDINH tSDOUTD tSYNCD1 tSYNCD2 Figure 31 51 HAC Interface Module Signal Timing ...

Page 1255: ...gh level width Output high level width tIHC tOHC 65 ns input output 31 52 Input low level width Output low level width tILC tOLC 65 ns input output 31 52 SSI_SCK Output rise time tRC 60 ns output 31 52 SSI_SDATA WS Output delay time tDTR 10 ns transmit 31 53 31 54 SSI_SDATA WS Input setup time tSR 10 ns receive 31 55 31 56 SSI_SDATA WS Input hold time tHTR 10 ns receive 31 55 31 56 tOHC tIHC VIH V...

Page 1256: ... Dec 13 2005 Page 1206 of 1286 REJ09B0158 0100 tDTR SSI_SCK SSI_WS SSI_SDATA Figure 31 54 SSI Transmit Timing 2 tSR tHTR SSI_SCK SSI_WS SSI_SDATA Figure 31 55 SSI Receive Timing 1 tSR tHTR SSI_SCK SSI_WS SSI_SDATA Figure 31 56 SSI Receive Timing 2 ...

Page 1257: ...CDAD1 1 5 tFcyc 10 ns 31 57 31 58 Command to address transition time 2 tNCDAD2 2 tFcyc 10 ns 31 58 FWE cycle time tNWC tFcyc 5 ns 31 58 31 60 FWE low pulse width tNWP 0 5 tFcyc 5 ns 31 57 31 58 31 60 31 61 FWE high pulse width tNWH 0 5 tFcyc 5 ns 31 58 31 60 Address to ready busy transition time tNADRB 32 tPcyc ns 31 58 31 59 Ready busy to data read transition time 1 tNRBDR1 1 5 tFcyc ns Ready bus...

Page 1258: ... tNCDSR 4 tFcyc ns Command output off to status read transition time tNCDFSR 3 5 tFcyc ns Status read setup time tNSTS 2 5 tFcyc ns 31 60 Notes 1 tFcyc one FLCTL clock cycle time 2 tPcyc one Pck cycle time tNDOS tNCDS tNWP tNCDH tNCDAD1 tNDOH Command Low High High FCE FCLE FALE FWE FRE FD7 to FD0 FRB R B Figure 31 57 Command Issue Timing of NAND type Flash Memory ...

Page 1259: ...DOS tNDOH tNWC tNCDAD2 Address Low High High FCE FCLE FALE FWE FRE FD7 to FD0 FRB R B Address Address Figure 31 58 Address Issue Timing of NAND type Flash Memory tNSP tNRBDR2 tNADRB tNRBDR1 tNSPH tNRDS tNRDH tNSP tNSP tNSCC Data tNRDS tNRDS tNRDH Data Low Low FCE FCLE FALE FWE FRE FD7 to FD0 FRB R B High Figure 31 59 Data Read Timing of NAND type Flash Memory ...

Page 1260: ...Data tNDOS tNDOS tNDOH Data Low Low FCE FCLE FALE FWE FRE FD7 to FD0 FRB R B High High Figure 31 60 Data Write Timing of NAND type Flash Memory tNDOS tNCDS tNWP tNCDH tNSTS tNCDFSR tNDOH Command Low High FCE FCLE FALE FWE FRE FD7 to FD0 FRB R B Low tNRDS tNSP tNCDSR tNRDH Status Figure 31 61 Status Read Timing of NAND type Flash Memory ...

Page 1261: ... Table 31 21 GPIO Signal Timing VDDQ 3 0 to 3 6V VDD 1 25V Ta 20 to 75 C 40 to 85 C CL 30pF Item Symbol Min Max Unit Figure GPIO output delay time tIOPD 1 5 6 ns 31 62 GPIO input setup time tIOPS 3 5 ns 31 62 GPIO input hold time tIOPH 1 5 ns 31 62 CLKOUT GPIO output GPIO input tIOPD tIOPS tIOPH Figure 31 62 GPIO Timing ...

Page 1262: ...lock pulse width Low tTCKL 15 ns 31 63 Input clock rise time tTCKr 10 ns 31 63 Input clock fall time tTCKf 10 ns 31 63 ASEBRK setup time tASEBRKS 10 tcyc 31 64 ASEBRK hold time tASEBRKH 10 tcyc 31 64 TDI TMS setup time tTDIS 15 ns 31 65 TDI TMS hold time tTDIH 15 ns 31 65 TDO data delay time tTDO 0 10 ns 31 65 ASEBRK pin break pulse width tPINBRK 2 tPcyc 31 66 Notes 1 tcyc one CLKOUT cycle time 2 ...

Page 1263: ...Dec 13 2005 Page 1213 of 1286 REJ09B0158 0100 ASEBRK BRKACK PRESET tASEBRKH tASEBRKS Figure 31 64 PRESET Hold Timing TDI TMS TCK TDO tTCKcyc tTDO tTDIH tTDIS Figure 31 65 H UDI Data Transfer Timing ASEBRK tPINBRK Figure 31 66 ASEBRK Pin Break Timing ...

Page 1264: ...3 0 to 3 6V VCCQ DDR 2 3 to 2 7V The output load circuit is shown in figure 31 67 IOL IOH 2 3 2 1 3 CL RT Reference level LSI output pin VTT DDR VREF DDR pins only DUT output Notes 1 CL 30pF All pins CL is the total value that includes the capacitance of measurement instruments The capacitance of each pin is set to 30 pF 2 RT 50Ω VTT DRR VREF DDR pins only 3 IOL IOH 7 6 mA DDR pins 4 mA PCI pins 2...

Page 1265: ...arger than the stipulated value 30 pF is connected to the LSI pins When connecting an external device with a load capacitance exceeding the regulation use the chart in figure 31 68 as reference for system design Note that if the load capacitance to be connected exceeds the range shown in figure 31 68 the graph will not be a straight line 4 0 ns 3 0 ns 2 0 ns 1 0 ns 0 0 ns 0 pF 25 pF 50 pF Load cap...

Page 1266: ...Section 31 Electrical Characteristics Rev 1 00 Dec 13 2005 Page 1216 of 1286 REJ09B0158 0100 ...

Page 1267: ...he CPU store instruction not the access from SuperHyway bus master except CPU After the CPUOPM is updated read CPUOPM once and execute one of the following two methods 1 Execute a branch using the RTE instruction 2 Execute the ICBI instruction for any address including non cacheable area After one of these methods are executed it is guaranteed that the CPU runs under the updated CPUOPM value 31 30...

Page 1268: ...utine return is issued speculatively When this bit is set to 0 refer to Appendix C Speculative Execution for Subroutine Return 1 Instruction fetch for subroutine return is not issued speculatively 4 0 R Reserved The write value must be the initial value 3 INTMU 0 R W Interrupt mode switch bit 0 SR IMASK is not changed when an interrupt is accepted 1 SR IMASK is changed to the accepted interrupt le...

Page 1269: ...1 presupposes a case in which the instruction ADD indicated by the program counter PC and the address H 04000002 instruction prefetch are executed simultaneously It is also assumed that the program branches to an area other than area 1 after executing the following JMP instruction and delay slot instruction In this case a bus access instruction prefetch to area 1 may unintentionally occur from the...

Page 1270: ...ter CPUOPM But this speculative instruction fetch may issue the access to the address that should not be accessed from the program Therefore a bus access to an unexpected area or an internal instruction address error may cause a problem As for the effect of this bus access to unexpected memory area refer to Appendix B Instruction Prefetch Side Effects Usage Condition When the speculative execution...

Page 1271: ...continued operation is not guaranteed do not attempt such access Legend The initial value x means undefined or depends on the setting of the external pins For details refer to the each module section H UDI H FC00 0000 H FC7F FFFF 8M bytes Physical Address Register Name Abbreviation Initial Value R W Access Size Module H FC00 0000 to H FC10 FFFF Reserved 1 114 112 bytes Physical Address Register Na...

Page 1272: ...ddress register 1 DAR1 H xxxx xxxx R W 32 DMAC H FC80 8038 DMA transfer count register 1 TCR1 H xxxx xxxx R W 32 DMAC H FC80 803C DMA channel control register 1 CHCR1 H 4000 0000 R W 32 DMAC H FC80 8040 DMA source address register 2 SAR2 H xxxx xxxx R W 32 DMAC H FC80 8044 DMA destination address register 2 DAR2 H xxxx xxxx R W 32 DMAC H FC80 8048 DMA transfer count register 2 TCR2 H xxxx xxxx R W...

Page 1273: ...t register 4 TCR4 H xxxx xxxx R W 32 DMAC H FC80 807C DMA channel control register 4 CHCR4 H 4000 0000 R W 32 DMAC H FC80 8080 DMA source address register 5 SAR5 H xxxx xxxx R W 32 DMAC H FC80 8084 DMA destination address register 5 DAR5 H xxxx xxxx R W 32 DMAC H FC80 8088 DMA transfer count register 5 TCR5 H xxxx xxxx R W 32 DMAC H FC80 808C DMA channel control register 5 CHCR5 H 4000 0000 R W 32...

Page 1274: ...served 4 bytes H FC80 8140 DMA source address register B 2 SARB2 H xxxx xxxx R W 32 DMAC H FC80 8144 DMA destination address register B 2 DARB2 H xxxx xxxx R W 32 DMAC H FC80 8148 DMA transfer count register B 2 TCRB2 H xxxx xxxx R W 32 DMAC H FC80 814C Reserved 4 bytes H FC80 8150 DMA source address register B 3 SARB3 H xxxx xxxx R W 32 DMAC H FC80 8154 DMA destination address register B 3 DARB3 ...

Page 1275: ... DMA destination address register 8 DAR8 H xxxx xxxx R W 32 DMAC H FC81 8048 DMA transfer count register 8 TCR8 H xxxx xxxx R W 32 DMAC H FC81 804C DMA channel control register 8 CHCR8 H 4000 0000 R W 32 DMAC H FC81 8050 DMA source address register 9 SAR9 H xxxx xxxx R W 32 DMAC H FC81 8054 DMA destination address register 9 DAR9 H xxxx xxxx R W 32 DMAC H FC81 8058 DMA transfer count register 9 TC...

Page 1276: ...ical Address Register Name Abbreviation Initial Value R W Access Size Module H FC81 8088 DMA transfer count register 11 TCR11 H xxxx xxxx R W 32 DMAC H FC81 808C DMA channel control register 11 CHCR11 H 4000 0000 R W 32 DMAC H FC81 8090 to H FC81 80FF Reserved 112 bytes ...

Page 1277: ...AC H FC81 8134 DMA destination address register B 7 DARB7 H xxxx xxxx R W 32 DMAC H FC81 8138 DMA transfer count register B 7 TCRB7 H xxxx xxxx R W 32 DMAC H FC81 813C Reserved 4 bytes H FC81 8140 DMA source address register B 8 SARB8 H xxxx xxxx R W 32 DMAC H FC81 8144 DMA destination address register B 8 DARB8 H xxxx xxxx R W 32 DMAC H FC81 8148 DMA transfer count register B 8 TCRB8 H xxxx xxxx ...

Page 1278: ...dule H FD00 0000 to H FDFF FFFF PCI memory space 0 16 777 216 bytes PCIC H FE00 0000 H FE3F FFFF 4M bytes R W indicates read write access from the SuperHyway bus Physical Address Register Name Abbreviation Initial Value R W Access Size Module H FE00 0000 to H FE00 0007 Reserved 8 bytes H FE00 0008 PCI enable control register PCIECR H 0000 0000 R W 32 PCIC H FE00 000C to H FE03 FFFF Reserved 262 13...

Page 1279: ...0F PCI cacheline size register PCICLS H 20 R 8 PCIC H FE04 0010 PCI I O base address register PCIIBAR H 0000 0001 R W 32 PCIC H FE04 0014 PCI Memory base address register 0 PCIMBAR0 H 0000 0000 R W 32 PCIC H FE04 0018 PCI Memory base address register 1 PCIMBAR1 H 0000 0000 R W 32 PCIC H FE04 001C to H FE04 002B Reserved 16 bytes H FE04 002C PCI subsystem ID register PCISID H 0000 R W 16 PCIC H FE0...

Page 1280: ...4 0043 PCI capability ID register PCICID H 01 R 8 PCIC H FE04 0044 PCI power consumption dissipation data register PCIPCDD H 00 R W 8 PCIC H FE04 0045 PCI PMCSR bridge support extension register PCIPMCSRBSE H 00 R 8 PCIC H FE04 0046 PCI power management control status register PCIPMCSR H 0000 R W 16 PCIC H FE04 0048 to H FE04 00FF Reserved 184 bytes ...

Page 1281: ...mmand information register PCICIR H xx00 000x R 32 PCIC H FE04 0124 to H FE04 012F Reserved 12 bytes H FE04 0130 PCI arbiter interrupt register PCIAINT H 0000 0000 R W 32 PCIC H FE04 0134 PCI arbiter interrupt mask register PCIAINTM H 0000 0000 R W 32 PCIC H FE04 0138 PCI arbiter bus master information register PCIBMIR H 0000 00xx R 32 PCIC H FE04 013C to H FE04 01BF Reserved 132 bytes H FE04 01C0...

Page 1282: ... W 32 PCIC Physical Address Register Name Abbreviation Initial Value R W Access Size Module H FE04 0200 to H FE04 020F Reserved 16 bytes H FE04 0210 PCI cache snoop control register 0 PCICSCR0 H 0000 0000 R W 32 PCIC H FE04 0214 PCI cache snoop control register 1 PCICSCR1 H 0000 0000 R W 32 PCIC H FE04 0218 PCI cache snoop address register 0 PCICSAR0 H 0000 0000 R W 32 PCIC H FE04 021C PCI cache s...

Page 1283: ... FFFF Reserved 65 536 bytes H FE41 0000 to H FE41 3FFF SuperHyway RAM 0 16 384 bytes Undefined R W SuperHyway RAM H FE41 4000 to H FE41 FFFF Reserved 49 152 bytes Physical Address Register Name Abbreviation Initial Value R W Access Size Module H FE42 0000 to H FE42 3FFF SuperHyway RAM 1 16 384 bytes Undefined R W SuperHyway RAM H FE42 4000 to H FE7F FFFF Reserved 4 046 848 bytes Note 8 16 32 64 bi...

Page 1284: ...H FE80 001C DDR SDRAM timing register STR 2 H 0000 0000 R W 32 DDRIF H FE80 0030 DDR SDRAM row attribute register SDR 1 H 0000 0000 R W 32 DDRIF H FE80 0034 DDR SDRAM row attribute register SDR 2 H 0000 0000 R W 32 DDRIF H FE80 0038 to H FE80 03FF Reserved 968 bytes Physical Address Register Name Abbreviation Initial Value R W Access Size Module H FE80 0400 DDR SDRAM back up register DBK 1 H 0000 ...

Page 1285: ...ster TEA H xxxx xxxx R W 32 MMU H FF00 0010 MMU control register MMUCR H 0000 0000 R W 32 MMU H FF00 0014 to H FF00 001B Reserved 8 bytes H FF00 001C Cache control register CCR H 0000 0000 R W 32 Cache H FF00 0020 TRAPA exception register TRA H xxxx xxxx R W 32 Exception Handling H FF00 0024 Exception event register EXPEVT H 0000 0000 R W 32 Exception Handling H FF00 0028 Interrupt event register ...

Page 1286: ...ss register 0 LDA0 H xxxx xxxx R W 32 L RAM H FF00 005C L memory transfer destination address register 1 LDA1 H xxxx xxxx R W 32 L RAM H FF00 0060 to H FF00 006F Reserved 16 bytes H FF00 0070 Physical address space control register PASCR H 0000 0000 R W 32 MMU H FF00 0074 On chip memory control register RAMCR H 0000 0000 R W 32 Cache L RAM H FF00 0078 Instruction re fetch inhibit control register ...

Page 1287: ...h operation setting register 1 CRR1 H 0000 2000 R W 32 UBC H FF20 0028 Match address setting register 1 CAR1 H xxxx xxxx R W 32 UBC H FF20 002C Match address mask setting register 1 CAMR1 H xxxx xxxx R W 32 UBC H FF20 0030 Match data setting register 1 CDR1 H xxxx xxxx R W 32 UBC H FF20 0034 Match data mask setting register 1 CDMR1 H xxxx xxxx R W 32 UBC H FF20 0038 Execution count break register ...

Page 1288: ...tion Initial Value R W Access Size Module H FF40 0000 to H FF40 001F Reserved 32 bytes H FF40 0020 Memory Address Map Select Register MMSELR H 0000 0000 R W 32 LBSC Physical Address Register Name Abbreviation Initial Value R W Access Size Module H FF40 0024 to H FF7F FFFF Reserved 4 194 268 bytes LBSC H FF80 0000 H FFBF FFFF 4M bytes Physical Address Register Name Abbreviation Initial Value R W Ac...

Page 1289: ...770F R W 32 LBSC H FF80 202C to H FF80 203F Reserved 20 bytes H FF80 2040 CS4 Bus Control Register CS4BCR H 7777 7770 R W 32 LBSC H FF80 2044 Reserved 4 bytes H FF80 2048 CS4 Wait Control Register CS4WCR H 7777 770F R W 32 LBSC H FF80 204C Reserved 4 bytes H FF80 2050 CS5 Bus Control Register CS5BCR H 7777 7770 R W 32 LBSC H FF80 2054 Reserved 4 bytes H FF80 2058 CS5 Wait Control Register CS5WCR H...

Page 1290: ...FC8 0030 Standby control register MSTPCR H 0000 0000 R W 32 CPG H FFC8 0034 to H FFCB FFFF Reserved 262 092 bytes Physical Address Register Name Abbreviation Initial Value R W Access Size Module H FFCC 0000 Watchdog timer stop time register WDTST H 0000 0000 R W 32 WDT H FFCC 0004 Watchdog timer control status register WDTCSR H 0000 0000 R W 32 WDT H FFCC 0008 Watchdog timer base stop time registe...

Page 1291: ...28 to H FFD0 0043 Reserved 28 bytes H FFD0 0044 Interrupt mask register 0 INTMSK0 H 0000 0000 R W 32 INTC H FFD0 0048 Interrupt mask register 1 INTMSK1 H FF00 0000 R W 32 INTC H FFD0 004C to H FFD0 0063 Reserved 24 bytes H FFD0 0064 Interrupt mask clear register 0 INTMSKCLR0 H 0000 0000 R W 32 INTC H FFD0 0068 Interrupt mask clear register 1 INTMSKCLR1 H 0000 0000 R W 32 INTC H FFD0 006C to H FFD0...

Page 1292: ...ask state is not affected INT2A0 H xxxx xxxx R 32 INTC H FFD4 0034 Interrupt source register mask state is affected INT2A1 H 0000 0000 R 32 INTC H FFD4 0038 Interrupt mask register INT2MSKRG H FFFF FFFF R W 32 INTC H FFD4 003C Interrupt mask clear register INT2MSKCR H 0000 0000 R W 32 INTC H FFD4 0040 Individual module interrupt source registers 0 INT2B0 H xxxx xxxx R 32 INTC H FFD4 0044 Individua...

Page 1293: ...tput control register TOCR H 00 R W 8 TMU H FFD8 0004 Timer start register 0 TSTR0 H 00 R W 8 TMU H FFD8 0008 Timer constant register 0 TCOR0 H FFFF FFFF R W 32 TMU H FFD8 000C Timer counter 0 TCNT0 H FFFF FFFF R W 32 TMU H FFD8 0010 Timer control register 0 TCR0 H 0000 R W 16 TMU H FFD8 0014 Timer constant register 1 TCOR1 H FFFF FFFF R W 32 TMU H FFD8 0018 Timer counter 1 TCNT1 H FFFF FFFF R W 3...

Page 1294: ...CR5 H 0000 R W 16 TMU H FFDC 002A to H FFDF FFFF Reserved 262 102 bytes Physical Address Register Name Abbreviation Initial Value R W Access Size Module H FFE0 0000 Serial mode register 0 SCSMR0 H 0000 R W 16 SCIF H FFE0 0004 Bit rate register 0 SCBRR0 H FF R W 8 SCIF H FFE0 0008 Serial control register 0 SCSCR0 H 0000 R W 16 SCIF H FFE0 000C Transmit FIFO data register 0 SCFTDR0 H xx W 8 SCIF H F...

Page 1295: ... xx W 8 SCIF H FFE1 0010 Serial status register 1 SCFSR1 H 0060 R W 16 SCIF H FFE1 0014 Receive FIFO data register 1 SCFRDR1 H xx R 8 SCIF H FFE1 0018 FIFO control register 1 SCFCR1 H 0000 R W 16 SCIF H FFE1 001C Transmit FIFO data count register 1 SCTFDR1 H 0000 R 16 SCIF H FFE1 0020 Receive FIFO data count register 1 SCRFDR1 H 0000 R 16 SCIF H FFE1 0024 Serial port register 1 SCSPTR1 H 00xx R W ...

Page 1296: ...gister SICDAR H 0000 R W 16 SIOF H FFE2 000C Control register SICTR H 0000 R W 16 SIOF H FFE2 0010 FIFO control register SIFCTR H 1000 R W 16 SIOF H FFE2 0014 Status register SISTR H 0000 R W 16 SIOF H FFE2 0016 Interrupt enable register SIIER H 0000 R W 16 SIOF H FFE2 0018 to H FFE2 001F Reserved 8 bytes H FFE2 0020 Transmit data register SITDR H xxxx xxxx W 32 SIOF H FFE2 0024 Receive data regis...

Page 1297: ...me register CMTCH1T H 0000 0000 R W 32 CMT H FFE3 0018 Channel 2 time register CMTCH2T H 0000 0000 R W 32 CMT H FFE3 001C Channel 3 time register CMTCH3T H 0000 0000 R W 32 CMT H FFE3 0020 Channel 0 stop time register CMTCH0ST H 0000 0000 R W 32 CMT H FFE3 0024 Channel 1 stop time register CMTCH1ST H 0000 0000 R W 32 CMT H FFE3 0028 to H FFE3 002F Reserved 8 bytes H FFE3 0030 Channel 0 timer count...

Page 1298: ...32 bytes H FFE4 6050 TX interrupt enable register HACTIER H 0000 0000 R W 32 HAC H FFE4 6054 TX status register HACTSR H F000 0000 R W 32 HAC H FFE4 6058 RX interrupt enable register HACRIER H 0000 0000 R W 32 HAC H FFE4 605C RX status register HACRSR H 0000 0000 R W 32 HAC H FFE4 6060 HAC control register HACACR H 8400 0000 R W 32 HAC H FFE4 6064 to H FFE4 FFFF Reserved 40 860 bytes Physical Addr...

Page 1299: ...6 000E Interrupt status register 0 INTSTR0 H 00 R W 8 MMCIF H FFE6 000F Interrupt status register 1 INTSTR1 H 00 R W 8 MMCIF H FFE6 0010 Transfer clock control register CLKON H 00 R W 8 MMCIF H FFE6 0011 Command timeout control register CTOCR H 00 R W 8 MMCIF H FFE6 0014 Transfer byte number count register TBCR H 00 R W 8 MMCIF H FFE6 0016 Mode register MODER H 00 R W 8 MMCIF H FFE6 0018 Command t...

Page 1300: ... 00 R W 8 MMCIF H FFE6 0031 CRC status register RSPRD H 00 R W 8 MMCIF H FFE6 0032 Data timeout register DTOUTR H FFFF R W 16 MMCIF H FFE6 0034 to H FFE6 003F Reserved 12 bytes H FFE6 0040 Data register DR H xxxx R W 16 MMCIF H FFE6 0042 FIFO pointer clear register FIFOCLR H 00 W 8 MMCIF H FFE6 0044 DMA control register DMACR H 00 R W 8 MMCIF H FFE6 0046 Interrupt control register 2 INTCR2 H 00 R ...

Page 1301: ...E8 001C Year counter RYRCNT H xxxx R W 16 RTC H FFE8 0020 Second alarm register RSECAR H xx R W 8 RTC H FFE8 0024 Minute alarm register RMINAR H xx R W 8 RTC H FFE8 0028 Hour alarm register RHRAR H xx R W 8 RTC H FFE8 002C Day of week alarm register RWKAR H xx R W 8 RTC H FFE8 0030 Day alarm register RDAYAR H xx R W 8 RTC H FFE8 0034 Month alarm register RMONAR H xx R W 8 RTC H FFE8 0038 RTC contr...

Page 1302: ...TL H FFE9 0010 Data register FLDATAR H 0000 0000 R W 32 FLCTL H FFE9 0014 Data counter register FLDTCNTR H 0000 0000 R W 32 FLCTL H FFE9 0018 Interrupt DMA control register FLINTDMACR H 0000 0000 R W 32 FLCTL H FFE9 001C Ready busy timeout setting register FLBSYTMR H 0000 0000 R W 32 FLCTL H FFE9 0020 Ready busy timeout counter FLBSYCNT H 0000 0000 R 32 FLCTL H FFE9 0024 Data FIFO register FLDTFIF...

Page 1303: ...4 Port L control register PLCR H FFFF R W 16 GPIO H FFEA 0016 Port M control register PMCR H FFFF R W 16 GPIO H FFEA 0018 to H FFEA 001F Reserved 8 bytes H FFEA 0020 Port A data register PADR H 00 R W 8 GPIO H FFEA 0022 Port B data register PBDR H 00 R W 8 GPIO H FFEA 0024 Port C data register PCDR H 00 R W 8 GPIO H FFEA 0026 Port D data register PDDR H 00 R W 8 GPIO H FFEA 0028 Port E data regist...

Page 1304: ... 0052 Port K pull up control register PKPUPR H FF R W 8 GPIO H FFEA 0056 Port M pull up control register PMPUPR H FF R W 8 GPIO H FFEA 0057 to H FFEA 005F Reserved 9 bytes H FFEA 0060 Input pin pull up control register 1 PPUPR1 H FFFF R W 16 GPIO H FFEA 0062 Input pin pull up control register 2 PPUPR2 H FFFF R W 16 GPIO H FFEA 0064 to H FFEA 007F Reserved 28 bytes H FFEA 0080 On chip module select...

Page 1305: ... C A φ 0 08 M C B A B 0 20 21 00 Index 0 80 4 449 φ 0 50 0 05 0 4 0 05 2 0 Max 0 15 C 0 35 C 0 90 0 90 C A 0 80 Unit mm PRBG0449GA A P FBGA449 21x21 0 80 RENESAS Code JEITA Code Figure E 1 Package Dimensions 449 Pin BGA Note The Tj junction temperature of this LSI becomes over 125 C if operating with the maximum power consumption So a careful thermal design is necessary Use a heat sink or forced a...

Page 1306: ...PLL1 PLL2 CPU Clock Ick Super Hyway Clock SHck Peripheral Clock Pck DDR Clock DDRck Bus Clock Bck FRQCR Initial Value 0 L On 12 6 3 2 24 5 3 H 1023 3335 1 L H On 12 6 1 24 5 2 H 1024 4336 2 L On 12 6 3 2 24 5 3 2 H 1025 5335 3 LL H H On 12 6 1 24 5 1 H 1026 6336 12 HH L L On 12 4 1 4 2 H 1044 4346 Table F 2 Area 0 Memory Map and Bus Width Pin Value MODE4 MODE3 Memory Interface Bus Width L L MPX in...

Page 1307: ... Mode L PCIC normal non host H PCI host bus bridge Table F 5 Clock Input Pin Value MODE8 Clock Input L External input clock H Crystal resonator Table F 6 Mode Control Pin Value MPMD Mode L Emulation support mode H LSI operation mode Note When using emulation support mode refer to the emulator manual of the SH7780 ...

Page 1308: ... I O Z PZ Z PZ Z PZ Z Port G 7 0 GPIO I O PI I O PI I O PI I O D 15 0 D 15 0 LBSC I O Z PZ Z PZ Z PZ Z CS 2 0 CS 6 4 CS 2 0 CS 6 4 LBSC O H H O PZ Z BACK Port M0 default GPIO I O PI 2 PI I O PI I O PI I O BACK LBSC O H O O BREQ Port M1 default GPIO I O PI 2 PI I O PI I O PI I O BREQ LBSC I I I I BS BS LBSC O H H O PZ Z R W R W LBSC O H H O PZ Z RD FRAME RD FRAME LBSC O H O O PZ Z O RDY RDY LBSC I ...

Page 1309: ...UT RESET O L O O AUDATA2 H UDI O O O O Port K2 default GPIO I O PI 2 I O I O I O DACK3 IRQOUT AUDATA3 DACK3 DMAC O O O K O IRQOUT INTC O O O O AUDATA3 H UDI O O O O DRAK0 MODE2 MODE2 POR CPG I I Port L1 3 default GPIO O O O O DRAK0 DMAC O O O K O DRAK1 MODE7 MODE7 POR CPG I I Port L0 3 default GPIO O O O O DRAK1 DMAC O O O K O DRAK2 CE2A AUDCK Port K1 3 default GPIO O O O O O DRAK2 DMAC O O O K O ...

Page 1310: ...DATA0 DREQ2 DMAC I PZ Z PI I PZ Z PI I INTB PCIC I PI I PI I PI I AUDATA0 H UDI O O O O Port K4 default GPIO I O PI 2 PI I O PI I O PI I O DREQ3 INTC AUDATA1 DREQ3 DMAC I PZ Z PI I PZ Z PI I INTC PCIC I PI I PI I PI I AUDATA1 H UDI O O O O MCLK MCLK DDRIF O O O O O MCLK MCLK DDRIF O O O O O MDQS 3 0 MDQS 3 0 DDRIF I O Z Z I O I O MDQM 3 0 MDQM 3 0 DDRIF O H H O O MDA 31 0 MDA 31 0 DDRIF I O Z Z I ...

Page 1311: ...7 0 GPIO I O I O I O I O CBE 3 0 CBE 3 0 PCIC I O Z I O I O I O GNT0 GNTIN GNT0 GNTIN PCIC I O PZ PI O PI O PI O GNT 3 1 GNT 3 1 default PCIC O PZ O O O Port E0 E2 GPIO I O PI O PI O PI O REQ0 REQOUT REQ0 REQOUT PCIC I O PZ I O I O I O REQ 3 1 REQ 3 1 default PCIC I PZ PI PI PI Port E3 E5 GPIO I O PZ PI O PI O PI O DEVSEL DEVSEL PCIC I O PZ PI O PI O PI O PCIFRAME PCIFRAME PCIC I O PZ PI O PI O PI...

Page 1312: ...t RESET O H H L O CMT_CTR0 CMT I O PZ O I O K PI I O STATUS1 CMT_CTR1 STATUS1 default RESET O H H H O CMT_CTR1 CMT I O PZ O I O K PI I O IRQ IRL 3 0 IRQ IRL 3 0 INTC I PI 2 PI I PI I PI I MODE3 POR LBSC I I IRQ IRL4 FD4 MODE3 IRQ IRL4 default INTC I I I I FD4 FLCTL I O I O I O K I O MODE4 POR LBSC I I IRQ IRL5 FD5 MODE4 IRQ IRL5 default INTC I I I I FD5 FLCTL I O I O I O K I O MODE6 POR PCIC I I I...

Page 1313: ... I O FSE FLCTL O O O K O SCIF0_RXD HSPI_RX FRB Port H2 default GPIO I O PI 2 PI I O PI I O PI I O SCIF_RXD SCIF I PI I PI I PZ Z PI I HSPI_RX HSPI I PI I PI I PZ Z PI I FRB FLCTL I PI I PI I PZ Z PI I SCIF0_SCK HSPI_CLK FRE Port H4 default GPIO I O PI 2 PI I O PI I O PI I O SCIF0_SCK SCIF I O PI I PI I O K PI I O HSPI_CLK HSPI I O PI I O PI I O K PI I O FRE FLCTL O O O K O MODE8 POR CPG I I SCIF0_...

Page 1314: ...HAC_RES HAC O O O K O Port J4 default GPIO I O PI 2 PI I O PI I O PI I O SIOF_RXD SIOF I PI I PI I PZ Z PI I SIOF_RXD HAC_SDIN SSI_SCK HAC_SDIN HAC I PI I PI I PZ Z PI I SSI_SCK SSI I O PI I PI I O K PI I O Port J1 default GPIO I O PI 2 PI I O PI I O PI I O SIOF_SCK SIOF I O PI I O PI I O K PI I O SIOF_SCK HAC_BITCLK SSI_CLK HAC_BITCLK HAC I PI I PI I PZ Z PI I SSI_CLK SSI I O PI I PI I O K PI I O...

Page 1315: ...O AUDSYNC FCE AUDSYNC default H UDI O O O O O FCE FLCTL O O O K O AUDATA 3 0 default H UDI O O O O O AUDATA 3 0 FD 3 0 FD 3 0 FLCTL I O PI I O PI I O K PI I O MPMD MPMD H UDI I PI PI PI PI XRTCSTBI XRTCSTBI RTC I I I I I XTAL2 XTAL2 RTC O O O O O EXTAL2 EXTAL2 RTC I I I I I Legend Disabled not selected or not supported I Input O Output H High level output L Low level output Z High impedance state ...

Page 1316: ...86 REJ09B0158 0100 Notes 1 High impedance state until the internal clock is stable 2 Input state until the internal clock is stable 3 Do not input signals to these pins immediately after power on reset because these initial states are port outputs ...

Page 1317: ... LBSC I O Must be used CS 2 0 CS 6 4 CS 2 0 CS 6 4 LBSC O Open BACK Port M0 default GPIO I O Open BACK LBSC O BREQ Port M1 default GPIO I O Open BREQ LBSC I BS BS LBSC O Open R W R W LBSC O Open RD FRAME RD FRAME LBSC O Open RDY RDY LBSC I Pulled down to VSSQ 1 WE0 REG WE0 REG LBSC O Open WE1 WE1 LBSC O Open WE2 IORD WE2 IORD LBSC O Open WE3 IOWR WE3 IOWR LBSC O Open DACK0 MODE0 MODE0 POR CPG I Mu...

Page 1318: ...UT INTC O AUDATA3 H UDI O DRAK0 MODE2 MODE2 POR CPG I Must be used during power on reset Port L1 default GPIO O Open DRAK0 DMAC O DRAK1 MODE7 MODE7 POR CPG I Must be used during power on reset Port L0 default GPIO O Open DRAK1 DMAC O DRAK2 CE2A AUDCK Port K1 default GPIO O Open DRAK2 DMAC O CE2A LBSC O AUDCK H UDI O Port K0 default GPIO O Open DRAK3 CE2B AUDSYNC DRAK3 DMAC O CE2B LBSC O AUDSYNC H ...

Page 1319: ...IF O Open MDQS 3 0 MDQS 3 0 DDRIF I O Open MDQM 3 0 MDQM 3 0 DDRIF O Open MDA 31 0 MDA 31 0 DDRIF I O Open CKE CKE DDRIF O Open MCAS MCAS DDRIF O Open MRAS MRAS DDRIF O Open MCS MCS DDRIF O Open MWE MWE DDRIF O Open MA 13 0 MA 13 0 DDRIF O Open BA 1 0 BA 1 0 DDRIF O Open BKPRST BKPRST DDRIF I Pulled up to VCCQ DDR AD 31 24 AD 31 24 default PCIC I O Open Port A 7 0 GPIO I O AD 23 16 AD 23 16 defaul...

Page 1320: ...IC I Pulled down to VSSQ INTA INTA PCIC I O Pulled up to VDDQ IRDY IRDY PCIC I O Open LOCK LOCK PCIC I O Open PAR PAR PCIC I O Open PCICLK PCICLK PCIC I Fixed to VSSQ PCIRESET PCIRESET PCIC O Open PERR PERR PCIC I O Open SERR SERR PCIC I O Pulled up to VDDQ STOP STOP PCIC I O Open TRDY TRDY PCIC I O Open CLKOUT CLKOUT CPG O Open PRESET PRESET RESET I Must be used during power on reset EXTAL EXTAL ...

Page 1321: ...t INTC I Pulled up to VDDQ FD5 FLCTL I O IRQ IRL6 FD6 MODE6 MODE6 POR PCIC I Must be used during power on reset IRQ IRL6 default INTC I Pulled up to VDDQ FD6 FLCTL I O IRQ IRL7 FD7 Port E6 default GPIO I O Open IRQ IRL7 INTC I FD7 FLCTL I O NMI NMI INTC I Pulled up to VDDQ Port H1 default GPIO I O Open SCIF0_CTS INTD FCLE SCIF0_CTS SCIF I INTD PCIC I Port H0 default GPIO I O Open SCIF0_RTS HSPI_CS...

Page 1322: ...GPIO O Open SCIF0_TXD SCIF O HSPI_TX HSPI O FWE FLCTL O SCIF1_RXD MCDAT Port H5 default GPIO I O Open SCIF1_RXD SCIF I MCDAT MMCIF I O SCIF1_SCK MCCMD Port H7 default GPIO I O Open SCIF1_SCK SCIF I O MCCMD MMCIF I O SCIF1_TXD MCCLK MODE5 MODE5 POR LBSC I Must be used during power on reset Port H6 default GPIO O Open SCIF1_TXD SCIF O MCCLK MMCIF O Port J2 default GPIO I O Open SIOF_MCLK HAC_RES SIO...

Page 1323: ... Port J5 default GPIO I O Open SIOF_TXD HAC_ SDOUT SSI_SDATA SIOF_TXD SIOF O HAC_SDOUT HAC O SSI_SDATA SSI I O TCLK IOIS16 Port J0 default GPIO I O Open TCLK TMU I O IOIS16 LBSC I ASEBRK BRKACK ASEBRK BRKACK H UDI I O Open 2 TCK TCK TMU I Open 2 TRST TRST H UDI I Fixed to ground or connected to PRESET 2 3 TDI TDI H UDI I Open 2 TMS TMS H UDI I Open 2 TDO TDO H UDI O Open 2 AUDCK FALE AUDCK default...

Page 1324: ... LSI after power on reset Set the RDYPUP bit in PPUPR1 GPIO to 1 to pull up off the RDY pin s pulled up 2 When using an emulator follow the instruction from the emulator 3 When not using emulator the pin should be fixed to ground or connected to another pin which operates in the same manner as PRESET However when fixed to a ground pin the following problem occurs Since the TRST pin is pulled up wi...

Page 1325: ...ackup Turning Off Power Supply There is no restriction for the order of the power supply between each power supplies Within 300 ms after turning off a single power supply turn off all the other power supplies except DDR SDRAM power supply backup and RTC power supply backup Turning on 0 1 V min V min 300 t 0 ms V min VDD VDD PLL1 to 3 VDD DLL1 to 2 1 15 V VCCQ DDR 2 3 V VDDQ VDD RTC 3 0 V Turning o...

Page 1326: ...Register Configuration Register Name Abbrev R W Initial Value P4 Address Area 7 Address Access Size Processor Version Register PVR R H 1020 0Axx H FF00 0030 H 1F00 0030 32 Product Register PRR R H 0000 092x H FF00 0044 H 1F00 0044 32 Legend x Undefined Processor Version Register PVR 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit version information version information 0 0 0 1 0 0 0 0 0 0 1 0 ...

Page 1327: ...t Table J 1 SH7780 Product Lineup Product Name Voltage Operating Frequency Part Number Operating Temperature Package SH7780 1 25 V 400 MHz R8A77800ADBG 40 to 85 C 449 pin BGA R8A77800ADBGV 449 pin BGA Lead Free R8A77800ANBG 20 to 75 C 449 pin BGA R8A77800ANBGV 449 pin BGA Lead Free ...

Page 1328: ...Appendix Rev 1 00 Dec 13 2005 Page 1278 of 1286 REJ09B0158 0100 ...

Page 1329: ...tions 65 Break 794 BRI 793 Burst mode 599 Burst Mode 599 Burst ROM Interface 370 Bus Arbitration 395 Byte Control SRAM Interface 389 C Cacheability bit 168 Caches 197 Clock Pulse Generator CPG 613 Clocked synchronous serial communication mode 733 Command Access Mode 1044 Compare Match Timer CMT 677 Control registers 34 Crystal Oscillator Circuit 730 CUI 730 Cycle steal mode 597 D Data address erro...

Page 1330: ...exception 120 General FPU disable exceptions and slot FPU disable exceptions 142 General illegal instruction exception 118 General interrupt request 125 General Purpose I O GPIO 1055 General registers 34 Geometric operation instructions 144 H Hardware ITLB miss handling 175 H UDI reset 108 I I O card interface 372 IC memory card interface 372 Inexact exception 142 Initial page write exception 112 ...

Page 1331: ...k 1123 Overflow 142 P P0 P3 and U0 areas 152 P1 area 152 P2 area 152 P4 area 152 Page size bits 168 Pair single precision data transfer instructions 145 PCMCIA Interface 372 PCMCIA Support 325 Pipelining 73 Power Down Mode 428 643 Power down state 49 Power on reset 108 PPN 168 Pre execution user break post execution user break 122 Prefetch instruction 238 PRI 730 Privileged mode 34 Processing mode...

Page 1332: ...26 FLDATAR 1033 FLDTCNTR 1032 FLDTFIFO 1041 FLECFIFO 1042 FLINTDMACR 1034 FLTRCR 1043 FPSCR 43 137 FPUL 140 FRQCR 619 GBR 42 HACACR 971 HACCR 958 HACCSAR 960 HACCSDR 962 HACPCML 963 HACPCMR 965 HACRIER 969 HACRSR 970 HACTIER 966 HACTSR 967 ICR 255 INT2A 277 INT2B 287 INT2GPIC 294 INT2MSKCR 285 INT2MSKR 282 INT2PRI 276 INTCR 877 INTEVT 100 INTMSK 261 INTMSKCLR 266 INTPRI 259 INTREQ 260 INTSTR 880 I...

Page 1333: ... PMDR 1087 PMPUPR 1091 PMSELR 1094 PPUPR1 1092 PPUPR2 1093 PR 42 PTEH 157 PTEL 158 QACR0 203 QACR1 204 R64CNT 712 RAMCR 205 229 RCR1 721 RCR2 723 RCR3 726 RDAYAR 719 RDAYCNT 715 RHRAR 718 RHRCNT 713 RMINAR 717 RMINCNT 713 RMONAR 720 RMONCNT 716 RSECAR 717 RSECCNT 712 RSPR 895 RSPTYR 890 RWKAR 718 RWKCNT 714 RYRAR 720 RYRCNT 716 SAR 567 SARB 568 SCBRR 758 SCFCR 759 SCFRDR 742 SCFSR 751 SCFTDR 743 S...

Page 1334: ...ckup 653 RXI 793 S Sector Access Mode 1046 Sequential break 1124 Serial Communication Interface with FIFO SCIF 733 Serial I O with FIFO SIOF 797 Serial Protocol Interface HSPI 849 Serial Sound Interface SSI Module 983 Share status bit 168 Shift instructions 64 Sign extended 47 Single virtual memory mode 155 Single precision floating point extended register matrix 39 Single precision floating point...

Page 1335: ...s 102 U Unconditional trap 117 Underflow 142 User break controller 1101 User break operation 1121 User debugging interface 1135 User mode 34 UTLB 167 UTLB address array 186 UTLB data array 187 V Validity bit 168 Vector addresses 102 Virtual address space 149 VPN 167 W Wait Cycles between Accesses 393 Watchdog Timer and Reset 625 Write back instruction 238 Write through bit 169 ...

Page 1336: ...Rev 1 00 Dec 13 2005 Page 1286 of 1286 REJ09B0158 0100 ...

Page 1337: ...lication Date Rev 1 00 Dec 13 2005 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Customer Support Department Global Strategic Communication Div Renesas Solutions Corp 2005 Renesas Technology Corp All rights reserved Printed in Japan ...

Page 1338: ...nesas Technology Hong Kong Ltd 7th Floor North Tower World Finance Centre Harbour City 1 Canton Road Tsimshatsui Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2730 6071 Renesas Technology Taiwan Co Ltd 10th Floor No 99 Fushing North Road Taipei Taiwan Tel 886 2 2715 2888 Fax 886 2 2713 2999 Renesas Technology Singapore Pte Ltd 1 Harbour Front Avenue 06 10 Keppel Bay Tower Singapore 098632 Tel 65 621...

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Page 1340: ...SH7780 Hardware Manual ...

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