LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 871 / 882

ML62Q1000 Series User’s Manual
Appendix E. List of Notes
FEUL62Q1000 E-12
[ ] When performing the software trigger by setting the DCnSTRG bit to "1", the transfer is held if the next
instruction is data memory access. Place two NOP instructions after setting DCnSTRG to "1" to prevent
the hold and make the immediate transfer.
[ ] When selecting the 16bit timer DMA request, choose the 16bit timer mode by setting THn8BM bit of
16bit timer n mode register (TMHnMOD) to "0".
[ ] The DMA requests in the channel 0 and channel 1 of the serial communication unit are only available
for the DMA transfer trigger.
See Section 14.2.3 "DMA Channel n Transfer Count Register (DCnTN: n = 0, 1)".
[ ] Set the DCnTN register when the transfer is disabled (DCnEN = 0). The DCnTN is not writable if the
transfer is enabled (DCnEN = 1).
[ ] If the transfer is stopped (DCnEN = 0) before finishing the specified transfer count, the value of the
DCnTN is not guaranteed. Reconfigure the DCnTN when restarting the transfer.
See Section 14.2.4 "DMA Channel n Transfer Source Address Register (DCnSA: n = 0, 1)".
[ ] Set the DCnSA register when the transfer is disabled (DCnEN bit = 0). The DCnTN is not writable if the
transfer is enabled (DCnEN bit = 1).
[ ] If the transfer is stopped (DCnEN bit = 0) before finishing the specified transfer count, the value of the
DCnSA is not guaranteed. Reconfigure the DCnSA when restarting the transfer..
See Section 14.2.5 "DMA Channel n Transfer Destination Address Register (DCnDA: n = 0, 1)".
[ ] Set the DCnDA register when the transfer is disabled (DCnEN bit = 0). The DCnTN is not writable if the
transfer is enabled (DCnEN bit = 1).
[ ] If the transfer is stopped (DCnEN bit = 0) before finishing the specified transfer count, the value of the
DCnSA is not guaranteed. Reconfigure the DCnDA when restarting the transfer.
See Section 14.2.6 "DMA Transfer Enable Register (DCEN)".
[ ] Set the DCF bit when the transfer is disabled (DCnEN bit = 0). The DCnTN is not writable if the transfer
is enabled (DCnEN bit = 1).
[ ] When the specified transfer count is completed, the channel corresponding bit of the DMA interrupt
status register (DSTATL) is set to "1". Be sure to clear the status bit (DCnISTA) by using the DMA
interrupt status clear register (DICLR) before enabling the next DMA transfer. When the status is "1", the
DMA transfer is unenabled. Clear the status bit (DCnISTA) regardless using or not using the DMA
interrupt.
See Section 14.3.2 "DMA transfer Operation Timing Diagram".
[ ] CPU data memory access is processed in priority to the DMA transfer. Successive CPU data memory
access may cause the DMA transfer to be held, resulting in the transfer trigger overwritten. Prevent
successive CPU data memory access from continuing for longer than the transfer trigger generation
cycle. If CPU data memory access is not performed, ensure that the interval of four clocks of the system
clock is secured.
[ ] If a transfer trigger and the software trigger are generated at the same time, the transfer trigger is
overwritten. Pay attention to the timing the software trigger is generated.
[ ] Specify an area where the RAM and SFR exist for the transfer source address and destination address.
If the area that does not exist in the transfer source address is set, data "0x00" is transferred. If the area
that does not exist in the transfer destination address is set, it is invalid.
Chapter 15 Buzzer
See Section 15.3.1.2 "Example of Intermittent Sound 1 Mode Setting Procedure".
[ ] The buzzer output may be started in the middle of the buzzer waveform depending on timing the
BZ0RUN bit of the BZ0CON register is set to "1". If it causes a problem, take one of the following
measure A or measure B :
Measure A: Use the low-speed time base counter interrupt (choose T8HZ or T1HZ for signal
assignment).
Measure B: Use the LTBR register to synchronize the falling edge of the T8HZ or T1HZ signal with the
timing BZ0RUN is set to "1".