LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 490 / 882

ML62Q1000 Series User's Manual
Chapter 12 I2C Bus Unit
FEUL62Q1000 12-34
Table 12-5 Relationship between Communication Speeds and HSCLK Clock Counts (at HSCLK=16MHz)
I2UM0MOD register
t
CYC
t
HD:STA
t
LOW
t
HD:DAT
t
HIGH
t
SU:STA
t
SU:DAT
t
SU:STO
t
BUF
Communication
speed
(I2UM0MD1,
I2UM0MD0 bits)
Speed reduction
(I2UM0DW1,
I2UM0DW0 bits)
00
(Standard
mode
: 100 kbps)
00 (no reduction)
160 φ 72 φ 88 φ 16 φ 72 φ 88 φ 72 φ 72 φ 88 φ
01 (10% reduction)
176 φ 80 φ 96 φ 16 φ 80 φ 96 φ 80 φ 80 φ 96 φ
10 (20% reduction)
192 φ 88 φ 104 φ 16 φ 88 φ 104 φ 88 φ 88 φ 104 φ
11 (30% reduction)
208 φ 96 φ 112 φ 16 φ 96 φ 112 φ 96 φ 96 φ 112 φ
01
(Fast
mode
: 400 kbps)
00 (no reduction)
40 φ 14 φ 26 φ 12 φ 14 φ 26 φ 14 φ 14 φ 26 φ
01 (10% reduction)
44 φ 16 φ 28 φ 12 φ 16 φ 28 φ 16 φ 16 φ 28 φ
10 (20% reduction)
48 φ 18 φ 30 φ 12 φ 18 φ 30 φ 18 φ 18 φ 30 φ
11 (30% reduction)
52 φ 20 φ 32 φ 12 φ 20 φ 32 φ 20 φ 20 φ 32 φ
10 or 11
(1 Mbps
mode
: 1 Mbps)
00 (no reduction)
16 φ 6 φ 10 φ 4 φ 6 φ 10 φ 6 φ 6 φ 10 φ
01 (10% reduction)
18 φ 7 φ 11 φ 4 φ 7 φ 11 φ 7 φ 7 φ 11 φ
10 (20% reduction)
19 φ
8
φ 11 φ 4 φ 8 φ 11 φ 7 φ 8 φ 11 φ
11 (30% reduction)
21 φ 9 φ 12 φ 4 φ 9 φ 12 φ 8 φ 9 φ 12 φ
The above clock counts are values when HSCLK is chosen for the operating frequency (I2UM0CD2 to 0 bits of
the I2UM0MOD register = "000"). When 1/2HSCLK is chosen, the counts increase in proportion to the dividing
ratio.
When using the high-speed clock for the I2C operation, specify the following I2C operating clock frequency
depending on the mode and the reference frequency of the PLL oscillation.
Standard mode: HSCLK or 1/2HSCLK
Fast mode: HSCLK
1Mbps mode: HSCLK
φ: Clock cycle of 1/mHSCLK
1/mHSCLK: Set in I2UM0CD2 to I2UM0CD0 bits of the I2UM0MOD register.
(m=1, 2)
(Example)
HSCLK = 16 MHz
: φ≈62.50 ns
= 8 MHz
: φ≈125.00 ns
Table 12-6 Relationship between Communication Speeds and LSCLK Clock Counts
I2UM0MD1 I2UM0MD0
Communication
speed
t
CYC
t
HD:STA
t
LOW
t
HD:DAT
t
HIGH
t
SU:STA
t
SU:DAT
t
SU:STO
t
BUF
0 0 2.048kbps
16 φ 8 φ 8 φ 1 φ 8 φ 8 φ 7 φ 8 φ 8 φ
0 1 4.096kbps
8 φ 4 φ 4 φ 1 φ 4 φ 4 φ 3 φ 4 φ 4 φ
1 * 8.192kbps
4 φ 2 φ 2 φ 1 φ 2 φ 2 φ 1 φ 2 φ 2 φ
The above clock counts are values when LSCLK is chosen for the operating frequency (I2UM0CD2 to 0 bits of the
I2UM0MOD register = "100"). When 1/2 to 1/8LSCLK is chosen, the counts increase in proportion to the dividing ratio.
φ: Clock cycle of 1/mLSCLK
1/mLSCLK: Set in I2UM0CD2 to 0 bits of the I2UM0MOD register.
When LSCLK is used as the clock, the setting values of I2UM0DW1 and I2UM0DW0 bits of the I2UM0MOD register
are ignored.
*: 1 or 0
[Note]
Ÿ
When the slave device uses the clock stretch function which holds the I2CU0_SCL pin at "L" level, the
time t
CYC
and time t
LOW
are extended.