LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 434 / 882

ML62Q1000 Series User's Manual
Chapter 11 Serial Communication Unit
FEUL62Q1000 11-32
11.2.14 UARTn0 Status Register (UAn0STAT)
UAn0STAT is a specific function register (SFR) to indicate the state in the transmit/receive operation in UARTn0
full-duplex communiction mode and half-duplex communication mode.
Address: 0xF612(UA00STAT), 0xF632(UA10STAT), 0xF652(UA20STAT), 0xF672(UA30STAT),
0xF692(UA40STAT), 0xF6B2(UA50STAT)
Access: R/W
Access size: 8bit
Initial value: 0x00
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word
−
Byte
−
UAn0STAT
Bit
− − − − − − − − − −
Un0R
XF
Un0T
XF
Un0F
UL
Un0P
ER
Un0O
ER
Un0F
ER
R/W
R R R R R R R R R R R R R/W R/W R/W R/W
Initial
value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit no.
Bit symbol
name
Description
5 Un0RXF This bit is used to indicate the UART is receiving data in UARTn0 full-duplex communication
mode and half-duplex communication mode.
0: Date reception is stopped (initial value)
1: Data reception is in progress
4 Un0TXF This bit is used to indicate the UART is transmitting data in UARTn0 full-duplex
communication mode and half-duplex communication mode.
0: Data transmission is stopped (initial value)
1: Data transmission is in progress
3 Un0FUL This bit is used to indicate the state of the transmit/receive buffer in UARTn0 full-duplex
communication mode and half-duplex communication mode.
When the full-duplex communication mode is chosen, this bit becomes "1" when
transmission data is written to the SD0BUFH register and becomes "0" when the
transmission data is transferred to the shift register. To transmit data successively, check that
the Un0FUL bit is "0" before writing write the next transmit data to the SDn0BUFH register.
When the half-duplex mode is chosen, this bit becomes "1" when transmission data is written
to the SDn0BUFL register in the transmission mode and becomes "0" when the transmit data
is transferred to the shift register. To transmit data successively, check that the Un0FUL flag
is "0" before writing the next transmission data to the SD0BUFL register.
The Un0FUL bit is forcibly reset to “0” by writing “1” to this bit.
The Un0FUL bit is fixed to "0" in the receive mode.
・
Full-duplex communication mode
0: No data in the SD0BUFH register (initial value)
1: There is data in the SD0BUFH register
・
Half-duplex communication mode
0: No data in the SD0BUFL register (initial value)
1: There is data in the SD0BUFL register
2 Un0PER This bit is used to indicate a parity error in UARTn0 full-duplex communication mode and
half-duplex communication mode.
The parity of the received data and the parity bit added to the data are compared and if they
do not match, this bit becomes "1" and holds “1” until it is cleared by the software.
The Un0PER bit is forcibly reset to "0" by writing “1” to this bit.
The Un0PER is fixed to "0" in the transmit mode.
0: The parity error has not occurred (initial value)
1: The parity error has occurred