LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 235 / 882

ML62Q1000 Series User's Manual
Chapter 5 Interrupts
FEUL62Q1000 5-39
Table 5-2 List of Interrupt Sources (2/2)
Interrupt
source
number
(priority)
Register assignment
Interrupt
vector
address
Mask
External/
internal
source
Interrupt source
Interrupt
source
symbol
IRQ
(interrupt
request)
IE
(interrupt
enable)
ILC (interrupt
level)
35 IRQ4[6] IE4[6] ILC4[13:12] 0x004C Enabled
Internal
16-bit timer 2 interrupt TM2INT
36 IRQ4[7] IE4[7] ILC4[15:14] 0x004E Enabled
16-bit timer 3 interrupt TM3INT
37 IRQ5[0] IE5[0] ILC5[1:0] 0x0050 Enabled
Serial communication unit 20 interrupt SIU20INT
38 IRQ5[1] IE5[1] ILC5[3:2] 0x0052 Enabled
Serial communication unit 21 interrupt SIU21INT
39 IRQ5[2] IE5[2] ILC5[5:4] 0x0054
Enabled
Analogue Comparator 0
interrupt
CMP0INT
40 IRQ5[3] IE5[3] ILC5[7:6] 0x0056
Enabled
Analogue Comparator 1
interrupt
CMP1INT
41 IRQ5[4] IE5[4] ILC5[9:8] 0x0058 Enabled
Functional timer 4 interrupt FTM4INT
42 IRQ5[5] IE5[5] ILC5[11:10] 0x005A Enabled
Functional timer 5 interrupt FTM5INT
43 IRQ5[6] IE5[6] ILC5[13:12] 0x005C Enabled
16-bit timer 4 interrupt TM4INT
44 IRQ5[7] IE5[7] ILC5[15:14] 0x005E Enabled
16-bit timer 5 interrupt TM5INT
45 IRQ6[0] IE6[0] ILC6[1:0] 0x0060 Enabled
Internal
Serial communication unit 30 interrupt SIU30INT
46 IRQ6[1] IE6[1] ILC6[3:2] 0x0062 Enabled
Serial communication unit 31 interrupt SIU31INT
47 IRQ6[2] IE6[2] ILC6[5:4] 0x0064 Enabled
Serial communication unit 40 interrupt SIU40INT
48 IRQ6[3] IE6[3] ILC6[7:6] 0x0066 Enabled
Serial communication unit 41 interrupt SIU41INT
49 IRQ6[4] IE6[4] ILC6[9:8] 0x0068 Enabled
Functional timer 6 interrupt FTM6INT
50 IRQ6[5] IE6[5] ILC6[11:10] 0x006A Enabled
Functional timer 7 interrupt FTM7INT
51 IRQ6[6] IE6[6] ILC6[13:12] 0x006C Enabled
16-bit timer 6 interrupt TM6INT
52 IRQ6[7] IE6[7] ILC6[15:14] 0x006E Enabled
16-bit timer 7 interrupt TM7INT
53 IRQ7[0] IE7[0] ILC7[1:0] 0x0070
Enabled
Internal
Serial communication unit 50
interrupt
SIU50INT
54 IRQ7[1] IE7[1] ILC7[3:2] 0x0072
Enabled Serial communication unit 51
interrupt
SIU51INT
55 IRQ7[2] IE7[2] ILC7[5:4] 0x0074
Enabled
Low-speed time base counter
0 interrupt
LTBC0INT
56 IRQ7[3] IE7[3] ILC7[7:6] 0x0076 Enabled - -
57 IRQ7[4] IE7[4] ILC7[9:8] 0x0078
Enabled
Low-speed time base counter
1 interrupt
LTBC1INT
58 IRQ7[5] IE7[5] ILC7[11:10] 0x007A
Enabled
Low-speed time base counter
2 interrupt
LTBC2INT
59 IRQ7[6] IE7[6] ILC7[13:12] 0x007C Enabled Simplified RTC interrupt RTCINT
60 (low) IRQ7[7] IE7[7] ILC7[15:14] 0x007E Enabled - -
[Note]
Ÿ
The watchdog timer interrupt (WDTINT) is a non-maskable interrupt. If the non-maskable interrupt
occurs while an interrupt processing is in progress, abort the interrupt processing and proceed with
processing the non-maskable interrupt preferentially regardless of multiple interrupts enabled/disabled.
Ÿ
For failsafe, define unused all interrupt vectors. If an unused interrupt occurs, it may indicate the
possibility that the CPU went out of control. It is recommended to cause the watch dog timer (WDT) reset
to occur using the infinite loop to initialize the LSI.