LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 210 / 882

ML62Q1000 Series User's Manual
Chapter 5 Interrupts
FEUL62Q1000 5-14
5.2.7 Interrupt Request Register 23 (IRQ23)
IRQ23 is a specific function register (SFR) to request interrupts.
The bits are unwriteable when the products do not have the peripheral circuits and they return "0" for reading.
Each request flag of IRQ23 except for the QWDT bit becomes "1" when the interrupt request is generated, regardless of
the values of the interrupt enable register (IE23) and master interrupt enable flag (MIE). At that time, it requests the
interrupt to the CPU if the applicable flag of IE23 is "1" and the CPU accepts the interrupt if the MIE is "1" to go to the
interrupt routine.
Also, an interrupt can be generated by writing "1" to the request flag of IRQ23. In this case, the CPU goes to the interrupt
routine immedicately after the next one instruction is executed.
The applicable flag of IRQ23 becomes "0" automatically when the interrupt request is accepted by the CPU.
Address: 0xF02A(IRQ2/IRQ23), 0xF02B(IRQ3)
Access: R/W
Access size: 8/16bit
Initial value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word
IRQ23
Byte IRQ3 IRQ2
Bit
QTM1 QTM0
QFT
M1
QFT
M0
QI2C
M1
QI2C
M0
-
QEXT
X
-
QSA
D
-
QSIU
01
QSIU
00
QMC
S
QDM
A
QCB
U
R/W R/W R/W R/W R/W R/W R/W R R/W R R/W R R/W R/W R/W R/W R/W
Initial
value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit No.
Bit symbol
name
Description
15 QTM1 This bit controls to request the 16bit Timer 1 interrupt (TM1INT).
0: Not request the interrupt (initial value)
1: Request the interrupt
14 QTM0 This bit controls to request the 16bit Timer 0 interrupt (TM0INT).
0: Not request the interrupt (initial value)
1: Request the interrupt
13 QFTM1 This bit controls to request the Functional Timer 1 interrupt (FTM1INT).
0: Not request the interrupt (initial value)
1: Request the interrupt
12 QFTM0 This bit controls to request the Functional Timer 0 interrupt (FTM0INT).
0: Not request the interrupt (initial value)
1: Request the interrupt
11 QI2CM1 This bit controls to request the I
2
C Bus Master 1 interrupt (I2CM1INT).
0: Not request the interrupt (initial value)
1: Request the interrupt
10 QI2CM0 This bit controls to request the I
2
C Bus Master 0 interrupt (I2CM0INT).
0: Not request the interrupt (initial value)
1: Request the interrupt
9 - Reserved bit
8 QEXTX This bit controls to request the External expanded interrupt (EXTXINT).
0: Not request the interrupt (initial value)
1: Request the interrupt
7 - Reserved bit