LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 861 / 882

ML62Q1000 Series User’s Manual
Appendix E. List of Notes
FEUL62Q1000 E-2
Chapter 3 Reset Function
See Section 3.3.1 "Operation of Reset Function".
[ ] The voltage level supervisor function is only initialized at a reset input pin reset or power-on reset
(POR).
[ ] The BRK instruction reset only initializes the CPU if ELEVEL is 2 or higher. Peripheral circuits and other
circuits are not initialized. Use the reset input pin reset or the watchdog timer (WDT) reset to surely
initialize the LSI when an abnormality is detected.
[ ] In a BRECON 0 to 3 reset and SOFTRCON reset, only the corresponding peripheral circuits are
initialized. The CPU and other circuits are not initialized, and not transferred to the system reset mode.
See Section 3.3.2 "System Reset Mode".
[ ] In system reset mode, the contents of data memory (RAM) and SFRs that have an undefined initial
value are not initialized. Initialize them by the software.
See Section 3.3.3 "Reset Input Pin Reset".
[ ] To cause a reset to occur, assert the "L" level which is longer than the reset activation pulse width
(PRST).
[ ] The reset input pin has neither pull-up nor pull-down resistors built-in. Have a pull-up register externally.
See Section 3.3.4 "Power-on Reset".
[ ] Rise the VDD up to 1.8V or higher at the power up.
[ ] At the power-on, the reset is released when the power voltage (VDD) reaches the power-on reset
threshold voltage (VPOR) or above. The CPU begins to run the program with low-speed clock (LSCLK)
at approximately 32.768kHz. If switching the CPU to a high-speed clock, start the voltage level
supervisor (VLS) function and perform one of the following processes:
- Using the reset function of the VLS, retain the reset until the voltage reaches the level that enables
the high-speed clock operation.
- Using the voltage detection function of the VLS, detect the voltage level that enables the
high-speed clock operation (1.8 V or higher).
See Chapter 22 "Voltage Level Supervisor (VLS)" for the voltage level supervisor function.
[ ] At the power-off, the reset occurs when the power voltage (VDD) decreases below the power-on reset
threshold voltage (VPOR). In addition to that, bring the reset state using the voltage level supervisor
(VLS) before the voltage falls below the operating voltage limit described on the electrical characteristics
in the data sheet. When resuming the operation, make sure that the voltage has been returned within the
operating voltage range.
Chapter 4 Power Management
See Section 4.2.2 "Stop Code Acceptor (STPACP)".
[ ] Writing to the stop code acceptor is invalid on the condition both interrupt enable bits and interrupt
request bits are "1", it will not get enabled for entering to the STOP mode and STOP-D mode.
See Section 4.2.3 "Standby Control Register (SBYCON)".
[ ] The operating state does not enter the standby mode under the condition that both an interrupt enable
flag and an interrupt request flag are "1" that is requesting the interrupt to the CPU.
[ ] When an interrupt enabled in the interrupt enable registers (IE0 to IE7) is generated on the condition of
MIE flag of the program status word (PSW) is "0", it cancels the standby mode only and the CPU does
not go to the interrupt routine. For more details about MIE flag, see "nX-U16/100 Core Instruction
Manual".
[ ] Insert two NOP instructions in the next to the instruction of that sets HLT, STP, HLTH and STPD bit to
"1". The operation without the two NOP instructions is not guaranteed.
[ ] If two bits or more in the SBYCON are set to "1" at the same time, the setting are gets invalid and
continues the program rum mode.
[ ] When the CPU operation mode is "Wait mode", the PLL reference frequency is 24MHz and the MIE bit
is "0", choose 12MHz or slower as the SYSTEMCLK before entering the standby modes.
[ ] When choosing the low-speed crystal oscillation clock or low-speed external clock (LOSCM[1:0] of
FLMOD register is set to "01" or "11"), switch the SYSTEMCLK to the low-speed clock before setting
STP bit or STPD bit.