LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 379 / 882

ML62Q1000 Series User's Manual
Chapter 9 Functional Timer (FTM)
FEUL62Q1000 9-59
9.3.9 Changing Cycle, Event A/B, and Dead Time during Operation
The cycle, event A/B, and dead time can be updated by setting FTnP/ FTnEA/ FTnEB/ FTnDT registers.
The update timing is depending on the counter operation status and the counter value when writing data to the registers.
Counter operation
status when setting
the register
Counter value
when setting the
register
Update timing
Stop 0x0000 Updated at the counter start
Stop
Other than
0x0000
Updated at the start of cycle while the counter has been restarting
and FTCUDn bit is set to
"
1
"
.
Operating Any value
Updated at the start of cycle while the counter is operating and
FTCUDn bit is set to
"
1
"
.
Figure 9-18 shows the operating waveforms when the registers are updated while the counter stops(counter value is
0x0000) or the counter is operating.
Figure 9-19 shows the operating waveforms when the registers are updated while the counter stops(counter value is other
than 0x0000).
Figure 9-18 Update timing while the counter stops(counter value is 0x0000) or the counter is operating
FTnRUN
(2)
(1) Update the registers while the counter stops ( counter value is 0x0000)
(2) Each buffer is update at the start of counter operation
(3) Update the registers while the counter is operating
(4) Set FTCUDn bit to
"
1
"
(5) Each buffer is updated at the start of cycle and the FTCUDn bit gets cleared
(5)
Counter
Positive phase
Negative phase
FTnP
FTnEA
FTnEB
FTnDT
FTnUD
Buffer for cycle
Buffer for event A
Buffer for event B
Buffer for dead time
Buffer for cycle
Buffer for event A
Buffer for event B
Buffer for dead time
(1) (3)
(4)