LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 522 / 882

ML62Q1000 Series User's Manual
Chapter 14 DMA Controller
FEUL62Q1000 14-10
14.2.6 DMA Transfer Enable Register (DCEN)
DCEN is a special function register (SFR) used to enable the DMA transfer and set the behaivor in the case two channels
competed to work.
Address: 0xF720
Access: R/W
Access size: 8bit
Initial value:
0x00
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word
-
Byte
-
DCEN
Bit
- - - - - - - -
DCF
- - - - -
DC1EN DC0EN
R/W
- - - - - - - -
R/W
- - - - -
R/W R/W
Initial
value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit
No.
Bit symbol
name
Description
7 DCF This bit is used to choose the behavior of DMA, whether to fix the channel until the all counts
of transfer set in the DMA channel transfer count register (DCnTN) is completed or to follow
the priority order.
When this bit is set to "1", a transfer trigger of another channel is ignored until the current
transfer is completed.
If the DCnEN bits are enabled in both channels, the one with a transfer trigger generated first
starts the transfer. If a trigger is generated on both at the same time, channel 0 has the
priority.
0: DMA transfer channel is free (initial value)
1: DMA transfer channel is fixed
6 to 2 - Reserved bit
1, 0 DC1EN,
DC0EN
These bits are used to enable the DMA transfer channel n.
On the condition of this bit is set to "1", the DMA transfer starts when a transfer trigger is
generated.
When the transfer count set in the DMA channel transfer count register (DCnTN) is
completed, the DCnEN bits are automatically reset to "0".
Reset the DCnEN bit to "0" to stop the DMA transfer.
0: Stop the DMA channel n transfer (initial value)
1: Enable the DMA channel n transfer
[Note]
•
Set the DCF bit when the transfer is disabled (DCnEN bit = 0). The DCnTN is not writable if the transfer is
enabled (DCnEN bit = 1).
•
When the specified transfer count is completed, the channel corresponding bit of the DMA interrupt
status register (DSTATL) is set to "1". Be sure to clear the status bit (DCnISTA) by using the DMA
interrupt status clear register (DICLR) before enabling the next DMA transfer. When the status is "1", the
DMA transfer is unenabled. Clear the status bit (DCnISTA) regardless using or not using the DMA
interrupt.