LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 273 / 882

ML62Q1000 Series User's Manual
Chapter 6 Clock Generation Circuit
FEUL62Q1000 6-25
6.3.5 Switching Low-speed clock
Figure 6-15 shows a flow chart of the low-speed clock switching process (low-speed RC oscillation circuit
à
low-speed
crystal oscillation circuit). Follow the flow chart below to check the state of the low-speed clock after releasing the
STOP/STOP-D mode. When switching the system clock to the high-speed clock, first switch the low-speed clock to the
low-speed crystal oscillation circuit. This circuit is unavailable on the ML62Q1300 group.
Figure 6-15 Flow Chart for switching the Low-speed clock
(RC oscillation clock to Crystal oscillation/External clock)
Read LOSCS
LOSCS=0x0
Write 0x1 to LOSCB
NOP instruction x2
LOSCS=0x1
End switching to low-speed crystal
oscillation clock
*1*2
Read LOSCB
LOSCB=0x0
LOSCB=0x1
LOSCM[1:0]=0x0
Read LOSCM[1:0]
Read LOSCB
LOSCB=0x0
LOSCB=0x1
Write "1" to ECBU bit of Interrupt
Enable register 23
*5
Process for abnormality
Write 0x0 to LOSCM[1:0]
Handle appropriately for the
application.
Wait for clock
backup interrupt
2s or more
Write 0x1
*1
to LOSCM[1:0]
*1: Read "0x1" with "0x3" and read "low-speed oscillation clock" with "low-speed external clock" when switching to the "low-speed
external clock".
*2: Do not control the power managements (write to SBYCON register) and the clock managements (write to LOSCM[1:0] of
FLMOD register and write to SELSCLK of FCON register) before the switching to the low-speed crystal oscillation clock.
*3: There are four interrupt sources. After switching to the low-speed crystal oscillation clock, handle them following to the flow of
the interrupt.
1)
When counting for the clock stabilization is completed after setting
LOSCM[1:0]
to "
0x1
".
2) When counting for the clock stabilization is completed after releasing STOP/STOP-D mode.
3) If an abnormal condition happened on the low-speed crystal circuit and the oscillation stopped for 8ms or longer.
4) If an abnormal condition happened on the low-speed crystal circuit and returned to normal oscillating in stable.
*4: Clear the setting once because it’s unknown whether the state is in backup clock or the state before setting the crystal oscillation
clock.
*5: Enable the interrupt after ending the reset release process because it’s unknown whether the state is in backup clock or the
state before setting the crystal oscillation clock.
Write 0x0 to LOSCM[1:0]
*4
Start (Reset release, Wake-up by
STOP/STOP-D)
Handle appropriately for
the application.
Yes
LOSCM[1:0]
≠
0x0
Write "1" to ECBU bit of Interrupt
Enable register 23
*5
LOSCM[1:0]==0x1
*1
No
Interrupt occur
*3
Working with low-speed crystal
oscillation clock
*1