LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 303 / 882

ML62Q1000 Series User's Manual
Chapter 8 16-Bit Timer
FEUL62Q1000 8-12
8.2.6 16-Bit Timer n Interrupt Clear Register (TMHnIC: n = 0 to 7)
TMHnIC is a write-only specific function register (SFR) to clear the status of the interrupt used in the 8-bit timer mode.
This is not used in the 16-bit mode.
If THnHIC bit(bit1) or THnLIC bit(bit0) of TMHnIC register is set to "1", the interrupt request indicated by the same
number of bit in the TMHnIS register is cleared.
Also, if the THnIR bit is set to "1" it generates the interrupt when there is a unhandled interrupt request in the TMHnIS
register. TMHnIC register is write-only register and returns always "0x0000" for reading.
Address: 0xF340(TMH0ICL/TMH0IC), 0xF341(TMH0ICH), 0xF342(TMH1ICL/TMH1IC), 0xF343(TMH1ICH)
0xF344(TMH2ICL/TMH2IC), 0xF345(TMH2ICH), 0xF346(TMH3ICL/TMH3IC), 0xF347(TMH3ICH)
0xF348(TMH4ICL/TMH4IC), 0xF349(TMH4ICH), 0xF34A(TMH5ICL/TMH5IC), 0xF34B(TMH5ICH)
0xF34C(TMH6ICL/TMH6IC), 0xF34D(TMH6ICH), 0xF34E(TMH7ICL/TMH7IC), 0xF34F(TMH7ICH)
Access: W
Access size: 8/16 bit
Initial value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word
TMHnIC
Byte
TMHnICH TMHnICL
Bit
- - - - - - - -
THn
IR
- - - - -
THn
HIC
THn
LIC
R/W R R R R R R R R W R R R R R W W
Initial
value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit no.
Bit symbol
name
Description
15 to 8 - Reserved bit
7 THnIR This bit is used to generate a unhandled interrupt request of the upper side 8bit timer or lower
side 8bit timer (when a not-target interrupt request for clear remains in the TMHnIS register)
Writing "0": Invalid
Writing "1": Generate the unhandled interrupt request.
6 to 2 - Reserved bit
1 THnHIC This bit is used to clear the interrupt request of the upper side 8bit timer.
Writing "0": Invalid
Writing "1": Clear the interrupt request status
0 THnLIC This bit is used to clear the interrupt request of the lower side 8bit timer.
Writing "0": Invalid
Writing "1": Clear the interrupt request status