LAPIS Semiconductor ML62Q1000 Series, User Manual, Page: 340 / 882

ML62Q1000 Series User's Manual
Chapter 9 Functional Timer (FTM)
FEUL62Q1000 9-20
9.2.9 FTMn Clock Register (FTnCLK: n=0 to 7)
FTnCLK is a specific function register (SFR) to set the timer clock and count clock of the FTMn.
The timer clock is used for sampling the external trigger input and for detecting the edge of the external clock input.
The count clock is used for the count operatiion and control of the output waveform.
Address: 0xF470(FT0CLKL/FT0CLK), 0xF471(FT0CLKH),
0xF472(FT1CLKL/FT1CLK), 0xF473(FT1CLKH),
0xF474(FT2CLKL/FT2CLK), 0xF475(FT2CLKH),
0xF476(FT3CLKL/FT3CLK), 0xF477(FT3CLKH),
0xF478(FT4CLKL/FT4CLK), 0xF479(FT4CLKH),
0xF47A(FT5CLKL/FT5CLK), 0xF47B(FT5CLKH),
0xF47C(FT6CLKL/FT6CLK), 0xF47D(FT6CLKH),
0xF47E(FT7CLKL/FT7CLK), 0xF47F(FT7CLKH)
Access: R/W
Access size: 8/16 bit
Initial value: 0x0000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Word
FTnCLK
Byte
FTnCLKH FTnCLKL
Bit
− − − − −
FTnX
CK2
FTnX
CK1
FTnX
CK0
−
FTnC
KD2
FTnC
KD1
FTnC
KD0
FTnE
X
− −
FTnC
K0
R/W R R R R R R/W R/W R/W R R/W R/W R/W R/W R R R/W
Initial
value
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit no.
Bit symbol
name
Description
15 to
11
- Reserved bit
10 to 8 FTnXCK2 to
FTnXCK0
These bits are used to choose the external clock input used when the FTnEX bit is "1".
000: External clock 0 input (EXTRG0) (Initial)
001: External clock 1 input (EXTRG1)
010: External clock 2 input (EXTRG2)
011: External clock 3 input (EXTRG3)
100: External clock 4 input (EXTRG4)
101: External clock 5 input (EXTRG5)
110: External clock 6 input (EXTRG6)
111: External clock 7 input (EXTRG7)
7 - Reserved bit
6 to 4 FTnCKD2 to
FTnCKD0
These bits are used to choose frequency dividing ratio for the count clock in the FTMn.
When the FTnEX bit is "1", this setting is invalid.
000: No dividing (Initial value)
001: 1/2 of the timer clock "FTnTCK"
010: 1/4 of the timer clock "FTnTCK"
011: 1/8 of the timer clock "FTnTCK"
100: 1/16 of the timer clock "FTnTCK"
101: 1/32 of the timer clock "FTnTCK"
110: 1/64 of the timer clock "FTnTCK"
111: 1/128 of the timer clock "FTnTCK"
3 FTnEX This bit is used to choose the count clock (FTnCK) in the FTMn.
0: Count the clock divided by a ratio, chosen by FTnCK0 bit and FTnCKD2-0 bits. (initial
value)
1: Count the clock at the rising edge of the external triggers EXTRGn (n=0 to 7) chosen
by the FTnXCK2-0 bits.